JPH0629808A - Method for preventing malfunction at application of power for transistor - Google Patents

Method for preventing malfunction at application of power for transistor

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Publication number
JPH0629808A
JPH0629808A JP4184232A JP18423292A JPH0629808A JP H0629808 A JPH0629808 A JP H0629808A JP 4184232 A JP4184232 A JP 4184232A JP 18423292 A JP18423292 A JP 18423292A JP H0629808 A JPH0629808 A JP H0629808A
Authority
JP
Japan
Prior art keywords
voltage
transistor
thyristor
base
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4184232A
Other languages
Japanese (ja)
Inventor
Morihiro Kuruma
守宏 来馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4184232A priority Critical patent/JPH0629808A/en
Publication of JPH0629808A publication Critical patent/JPH0629808A/en
Pending legal-status Critical Current

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  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To avoid thyristor mis-ignition by preventing malfunction in the transient state such as application of control power supply to a thyristor trigger control transistor(TR). CONSTITUTION:A Zener diode ZD having a prescribed Zener voltage VZD is connected in series with a base signal application path of a TR forming an ignition signal of a thyristor through the conduction in the opposite polarity with the prescribed base current conduction direction. Furthermore, an external induced voltage absorption capacitor C having a proper static capacitance is connected between the base of the TR and a control reference potential point. Thus, malfunction in the transient state of application of power is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電圧形インバータ装置
の直流中間回路平滑コンデンサに対する突入電流限流用
抵抗の短絡等に使用されるサイリスタの点弧信号形成用
トランジスタに対する制御電源投入時等の過渡時の誤動
作防止方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transient of a thyristor used for short-circuiting an inrush current limiting resistor for a DC intermediate circuit smoothing capacitor of a voltage source inverter device when a control power source is turned on. The present invention relates to a method for preventing malfunctions during operation.

【0002】[0002]

【従来の技術】従来、前記の如きサイリスタの点弧回路
としては図3の回路図に例示する如きものが知られてい
る。図3においてSCRは直流回路に挿入されたサイリ
スタ、PCはフォトカプラ、TRはトランジスタ、R1
〜R3 は抵抗、またVCCは制御電源電圧、Mは制御上の
基準電位、VR3は前記抵抗R3 の両端電圧即ち前記トラ
ンジスタのベースとエミッタ間の電圧、VFBは演算装置
CPUの出力ポートの電圧、VFSは該CPUの出力ポー
トより出力される前記サイリスタの点弧制御信号電圧で
ある。
2. Description of the Related Art Conventionally, as an ignition circuit for a thyristor as described above, the one exemplified in the circuit diagram of FIG. 3 is known. In FIG. 3, SCR is a thyristor inserted in a DC circuit, PC is a photocoupler, TR is a transistor, R 1
˜R 3 is a resistor, V CC is a control power supply voltage, M is a reference potential for control, V R3 is a voltage across the resistor R 3 , that is, a voltage between the base and emitter of the transistor, and V FB is a voltage of the arithmetic unit CPU. The voltage of the output port, V FS, is the firing control signal voltage of the thyristor output from the output port of the CPU.

【0003】図示の如く、前記CPUの出力する信号電
圧VFSによってトランジスタTRが導通し、該導通によ
りフォトカプラPCを介した信号電圧がそのゲートに印
加されることによりサイリスタSCRは導通状態とな
る。なお、前記電圧VFBにおいては前記の各抵抗R1
3 による前記電圧VCCの分圧電圧がバイアス電圧とし
て重畳されており、前記信号電圧VFSによるトランジス
タTRの動作加速を図っている。
As shown in the figure, the transistor TR is made conductive by the signal voltage V FS output from the CPU, and the signal voltage is applied to the gate of the thyristor SCR via the photocoupler PC due to the conduction, so that the thyristor SCR becomes conductive. . In addition, at the voltage V FB , the resistors R 1 to
The divided voltage of the voltage V CC due to R 3 is superposed as a bias voltage to accelerate the operation of the transistor TR due to the signal voltage V FS .

【0004】即ち図示の如く、従来のサイリスタ点弧回
路はその電源投入時等過渡時の制御電圧動揺等に対する
誤動作防止対策を特に講じるものではなかった。
That is, as shown in the figure, the conventional thyristor ignition circuit does not particularly take measures to prevent malfunctions due to fluctuations in the control voltage during a transition such as when the power is turned on.

【0005】[0005]

【発明が解決しようとする課題】例えば、図3に示すサ
イリスタSCRが電圧形インバータ装置の直流中間回路
平滑コンデンサに対する突入電流限流用抵抗の短絡に使
用されるものであれば、通常、前記の制御電圧VCCは前
記コンデンサの端子電圧を入力とするDC/DCコンバ
ータの出力電圧として得られるものであり、また、前記
サイリスタの所要導通時期は前記コンデンサの端子電圧
が所定値まで増大した時点となされており該コンデンサ
の充電開始時点よりも遅れることになる。該両時点間に
おいて前記DC/DCコンバータはその入力電圧が増大
中の過渡動作状態を経過することになり、その出力電圧
に関して一過性電圧増分の重畳により一様性を欠いた不
規則な増大経過をなすことがある。
If, for example, the thyristor SCR shown in FIG. 3 is used for short-circuiting the inrush current limiting resistor with respect to the DC intermediate circuit smoothing capacitor of the voltage type inverter device, the above-mentioned control is usually performed. The voltage V CC is obtained as an output voltage of a DC / DC converter having the terminal voltage of the capacitor as an input, and the required conduction time of the thyristor is the time when the terminal voltage of the capacitor increases to a predetermined value. Therefore, it will be later than the charging start time of the capacitor. Between the two time points, the DC / DC converter goes through a transient operating state in which its input voltage is increasing, and its output voltage is irregularly increased irregularly due to the superposition of transient voltage increments. It may make progress.

【0006】従って前記サイリスタの点弧制御用トラン
ジスタTRは、そのベース電圧VR3が前記の如き制御電
圧VCCの不規則な増大或いは何らかの外部誘導電圧の重
畳により該トランジスタを導通させるに要する値を偶発
的に超過する場合には、前記信号電圧VFSの印加によっ
て指定されるその所定の導通時期以前に望ましくない導
通状態となり、斯様なトランジスタの偶発的な導通によ
り直流回路に挿入された前記のサイリスタSCRもまた
前記信号電圧VFSの指定するその所定点弧時点以前に継
続的な導通状態となる誤動作をなす危険がある。
Therefore, the firing control transistor TR of the thyristor has a value required for the base voltage V R3 to make the transistor conductive by the irregular increase of the control voltage V CC or the superposition of some external induction voltage. In the event of an accidental overshoot, an undesired conduction state will occur prior to its predetermined conduction time specified by the application of the signal voltage V FS , and the accidental conduction of such a transistor will cause the transistor to be inserted into the DC circuit. The thyristor SCR also has a risk of malfunction due to continuous conduction before the predetermined ignition point designated by the signal voltage V FS .

【0007】因みに、図4は上記の如き誤動作の発生模
様を前記図3との対応において示す動作波形図であり、
図4の(イ)は時刻t1 の前後に一過性電圧増分が重畳
した前記制御電圧VCCの変動模様を示し、図4の(ロ)
は同図(イ)の如く変化する該制御電圧VCCの抵抗R1
〜R3 による分圧電圧と前記サイリスタ点弧信号電圧V
FSとの合成電圧VFBの変動模様を示し、図4の(ハ)は
該合成電圧VFBの抵抗R2 とR3 とによる分圧電圧とし
て得られる前記トランジスタTRのベース電圧VR3が前
記電圧VFBと相似となり且つ時刻t1 〜t2 間と時刻t
3 以降とにおいては該トランジスタを導通させ得る最低
のベース電圧VbMを超過する変動模様を示すものであ
る。
Incidentally, FIG. 4 is an operation waveform diagram showing a pattern of occurrence of the above-mentioned malfunction in correspondence with FIG.
FIG. 4A shows a variation pattern of the control voltage V CC on which a transient voltage increment is superimposed before and after time t 1 , and FIG.
Is the resistance R 1 of the control voltage V CC that changes as shown in FIG.
~ R 3 divided voltage and the thyristor firing signal voltage V
4 shows a variation pattern of the combined voltage V FB with FS, and FIG. 4C shows the base voltage V R3 of the transistor TR obtained as a divided voltage by the resistors R 2 and R 3 of the combined voltage V FB. It is similar to the voltage V FB and is between time t 1 and t 2 and time t.
From 3 onward, it shows a variation pattern that exceeds the lowest base voltage V bM that can make the transistor conductive.

【0008】更に図4の(ニ)は前記の如きベース電圧
R3の変化を受け時刻t1 〜t2 間と時刻t3 以降とに
おいて前記トランジスタTRが導通(on)状態となる
模様を示し、図4の(ホ)は該トランジスタの導通状態
を受け前記サイリスタSCRが時刻t1 より継続的な導
通(on)状態に入る模様を示すものである。ここに前
記サイリスタSCRの時刻t1 〜t3 間における導通状
態は前記トランジスタTRの時刻t1 における誤動作に
起因する望ましくないものとなる。
Further, (d) of FIG. 4 shows that the transistor TR becomes conductive (on) between time t 1 and t 2 and after time t 3 due to the change of the base voltage V R3 as described above. 4, (e) shows that the thyristor SCR receives the conduction state of the transistor and enters the continuous conduction state (on) from the time t 1 . Here, the conduction state of the thyristor SCR between the times t 1 and t 3 becomes undesired due to the malfunction of the transistor TR at the time t 1 .

【0009】上記に鑑み本発明は、前記の如きサイリス
タ誤点弧の原因となる該サイリスタの点弧制御用トラン
ジスタに対する電源投入時等過渡時の誤動作防止方法の
提供を目的とするものである。
In view of the above, it is an object of the present invention to provide a method of preventing malfunction of the thyristor, which causes the false ignition of the thyristor, during a transition such as power-on for the ignition control transistor.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に本発明のトランジスタの電源投入時誤動作防止方法
は、その導通動作によってサイリスタの点弧信号を形成
するトランジスタに対してその電源投入時等の過渡時の
誤動作を防止させるものであって、所定のツェナ電圧を
有する定電圧ダイオードを前記トランジスタのベース信
号印加経路に直列に所定のベース電流通電方向と逆極性
にて接続し且つ該トランジスタのベースと制御上の基準
電位点との間に所定の静電容量を有するコンデンサを接
続するものとする。
In order to achieve the above object, a method of preventing malfunction of a transistor at power-on according to the present invention is applied to a transistor which forms an ignition signal of a thyristor by its conductive operation at power-on. Of a constant voltage diode having a predetermined Zener voltage is connected in series to the base signal application path of the transistor in the reverse polarity of the predetermined base current conduction direction, and A capacitor having a predetermined electrostatic capacity is connected between the base and a control reference potential point.

【0011】[0011]

【作用】前記の如く、サイリスタ点弧制御用トランジス
タのベース電圧における異常な増大,即ち制御電圧自体
の一過性の増大或いは何らかの外部誘導電圧の重畳等の
通常の制御信号印加以外の原因によるベース電圧の増大
は、サイリスタ誤点弧の原因となる。
As described above, an abnormal increase in the base voltage of the thyristor firing control transistor, that is, a transient increase in the control voltage itself or a superimposition of some external induction voltage, etc. The increased voltage causes a false firing of the thyristor.

【0012】従って本発明は、所定の制御信号電圧と抵
抗を介して与えられた制御電源電圧との加算電圧を定電
圧ダイオードと複数の抵抗との直列接続を介して前記ト
ランジスタのベースに印加し、前記の加算電圧と定電圧
ダイオードのツェナ電圧との差電圧の適当な抵抗分圧電
圧を以て前記トランジスタのベース電圧となすと共に、
前記制御電源電圧の予想される一過性増大時においても
前記ベース電圧の値を前記トランジスタを導通させ得る
最小値より小となし,且つ前記の制御信号電圧印加時に
は該最小値よりも充分に大なるベース電圧が得られる如
く前記のツェナ電圧を選択するものであり、更に前記ト
ランジスタのベースに近接して該ベースへの外部誘導電
圧の吸収用コンデンサを設けることにより前記の如きサ
イリスタ誤点弧の防止を図るものである。
Therefore, according to the present invention, an added voltage of a predetermined control signal voltage and a control power supply voltage given through a resistor is applied to the base of the transistor through a series connection of a constant voltage diode and a plurality of resistors. , A base voltage of the transistor is formed by using an appropriate resistance-divided voltage of a difference voltage between the added voltage and the zener voltage of the constant voltage diode.
The value of the base voltage is set to be smaller than the minimum value that allows the transistor to conduct even when the control power supply voltage is expected to transiently increase, and is sufficiently larger than the minimum value when the control signal voltage is applied. The zener voltage is selected so that the base voltage can be obtained, and a capacitor for absorbing an external induction voltage to the base is provided in the vicinity of the base of the transistor to prevent the thyristor from false firing. It is intended to prevent it.

【0013】[0013]

【実施例】以下本発明の実施例を図1の回路図と該図1
に対応する図2の動作波形図とに従って説明する。なお
図1においては図3に示す従来技術の実施例の場合と同
一機能の構成要素に対しては同一の表示符号を付してい
る。図1は図3の回路図において、トランジスタTRへ
のベース信号印加経路をなす抵抗R2 とR3 との間にそ
のツェナ電圧をVZDとなす定電圧ダイオードZDを図示
の極性にて直列に接続すると共に該抵抗R3 に並列に外
部誘導電圧吸収用のコンデンサCを接続したものであ
る。
1 is a circuit diagram of FIG. 1 and FIG.
2 will be described with reference to the operation waveform diagram of FIG. In FIG. 1, constituent elements having the same functions as those in the embodiment of the prior art shown in FIG. 3 are designated by the same reference numerals. In the circuit diagram of FIG. 3, a constant voltage diode ZD whose Zener voltage is V ZD is connected in series between resistors R 2 and R 3 forming a base signal application path to the transistor TR in the polarity shown. A capacitor C for absorbing an external induced voltage is connected in parallel with the resistor R 3 in addition to the connection.

【0014】図1に示す回路構成により、トランジスタ
TRのベース電圧VR3はCPU出力ポート電圧VFBが前
記ツェナ電圧VZD以下の状態では前記基準電位Mに保持
され、また該両電圧がVFB>VZDの関係にあれば下記の
式(1)に従う値となる。 VR3=(VFB−VZD)R3 /(R2 +R3 )…………(1) なお前記ツェナ電圧VZDは、所定のサイリスタ点弧制御
信号電圧VFSがCPU出力ポートから出力されてVFB
FSとなった場合に前記ベース電圧VR3が前記トランジ
スタTRを充分に導通状態となし得る値となる様に選定
される。
With the circuit configuration shown in FIG. 1, the base voltage V R3 of the transistor TR is held at the reference potential M when the CPU output port voltage V FB is equal to or lower than the Zener voltage V ZD , and both voltages are V FB. If there is a relation of> V ZD, the value is in accordance with the following equation (1). V R3 = (V FB −V ZD ) R 3 / (R 2 + R 3 ) ... (1) The Zener voltage V ZD is the predetermined thyristor firing control signal voltage V FS output from the CPU output port. Done and V FB =
When V FS is reached, the base voltage V R3 is selected to be a value that can make the transistor TR sufficiently conductive.

【0015】次に図2の動作波形図において、図2の
(イ)は前記制御電圧VCCの変動模様を示すものであり
前記図4の(イ)と同一である。また図2の(ロ)は前
記電圧VFBの変動模様を示すものであり、前記の両電圧
CCとVZDとがVCC=VZDとなる時点迄は略VFB=VCC
にて推移し、VCC>VZDとなる時点から時刻t3 までは
下記の式(2)に従う値となる。
Next, in the operation waveform diagram of FIG. 2, (a) of FIG. 2 shows a variation pattern of the control voltage V CC , which is the same as (a) of FIG. 2B shows a variation pattern of the voltage V FB , which is approximately V FB = V CC until both the voltages V CC and V ZD become V CC = V ZD.
The value changes according to the following equation (2) from the time when V CC > V ZD to the time t 3 .

【0016】 VFB=VZD+(VCC−VZD)(R2 +R3 )/(R1 +R2 +R3 )…(2) 更に、図2の(ハ)に示す前記電圧VR3は前記のVCC
ZDとなる時点までは零(基準電位M)となり、該時点
以降時刻t3 までは上記の式(1)に従う値となって前
記の如き所要最低のベース電圧VbMより小となる。従っ
て、前記のトランジスタTRとサイリスタSCRそれぞ
れの導通模様を示す図2の(ニ)と(ホ)とにおいて
は、対応する前記図4の(ニ)と(ホ)に示す如き時刻
1 〜t2 間におけるトランジスタTRの導通状態と時
刻t1 〜t3間におけるサイリスタSCRの誤導通状態
とは何れも消滅することになる。
V FB = V ZD + (V CC −V ZD ) (R 2 + R 3 ) / (R 1 + R 2 + R 3 ) ... (2) Further, the voltage V R3 shown in FIG. V CC =
Until such time as the V ZD is zero (reference potential M), and the up said time point after time t 3 becomes smaller than the base voltage V bM of a required minimum the such of a value according to formula (1) above. Therefore, in (d) and (e) of FIG. 2 showing the conduction patterns of the transistor TR and the thyristor SCR, the corresponding times t 1 to t as shown in (d) and (e) of FIG. Both the conduction state of the transistor TR during the period 2 and the erroneous conduction state of the thyristor SCR between the times t 1 and t 3 disappear.

【0017】即ち、電源投入時における前記の如き制御
電圧VCCの一過性電圧増大に起因する前記のトランジス
タTRとサイリスタSCRとの誤動作は回避される。
That is, the malfunction of the transistor TR and the thyristor SCR due to the transient increase of the control voltage V CC as described above when the power is turned on is avoided.

【0018】[0018]

【発明の効果】本発明によれば、その導通動作によりサ
イリスタの点弧信号を形成するトランジスタに対し、所
定のツェナ電圧を有する定電圧ダイオードを該トランジ
スタのベース信号印加経路に直列に所定のベース電流通
電方向と逆極性にて接続し且つ該トランジスタのベース
と制御上の基準電位点との間に適当な静電容量を有する
コンデンサを外部誘導電圧吸収用に接続することによ
り、電源投入時等の過渡時において或いはノイズ等何ら
かの外部誘導電圧に対して前記トランジスタの誤動作防
止を簡易且つ安価に実現することが可能となり、前記の
サイリスをその回路構成要素となす各種装置の運転にお
ける信頼性の向上を図ることが出来る。
According to the present invention, a constant voltage diode having a predetermined Zener voltage is connected to a transistor forming a firing signal of a thyristor by its conduction operation in series with a predetermined base in a base signal application path of the transistor. At the time of power-on, etc., by connecting a capacitor having an appropriate electrostatic capacity between the base of the transistor and the reference potential point for control, which is connected in the opposite polarity to the direction of current flow It is possible to easily and inexpensively prevent the malfunction of the transistor at the time of the transient state or against some external induced voltage such as noise, and improve the reliability of the operation of various devices using the thyris as the circuit component. Can be planned.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示すサイリスタ点弧回路の回
路図
FIG. 1 is a circuit diagram of a thyristor firing circuit showing an embodiment of the present invention.

【図2】図1に示す回路各部諸量の動作波形図FIG. 2 is an operation waveform diagram of various components of the circuit shown in FIG.

【図3】従来技術の実施例を示すサイリスタ点弧回路の
回路図
FIG. 3 is a circuit diagram of a thyristor firing circuit showing an embodiment of the prior art.

【図4】図3に示す回路各部諸量の動作波形図FIG. 4 is an operation waveform diagram of various components of the circuit shown in FIG.

【符号の説明】[Explanation of symbols]

C 外部誘導電圧吸収用コンデンサ CPU 演算装置 PC フォトカプラ R 抵抗(R1 ,R2 ,R3 ) SCR サイリスタ TR トランジスタ ZD 定電圧ダイオードC External inductive voltage absorption capacitor CPU CPU PC photocoupler R resistance (R 1 , R 2 , R 3 ) SCR thyristor TR transistor ZD constant voltage diode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】その導通動作によってサイリスタの点弧信
号を形成するトランジスタの電源投入時誤動作防止方法
であって、所定のツェナ電圧を有する定電圧ダイオード
を前記トランジスタのベース信号印加経路に直列に所定
のベース電流通電方向と逆極性にて接続すると共に、該
トランジスタのベースと制御上の基準電位点との間に所
定の静電容量を有するコンデンサを接続することを特徴
とするトランジスタの電源投入時誤動作防止方法。
1. A method for preventing a malfunction of a transistor, which forms an ignition signal of a thyristor by the conduction operation thereof at power-on, in which a constant voltage diode having a predetermined Zener voltage is connected in series to a base signal application path of the transistor. When the power supply of the transistor is turned on, a capacitor having a predetermined electrostatic capacity is connected between the base of the transistor and a reference potential point for control, in addition to connecting the base current in the opposite polarity direction. Malfunction prevention method.
JP4184232A 1992-07-13 1992-07-13 Method for preventing malfunction at application of power for transistor Pending JPH0629808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4184232A JPH0629808A (en) 1992-07-13 1992-07-13 Method for preventing malfunction at application of power for transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4184232A JPH0629808A (en) 1992-07-13 1992-07-13 Method for preventing malfunction at application of power for transistor

Publications (1)

Publication Number Publication Date
JPH0629808A true JPH0629808A (en) 1994-02-04

Family

ID=16149690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4184232A Pending JPH0629808A (en) 1992-07-13 1992-07-13 Method for preventing malfunction at application of power for transistor

Country Status (1)

Country Link
JP (1) JPH0629808A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8286509B2 (en) 2007-01-29 2012-10-16 Tokyo Denki University Tactile sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8286509B2 (en) 2007-01-29 2012-10-16 Tokyo Denki University Tactile sensor

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