JPH0629506A - Semiconductor energy detector - Google Patents

Abstract

PURPOSE:To provide a semiconductor energy detector whose sensitivity to an energy beam such as short-wavelength light or the like is high. CONSTITUTION:A P-type epitaxial-layer 24 provided with a CCD 31 is formed on a silicon wafer 35. A P<+> layer 27 is formed in the P-type epitaxial layer 24. A silicon wafer 29 is installed on the upper side of the P-type epitaxial layer 24. In the silicon wafer 29, only a region to photodetect short-wavelength light incident from a window member 40 in a package 28 is etched and removed, and an opening is formed. In a rear-irradiation type semiconductor energy detector provided with the above-mentioned structure, an accumulation state is maintained. Consequently, the detector is made a stable detector whose sensitivity to the short-wavelength light is uniform all over its inside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backside irradiation type charge transfer type semiconductor energy detector which is effective for irradiation of energy rays having an extremely large absorption coefficient such as ultraviolet rays, radiation and particle beams.

[0002]

2. Description of the Related Art A charge transfer device (CCD) sequentially sends an analog charge group in one direction from the outside at a speed synchronized with a clock pulse. It is an extremely sophisticated functional device that can be converted into a series signal. However, in order to extract the two-dimensional image information as a time-series signal, it is necessary to devise a device configuration. If the charge is transferred while the device is still being irradiated with light, the photo-excited charge and the transferred charge are mixed at each place, and a phenomenon called so-called smear occurs and the video signal deteriorates. . In order to avoid this, a so-called time division operation that temporally divides the period of irradiating light (charge accumulation period) and the time of transferring charges (charge transfer period) can be considered. Therefore, the time when the video signal is output is limited to the charge transfer time, and becomes an intermittent signal.

Generally, as a practical image pickup device,
Frame transfer (FT), full frame transfer (FF)
The three methods of T) and interline transfer (IT) are typical. Of these, the full frame transfer method is mainly used for measurement.

The full frame transfer system will be described below. 10 and 11 show the structure of the full frame transfer system. FIG. 10 is a top view thereof, and FIG. 11 is a sectional view of a main part thereof. As shown in FIG. 10, in this method, the charge transfer channels are divided in the vertical direction by the channel stop diffusion layers 1 formed on the substrate to form pixel columns corresponding to the number of horizontal pixels. On the other hand, the transfer electrode group 2 is arranged orthogonal to the channel stop diffusion layer 1. In the above-mentioned FT method, this electrode group is grouped into two upper and lower parts, and the upper half is used as a light-receiving CCD and the lower half is used as a CCD for temporarily storing signal charges, but in the full frame transfer type CCD shown in FIG. There is no storage. Therefore, during the time when the charges are transferred, that is, during the reading time, it is necessary to close the shutter so that the light does not enter the CCD. Note that three overflow drains 5 are formed between the four vertical pixel columns.

As shown in FIG. 11, one pixel is surrounded by a number of electrodes 20 and a channel stop diffusion layer 1 corresponding to the number of phases (4) of clock pulses (φ _{1 to} φ ₄ ) constituting one stage of CCD. The area will be The vertical transfer clock pulse electrode group 2 supplies clock pulses φ _{1 to} φ ₄ to the polysilicon electrode 20. An interlayer insulating film 19 made of PSG (phosphorus glass) is deposited on the upper surface of the polysilicon electrode 20, and the gate oxide film 2 is formed between the electrode 20 and the silicon substrate 22.
1 is interposed.

When light is incident on the light receiving region, the signal charges excited as shown in FIG. 11 are one transfer electrode (storage electrode), that is, the potential under the polysilicon electrode 20 to which the rising clock pulse φ ₁ is applied. Collected in well 3.

When the charge accumulation time for converting an optical signal into a signal charge is over, the clock voltages φ _{1 to} φ ₄ given to the vertical transfer electrode group 2 on the light receiving region sequentially rise, and the reading of the signal charge is started. It However, in the full frame transfer CCD, as described above, there is no so-called storage section other than the light receiving section such as the FT-CCD.
Therefore, unless the input of the optical signal is blocked by closing the shutter before starting the signal reading, the optical signal is newly mixed in the signal being transferred, and the signal purity is improved. descend. However, in the case of catching a single-shot phenomenon, it is considered that there is no new light input during the transfer of the signal charge, and therefore a shutter or the like is not necessary.

The signal reading operation will be described with reference to FIG. The signal charges are sent downward row by row by the pulses φ ₁ to φ ₄ given to the clock pulse electrode group 2 for vertical transfer, and transferred to the output terminal through the horizontal read register 6. That is, in the figure, first, the signal charges in the bottom row are simultaneously sent to the horizontal reading register 6, and clocks of high frequency in the horizontal direction φ ₅ , φ
It is transferred at ₆ and read from the output end as a time series signal. The horizontal transfer clocks φ ₅ and φ ₆ are applied from the horizontal transfer clock pulse electrode group 7. At this time, since the next signal charge has already moved one step below the vertical register, it enters the horizontal read register 6 at the next vertical transfer clock pulse and is read out to the output end. In this way, all the signal charges for one screen are stored in the horizontal read register 6
Then, the shutter is opened and a new signal storage operation is started. As described above, since the horizontal read register 6 operates at a higher speed than the vertical register, it enables high-speed transfer as the two-phase clock pulses φ ₅ and φ ₆ .

Here, FIG. 12A shows an example of a read circuit which is on-chip in the CCD, and FIG. 12B shows an example showing the relationship between the applied clock pulse and the output waveform. The reference point of the pulse is 0V and the amplitude is + 12V. Regions 17 and 18 under the electrodes to which the clocks φ ₅ and φ ₆ are applied represent the final part of the horizontal register 6. In addition, the substrate 22 is + 12V _DC , and the output gate (OG) 13 is +
7V _DC , + 12V _{DC for} reset drain (RD) 16
Has been added. The drain 8 of the amplifying MOSFET is 15V _DC , and the source 9 is grounded via a load resistor. Therefore, this MOSFET operates as a source follower circuit. The operation will be described below with reference to FIG.

It is assumed that signal charges are successively transferred to the reading circuit by the horizontal register 6. Now time t
_{At 1} , since the clock pulse φ ₅ is at the high level, a potential well is formed in the region 17 below the electrode 7 to which the clock φ ₅ is applied, and the signal charge is transferred to the region 17. Next, at time t ₂ , the clock φ
_{Since 5} becomes low level and φ ₆ becomes high level, the potential well in the region 17 under the electrode 7 to which the clock φ ₅ is added disappears, and the potential well in the region 18 below the electrode 7 to which the clock φ ₆ is added. It is formed. Therefore, the above-mentioned signal charges are transferred to the region 18. Time t ₃
In this case, since a pulse is applied to the reset gate (RG) 15, the floating diffusion (F
D) 14 potential is reset to 12V which is the potential of RD16. At time t ₄ , the signal charge has not yet been transferred to the FD 14, so the potential maintains the reset value. At time t ₅ , the clock φ ₆ becomes low level, so that the signal charge existing in the final region 18 of the horizontal register 6 overcomes the low potential barrier formed by the low DC bias applied to the OG 13, and the FD 14 And change its potential. As can be seen from the example of the output voltage in the same figure (b), since electrons flow in, the output extends downward when the clock φ ₆ becomes low level. The FD 14 is connected to the gate of the source follower circuit (MOSFET) by wiring, and an output of the same magnitude as that input to the gate can be obtained from the source with low impedance.

As described above, the feature of the full frame transfer system is that it has a large area of the light receiving portion without a storage portion, so that the light utilization rate is high, and therefore it is widely used for weak light applications such as measurement. On the other hand, since incident light is absorbed by the transfer electrode, the sensitivity to blue light having a short wavelength is significantly reduced.
As described above, FIG. 11 shows a typical light receiving portion, but the polysilicon electrode 20 covers the surface without gaps, and due to the separation of the respective electrodes, the PSG having a thickness of several microns can be obtained. Membranes 19 are overlaid. In particular, since polysilicon absorbs light and electrons having a wavelength of 400 nm or less, it cannot contribute to photoelectric conversion.

For such a photodetector, the substrate 22
There is a method in which the thickness is reduced to about 15 μm to 20 μm and light is emitted from the back surface as shown in FIG. The front surface of the substrate 22 is provided so as to sandwich the gate oxide film 21 so that the polysilicon electrode 20 covers without gaps and absorbs short wavelength light, but the back surface of the substrate 22 has a thin oxide film 23.
Besides, there are no obstacles, and high sensitivity to short-wavelength light can be expected. This back-illuminated CCD is sensitive to light with a short wavelength of about 0.1 nm, and is further applied to an electron impact CCD image pickup device. This device can be used as a high-sensitivity imaging device because it can utilize the multiplication effect of signal charges generated by electron impact.

Here, a typical example of the manufacturing process of the backside illuminated CCD will be described. First, a P / P ⁺ type epi wafer is used as a wafer. The resistivity and thickness of this epi layer are
The resistivity and the thickness of the sub are 0.01 Ω-cm and 500 μm, respectively. For this epi wafer, aluminum (A
l) Complete all CCD manufacturing processes including the wiring process. It is naturally conceivable to apply aluminum wiring after thinning the silicon of the light receiving portion in a later step, but it is difficult to use the photo-etching method on the thinned film portion, and during the aluminum wiring process The thinned part may crack. Therefore, it is necessary to finish as many processes as possible before thinning.

Next, the silicon nitride and the oxide film on the back surface of the wafer are removed.

After that, a chrome / gold layer formed by laminating chrome and gold is deposited on the entire back surface. Then, the chrome / gold layer is removed only in the portion corresponding to the light receiving surface, that is, in the area corresponding to the back incident surface.

After dividing the epiwafer into chips, they are attached to a holder with wax. After that, HF: HNO ₃ :
The silicon substrate is etched from the rear surface using an etching solution having a ratio of CH ₃ COOH = 1: 3: 8 while leaving the peripheral portion of the chip thick. Since this etching solution is rich in nitric acid, the etching proceeds at a rate controlled by dissolution by hydrofluoric acid.
Here, the reason why the dissolution-controlled etchant is widely used will be described. If it is rich in hydrofluoric acid, the etching proceeds at a rate controlled by oxidation. Since the wafer used is a P / P ⁺ type, if only the P ⁺ layer is selectively etched, it is possible to manufacture a wafer with excellent absolute film thickness and in-plane uniformity.
It is very easy to control reproducibility and uniformity of short wavelength sensitivity. Since the oxidation rate of the P ⁺ layer is high, it is easy to produce a film having excellent film thickness uniformity and reproducibility by using an etching rate-determining etching solution.

[0017] However, in reality, there are many crystal defects in the P ⁺ layer, the crystal defects still faster oxidation rate than the P ⁺ layer, will be etched is also performed quickly, during the end of etching The existing crystal defects cause the etching surface to have a non-uniform thickness, resulting in clouding of the light receiving surface. Therefore, the oxidation rate-controlling etchant cannot be used, and the dissolution rate-controlling etchant, which is difficult to control the film thickness, must be used. In addition, if an alkaline etchant is used as the etchant, the ease of controlling the film thickness uniformity is excellent.
In S devices, the gate oxide film is contaminated with alkali metal,
If the threshold voltage is different from the designed value, it causes malfunction. Therefore, conventionally, no alkaline etchant was used in the process.

Next, the film thickness is measured. As a result, when the film thickness is insufficient as a desired value, etching is performed again.

Next, the above wafer is subjected to back surface oxidation in steam at 120 ° C. for 48 hours. Since Al wiring has already been completed, it is impossible to oxidize by applying high temperature. Therefore, oxidation is performed for a long time at a low temperature of 120 ° C.

Next, the back surface oxide film is irradiated with negative ions,
The so-called backside accumulation is performed. As described above, in the backside illumination CCD, the backside of the CCD serves as the light incident surface. The thickness of the silicon wafer that forms the CCD is typically several hundred microns. Also, from 200 nm to 300 n
The light of m has a very large absorption coefficient, and most of it is absorbed at a slight distance from the surface. Therefore, even if a CCD having a thickness of several hundreds of microns is used as it is as a backside illumination type, photoelectrons generated on the backside cannot diffuse into the potential well of the CCD on the frontside, and most of them recombine. Will be lost. Also, even if some of them can reach the potential well, the signals mix with each other as they spread over a long way, significantly reducing the so-called resolution. Therefore, in the back-illuminated CCD, the back surface, which is the light receiving surface, must be thinned by etching and polishing so that the generated electrons can reach the potential well on the front surface in the shortest distance.

The thickness of a typical detection element made of silicon as shown in FIG. 13 is 10 to 15 μm. Here, the oxide film 23 has a thickness of several tens angstroms to several hundreds angstroms.

FIG. 14 shows the potential profile of the cross section from the light receiving surface to the CCD on the surface of the thin silicon detection element shown in FIG. The left side of the drawing represents the back surface and the right side represents the front surface. The substrate 22 is P-type. An oxide film 23, which is a protective film, is grown on the back surface of the substrate 22.

However, oxide film charges and interface states are always present in the oxide film 23, and these all work to deplete the surface of the P-type silicon substrate 22. That is, as seen from the potential profile, as shown by the solid line in FIG. 14, the potential for electrons decreases as it approaches the oxide film 23 on the back surface, that is, photoelectrons generated at a shallow depth from the back surface go to the potential well of the CCD. However, it is destined to be pushed to the interface between the back surface oxide film 23 and silicon and to be recombined. Therefore, the surface of the P-type silicon 22 close to the back surface oxide film 23 is made into an accumulation state by irradiating with negatively charged ions after thinning the light receiving portion and oxidizing the back surface, as shown by the dotted line in FIG. A different potential profile. As a result, photoelectrons generated in a shallow area on the back surface can also efficiently reach the potential well of the CCD on the front surface side.

Generally, when performing accumulation, boron may be ion-implanted into the P-type silicon substrate, but the ion-implanted layer becomes amorphous, and recrystallization and ion implantation are performed by subsequent heat treatment. We have to activate the boron atom. Usually, this heat treatment (annealing) needs to be a so-called two-step annealing in which heat treatments at around 600 ° C. and around 1000 ° C. are continuously performed. If the annealing is insufficient, it becomes a source of leak current, which is not preferable. However, since the Al wiring is already applied, such high temperature annealing cannot be performed. Therefore, the backside silicon cannot be accumulated by ion implantation, and in reality, only passive accumulation such as irradiation with negative ions is adopted.

Finally, the wafer that has undergone the above operations is mounted in a package. Cooling the CCD to reduce leakage current and rms noise is an important technique for measuring weak light. Therefore, in this step, the surface of the thinned silicon substrate, that is, the surface on which the CCD is formed, is bonded to the package through a non-conductive resin having a small thermal resistance.

[0026]

However, the above-mentioned accumulation has a problem in the sustainability of the effect, and in spite of such work for improving the sensitivity of short-wavelength light, on the contrary, the accumulation is short. Irradiation with wavelength light facilitates removal and neutralization of negative ions attached to the back oxide film. That is, the state that had been accumulated becomes depleted again,
There is a problem that the sensitivity to short wavelength light is lost.

In addition, there are some problems in the process of manufacturing the above-mentioned detector. For example, since a dissolution rate-determining etchant is used for etching the substrate, the film thickness becomes extremely non-uniform unless the etchant is sufficiently stirred and a new etchant is not constantly supplied to the etching surface. However, no matter how much stirring is performed, a step is generated at the boundary between the etched portion and the non-etched portion due to the wrapping of the etchant, and the film thickness is likely to be uneven. Furthermore, when measuring the film thickness, the CCD must be removed from the holder once. But already CC
Since the film thickness of the portion corresponding to the light receiving portion of D is considerably thin, there is a possibility that the thin film portion may be damaged while being taken or stuck from the substrate.

In the back surface oxidation step, since the oxidation is performed at a low temperature, the properties of the oxide film are not so good, and there are many traps, which may serve as a source of leak current.

In the mounting process, the reduced thickness 10
When a resin is applied to silicon of 15 μm to 15 μm later and cured, compressive stress is generated when the resin is cured, and the force concentrates on the thin film portion, causing a wavy state, which may lead to damage such as cracks. is there.

As described above, the conventional backside illuminated CC
D has problems including the process of obtaining the configuration. That is, when aluminum wiring is performed after thinning the substrate, the degree of freedom of accumulation on the back surface is increased, and ion implantation and two-step annealing can be performed. However, it is difficult to use a photo-etching method for aluminum wiring, and the thin film portion may be damaged when the die bond resin is cured. That is, this method provides good characteristics, but the yield is considerably low.

On the other hand, when thinning is performed after aluminum wiring, the probability of damage to the thin film portion is small because only assembling is performed after thinning. However, back-side accumulation is difficult, and even if it is possible, there is a problem that the leak current is large and the change in sensitivity with time is large. Further, the thin film portion may be damaged when the die bond resin is cured. That is, this method is not bad in terms of yield, but has a very problematic characteristic.

In both cases, an alkaline etchant excellent in film thickness uniformity and controllability cannot be used because the CCD part is not protected.

As shown above, the conventional backside illuminated CC
D has many problems including processes, and it is very difficult to commercialize it.

Therefore, an object of the present invention is to provide a semiconductor energy detector which solves the above problems.

[0035]

The present invention provides a semiconductor energy detector in which a charge reading portion is formed on the front surface of a P-type semiconductor thin plate, and an energy ray is incident from the back surface of the P-type semiconductor thin plate. On the back side of the semiconductor thin plate of
It is characterized in that a high-concentration layer formed by doping ⁺ type impurities is formed.

The charge reading section described above may be one in which a plurality of charge transfer elements are arranged. Furthermore, the energy beam may be an electron beam.

[0037]

According to the present invention, the high-concentration layer doped with P ⁺ -type impurities is provided on the back surface of the P-type semiconductor thin plate. Therefore, unlike the case of the accumulation in which negative ions are irradiated, negative ions attached to the back surface oxide film are not removed and neutralized by irradiation with energy rays such as short-wavelength light, so that a depletion state does not occur. Therefore, it is possible to obtain the semiconductor energy detector in which the accumulation effect is maintained, the impurities are activated and the crystals are made defect-free, and the sensitivity to energy rays is improved.

[0038]

Embodiments of the semiconductor energy detector according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a sectional structure of a first embodiment of the present invention. As shown in FIG.
On the silicon wafer 35 fixed to the bottom of the inside, the CCD 3 is provided on the surface facing the silicon wafer 35.
P-type epi layer 24 as a P-type silicon thin plate having 1
Are installed via the metal bumps 32. The P type epi layer 24 is provided with a P ⁺ layer 27 on the surface not facing the silicon wafer 35. The P-type epi layer 24 is
A silicon wafer 29 is further provided on the upper side of the P ⁺ layer 27 and the oxide film 26 on the surface. The silicon wafer 29 has a structure in which the oxide film 26 is exposed by forming an opening by removing only the region of the package 38 that receives the short wavelength light incident from the window member 40 by etching.

In the back-illuminated semiconductor energy detector described above, the P ⁺ layer 27 is provided on the light-receiving surface of the epi layer 24, whereby the accumulation state is maintained.
Therefore, the detector has uniform and stable sensitivity to short-wavelength light in the same chip.

Next, a method of manufacturing the semiconductor energy detector according to the first embodiment described above will be described with reference to the drawings.

FIG. 2A shows a P-type silicon substrate 25 on which P-type silicon is epitaxially grown. The epi layer 24 has, for example, a specific resistance of 10 Ω-cm,
The thickness is 15 μm, and the silicon substrate 25 has, for example, a specific resistance of 10 Ω-cm and a thickness of 500 μm. The thickness of the epi layer 24 is required to be the same as the thickness of the light receiving portion after being thinned in a later step, or to be slightly thicker from 15 μm to 20 μm.

Next, the P ⁺ layer is formed. The same figure (b)
Shows a P ⁺ region 27 formed on the surface of the epi layer 24 of FIG. 9A by diffusion or ion implantation. The P ⁺ layer 27 is used to put the back side light receiving surface into an accumulation state after thinning is performed later. Therefore, it is desired that the high-concentration P ⁺ layer 27 be formed in a relatively shallow region. The thickness of the oxide film 26 on both sides is about 1000 angstroms.

FIG. 7C shows a separately prepared specific resistance 10
P-type bulk wafer or specific resistance of about 0.
A P ⁺ type bulk wafer of about 01 Ω-cm is shown. In a later step, when using an alkali-based etchant, P-type bulk wafer, and when using a hydrofluoric acid-based acid etchant, P
^The use of the ⁺ type bulk wafer is convenient because the selection ratio between the oxide film 28 and the silicon wafer 29 is large. Here, the thickness of the oxide film 28 on both surfaces is about 1000 angstroms.

Next, bonding is performed. Figure 2 (d) shows
It is a figure which shows the state which turned upside down what was shown in the same figure (b), and stuck the epi surface side and the bulk wafer 29 shown in the same figure (c). The interface between the oxide films 26 and 28 is the bonding surface. Here, the oxide films 26 and 28 are provided on both of the bonding surfaces, but either one may be used. Further, the thickness of the oxide films 26 and 28 is not limited to 1000 Å. The direct bonding technique of a silicon wafer uses a technique of integrating two wafers without using an adhesive. It sticks very firmly just by making it water-immersive or heat-treating it while applying voltage. This technique is described in detail in "Applied Physics Vol. 60, No. 8 (1991) Si wafer direct bonding technique".

Next, etching is performed. The figure (e) is
The silicon substrate 25 has just been removed by polishing or etching. Further, the epi layer 24 may be slightly removed. However, it should be noted here that the thickness from the surface left unetched to the oxide film on the bonding surface finally becomes the thickness of the light receiving surface. Therefore, this thickness must be accurately controlled to 10 microns or 15 microns.

Here, an example in which the CCD is formed in the epitaxial growth layer has been described. The features of the epitaxially grown layer are that it does not have the swirl seen in a bulk wafer, and that it has a low oxygen concentration and is therefore excellent in crystallinity. Therefore, of course, a bulk wafer can be applied, but a higher yield can be expected by using an epitaxial growth wafer. At this stage, the surface damage layer generated during polishing or etching must be completely removed.

Next, the surface side of the epi layer 24 shown in FIG. FIG. 3A shows a state in which the CCD 31 is formed on the epi layer 24 of the bonded wafer, and the metal wiring 30 is further provided.

Next, as shown in FIG. 9B, a silicon nitride film 33 is deposited on the entire upper and lower surfaces of the wafer after the steps up to FIG. Then, the silicon nitride film 33 on the portion where the metal bump is to be grown on the surface on which the CCD 31 is formed is removed. On the surface opposite to the surface on which the CCD 31 is formed, the portion of the silicon nitride film 33 to be thinned is removed.

Here, as a method of forming the bump 32, an example of forming a solder bump by an ultrasonic method will be shown.

FIG. 4 is a schematic view of an ultrasonic soldering device. The solder 43 filling the solder bath 45 is jetted by the stirrer 44 installed inside the solder bath 45. On top of this solder bath 45, the jetted solder 43
CCD wafer 41 is placed vertically inside the solder bath 4
An ultrasonic transducer 42 is placed so as to face the vertical surface of the CCD wafer 41 from the outside of 5. In this device, the CCD wafer 41 facing the ultrasonic transducer 42 is
Fresh solder is always sent to the surface of No. 3, and N ₂ is introduced into the solder bath 45 to prevent oxidation of the solder.

Next, the mechanism of ultrasonic soldering using the above apparatus will be described. First, the solder 43
When a cavity is formed in the cavity and the cavity loses pressure on the surface of the CCD wafer 41, the natural oxide film of the wafer 41 is destroyed. When the natural oxide film is removed, a eutectic reaction occurs with the formed Al electrode, and bumps are formed. Since no eutectic reaction occurs in the non-metal part such as the passivation film, no solder is attached. Therefore, there is no solder growth in the portion where the silicon nitride 33 is formed, and there is no silicon nitride film 33 on the surface opposite to the side where the CCD 31 is formed, but there is a thin natural oxide film there. Since the silicon substrate 29 is present, the solder does not grow.

The solder bumps 32 shown in FIG. 3B are formed by the above method. 10 by ultrasonic method
Bumps having a height of several tens of microns are formed with respect to an aluminum pattern of 0 micron square. The thicker the thickness of the underlying aluminum film is, the higher the height of the formed bumps can be adjusted. . In addition, as a method of forming bumps, there are other methods such as vapor deposition and plating, and the height of the bumps formed can also be changed by this method.

Since the processes up to this point are all performed in the form of a wafer, the total effort is not great. After that, it is divided into individual chips by dicing or the like.

FIG. 3 (c) shows a substrate 35 for supporting a CCD chip, which is preferably a silicon wafer or glass having the same coefficient of thermal expansion as the CCD chip. Here, a silicon wafer is used as the substrate 35. First, the silicon wafer 35 is oxidized to form an oxide film 37 having an appropriate thickness, and wiring 34 of Al or the like is formed. The metal wiring 34 connects the metal bump 32 formed on the CCD chip and the electrode of the package. After that, a silicon nitride film 36 is deposited in order to protect the portion of the silicon that comes into contact with the etchant. After that, those shown in FIGS. 2B and 2C are integrated.

FIG. 6D shows a bump bonding of the CCD chip on which the metal bump 32 is formed and the substrate 35 on which the metal wiring 34 is formed.
The side where the CCD 31 is formed is the abutting surface.

Next, the resin 50 is filled. Figure 5 (a)
Shows a state in which the resin 50 is filled so that the surface of the CCD chip and the substrate 35 butted against each other does not enter an etchant of silicon to be used later. This resin 50 is, for example, an epoxy resin manufactured by Nippon Kayaku Co., Ltd.
It is Kayatron ML-230P. The characteristics required for the resin 50 are non-conductivity, resistance to the etchant used in the subsequent process, no alkali metal, etc., and an appropriate shrinkage stress at the time of curing to ensure good contact at the bump bonding portion. To keep it, to withstand heat of about 150 ° C. during die bonding and wire bonding.

Next, the bulk wafer 29 is etched. FIG. 2B shows a state in which the product formed in FIG. 1A is immersed in an etchant and etched. The composition of the etchant is, for example, HF: HNO ₃ : CH ₃ C
Acid-based etchant with a ratio of OOH = 1: 3: 8 or KOH: H ₂ O: isopropyl alcohol = 950 m
1: 1150 ml: 700 ml alkaline etchant and the like. Here, the case where an alkaline etchant is used will be described. 78 etchants
The CCD 31 which is heated to 0 ° C. and bump-bonded to the substrate 24 has to remove bubbles generated on the etching surface which is rotated so as to revolve. If the bubbles are not sufficiently removed, the etched surface becomes rough and the film thickness becomes uneven. The etch rate is approximately 0.6 μm / min. With an alkaline etchant, the film thickness is relatively uniform due to anisotropic etching. However, in the case of the backside illuminated CCD, there is a possibility that a slight reproducibility of the film thickness between the chips and a variation within the chip may result. Here is a solution to this problem.

The selection ratio of the silicon oxide film to silicon with respect to the alkaline etchant is about 1/200. As described above, the bonding surface of the bonding wafer has an oxide film of 1000 angstrom on one side and 2000 angstrom in total. Oxide film 2
6 and 28 correspond to the bonding surface. Therefore, even if the etching progresses with an alkaline etchant and the film thickness becomes somewhat non-uniform during the etching, the etching is performed on the oxide film 28.
2E, the film thickness of the light-receiving surface after etching becomes very uniform between the chips and within the chip if the film thickness of the epitaxial layer 24 is firmly controlled in FIG. 2 (e). . That is, the use of the oxide films 26 and 28 on the bonding surface as an etching stopper is an important point of this technique. Also in the acid-based etchant described above, the oxide film on the bonding surface can be used as a stopper for etching.

FIG. 5B shows a state after the etching of the silicon wafer 29 is completed and the oxide film 28 on the light receiving surface is slightly etched with hydrofluoric acid to adjust the value to have a small reflection. It is not recommended to completely remove the oxide film 26 except for special applications. After the etching is completed, the silicon nitride film 36 deposited on the surface of the silicon wafer 35 is removed, and the metal wiring 34 is exposed on the surface.

Although the importance of the accumulation of the light-receiving surface on the back surface has been described above, the surface of the light-receiving surface is made P ⁺ -type in FIG. 2B. It helps to

In other words, this structure does not require a process for creating a new accumulation state. Since the potential profile for photoelectrons is formed so as to gradually decrease from the light receiving surface on the back surface toward the CCD on the front surface, the photoelectrons generated in the vicinity of the light receiving surface can be efficiently converted to C on the opposite surface.
The potential well of the CD can be reached. That is, the sensitivity to short wavelength light can be made high and stable. Further, as shown in FIG. 2A, since the light receiving surface side is of P ⁺ type at the very early stage of the process, the degree of freedom of heat treatment is large regardless of whether diffusion or ion implantation is used.
It is possible to obtain an accumulation state in which there are few crystal defects so that activation is sufficient and a leak current is not generated.

FIG. 5C shows a state where the backside illuminated CCD is incorporated in a package 38 made of ceramic or the like, and the silicon wafer 35 and the package 38 are connected by a bonding 39.

An example in which an etchant containing an alkali metal such as KOH is used to etch the silicon on the back surface of the CCD chip has been shown above. MOS-type devices such as CCDs usually require extremely high oxide film cleanliness, and therefore extremely dislike alkaline ions such as Na ⁺ and K ⁺ .
However, in the example shown here, when etching is started, the CCD chip is already protected by the resin 50 and does not touch the etchant. Further, after that, the resin 50 and the silicon wafer 35 are not separated from the CCD chip, and the surface on which the CCD chip is formed never touches the outside again. In this process, even if the alkaline etchant is used, the CCD is not used. The parts are kept clean, ensuring reliable operation.

Next, a second embodiment of the present invention will be described.

FIG. 6 shows a sectional structure of the second embodiment of the present invention. As shown in FIG.
On the silicon wafer 35 fixed to the bottom of the inside, the CCD 3 is provided on the surface facing the silicon wafer 35.
P-type epi layer 24 as a P-type silicon thin plate having 1
Are installed via the metal bumps 32. The P type epi layer 24 is provided with a P ⁺ layer 27 on the surface not facing the silicon wafer 35. The P-type epi layer 24 is
Further, a silicon wafer 29 as a sub-wafer is provided on the upper side thereof. The silicon wafer 29 has a structure in which an opening is formed by etching only a region for receiving short-wavelength light incident from the window member 40 provided on the package 38. The side where short-wavelength light enters, that is, the CCD 31 is formed and the epi layer 24 is formed.
An oxide film 47 is formed on the entire back surface of the.

In the back-illuminated semiconductor energy detector described above, the P ⁺ layer 27 is provided on the light-receiving surface of the epi layer 24, whereby the accumulation state is maintained.
Therefore, similarly to the first embodiment, the detector has a uniform and stable sensitivity to short wavelength light in the same chip.

Next, a method of manufacturing the above semiconductor energy detector will be described.

In FIG. 7A, the same P as the bulk portion of the silicon wafer 29 is formed on the first surface of the silicon wafer 29 which becomes the substrate of the P type epitaxial layer.
^{The state where the +} type high concentration impurity layer 27 is formed is shown. P ⁺
The impurity concentration of the type impurity layer 27 needs to be set so that the etching rate becomes slower than that of the alkaline etchant described later when the process up to immediately before the etching of the light receiving surface is completed. × 10 ¹⁸ c
m ⁻³ or more, ideally 1 × 10 ¹⁹ cm ⁻³ or more is required. The silicon wafer 29, which is a bulk portion, has a specific resistance of, for example, 10 Ω-cm and a thickness of 500 μm. Further, the impurity concentration must be 10 ¹⁷ cm ⁻³ or less, which does not slow down the etching rate with respect to the alkaline etchant. The above-mentioned conditions need to be changed slightly depending on the composition and temperature of the alkaline etchant.

Next, epitaxial growth is performed. FIG. 2B shows an epitaxial growth layer (hereinafter referred to as an epi layer) 24 on the first surface of the silicon wafer 29 shown in FIG.
Has just been formed. The specific resistance of the epi layer 24 is, for example, 10 Ω-cm and the thickness is 10 μm. The resistivity of the epi layer 24 may be determined only by considering the performance of the CCD. Since the sum of the thickness of the epi layer 24 and the thickness of the P ⁺ -type impurity layer 27 formed previously becomes the final thickness of the light receiving surface, the epi layer 24
The appropriate thickness is about 10 μm.

Next, the surface side of the epi layer 24 of FIG. 7B is processed. FIG. 3C shows the CCD 3 on the upper surface of the epi layer 24.
1 is formed, and the metal wiring 30 is further provided by Al.

Next, a silicon nitride film 33 is deposited on the entire front and back surfaces of the silicon wafer 29 which has undergone the steps up to FIG. After that, the silicon nitride film 33 in the region where the metal bump 32 is to be grown on the surface where the CCD 31 is formed is removed. On the surface opposite to the surface on which the CCD 31 is formed, the portion of the silicon nitride film 33 to be thinned is removed. Here, the bump 32 is formed according to the same procedure as in the case of the first embodiment described above. As a result, the state shown in FIG.

Separately from the above procedure, a substrate is prepared. FIG. 8A shows a substrate for supporting a CCD chip, and a silicon wafer or glass having a thermal expansion coefficient equal to that of the CCD chip is preferable. Here, the case where the silicon wafer 35 is used as the substrate will be described. First,
Oxide film 3 of appropriate thickness by oxidizing silicon wafer 35
7 is formed, and metal wiring 34 such as Al is formed. The metal wiring 34 connects the metal bump 32 formed on the CCD chip and the electrode of the package. After that, a silicon nitride film 36 is deposited on both surfaces to protect a portion of the silicon that comes into contact with the etchant, and a region where the CCD chip is abutted against the silicon wafer 35 in a later step is removed by etching. Then, FIG. 7 (d) and FIG.
(A) is integrated.

FIG. 8B shows a state in which the CCD chip on which the metal bumps 32 are formed and the silicon wafer 35 on which the metal wiring 34 is formed are bump-bonded. The side where the CCD 31 is formed is the abutting surface. Also, in the same figure, on the butted surface,
The resin 50 is filled so that a silicon etchant used later does not enter. The resin 50 is, for example, Kayatron ML-230P manufactured by Nippon Kayaku Co., Ltd. Then, heat treatment for curing the resin 50 is performed. As described above, most resins generate compressive stress during curing, but since the CCD light receiving portion is not yet thinned, the compressive stress is dispersed throughout the CCD chip and is not cracked or cracked. The characteristics required for the resin 50 are that they are non-conductive, that they withstand the etchant used in the subsequent process, that they do not contain alkali metals, etc. To maintain good contact and to withstand heat of about 150 ° C during die bonding and wire bonding.

Next, the silicon wafer 29 is etched. FIG. 8C shows a thinned state by immersing the one formed in FIG. 8B in an etchant and etching the silicon wafer 29 in the portion corresponding to the light receiving surface. The composition of the etchant is, for example, 8N KOH: H.
₂ O: isopropyl alcohol = 950 ml: 1150
ml: 700 ml of alkaline etchant. The etchant must be heated to 78 ° C., and the CCD chip bump-bonded to the silicon wafer 35 must be rotated so as to revolve around itself to remove bubbles generated on the etching surface. If the bubbles are not sufficiently removed, the etched surface becomes rough and the film thickness becomes uneven. The etch rate is approximately 0.6 μm / min. With an alkaline etchant, the film thickness is relatively uniform due to anisotropic etching.
However, in the case of a backside illuminated CCD, a slight variation in film thickness between chips and poor uniformity within a chip may lead to non-uniform short wavelength sensitivity between chips and within a chip. Here is a solution to this problem.

10 for this alkaline etchant
P-type silicon layer with an impurity concentration of ¹⁷ cm ⁻³ or less and 1 × 1
The selection ratio of the P ⁺ type silicon layer having an impurity concentration of 0 ¹⁹ cm ⁻³ or more is about 1/10. As described above, the epitaxially grown wafer on which the CCD is formed has the P ⁺ type silicon layer as a buried layer.

Therefore, even if the etching is advanced from the back surface P-type silicon layer 29 with an alkaline etchant and the film thickness becomes somewhat non-uniform during the etching, the etching rate is automatically adjusted when the etching reaches the P ⁺ layer 27. Since it becomes slower, the epitaxial layer 24 in FIG.
If the film thickness is controlled well, the film thickness of the light-receiving surface after etching becomes very uniform between chips. That is, P formed in the epitaxial growth layer 24
It is an important part of this technique that the etching can be terminated semi-automatically by the ⁺ layer 27.

After the silicon etching is completed, the silicon nitride film 33 on the surface is removed. Thereafter, as shown in FIG. 3D, the silicon oxide film 47 is grown on the light receiving surface in a wet atmosphere at 120 ° C. for about 48 hours. No silicon oxide film is not recommended except for special applications. After the growth of the silicon oxide film 47, the silicon nitride film 36 deposited on the electrode 34 of the silicon wafer 35 is removed, and the metal wiring 34 is exposed on the surface. The reason why the silicon nitride film 36 is removed after the growth of the silicon oxide film is to prevent the metal forming the electrode 34 from being oxidized.

The importance of the accumulation of the light receiving surface on the back surface has been described above. In FIG.
^{The +} type is useful for putting the light receiving surface into the accumulation state in FIG. 8 (d). That is, this structure does not require a process for creating a new accumulation state. Since the potential profile for photoelectrons is formed so as to decrease from the light receiving surface on the back surface toward the CCD on the front surface, photoelectrons generated near the light receiving surface can also efficiently reach the potential well of the CCD on the opposite surface. . That is, the sensitivity to short wavelength light can be made high and stable. Further, as shown in FIG. 7A, since the light-receiving surface side is of P ⁺ type at the very early stage of the process, the degree of freedom of heat treatment is large and activation is high regardless of whether diffusion or ion implantation is used. The accumulation state is sufficient and has few crystal defects so as not to be a generation source of leakage current.

FIG. 9 shows a state in which the backside illuminated CCD is incorporated in a package 38 made of ceramic or the like, and the silicon wafer 35 and the package 38 are connected by a bonding 39.

In the above embodiment, an example is shown in which an etchant containing an alkali metal such as KOH is used to etch the silicon on the back surface of the CCD chip. MOS-type devices such as CCDs usually require extremely high oxide film cleanliness, and therefore extremely dislike alkaline ions such as Na ⁺ and K ⁺ . However, in the example shown here, like the first embodiment, the CCD chip is already protected by the resin 50 and does not come into contact with the etchant when etching is started. Also, after that, the resin 50 and the silicon wafer 35
Is never separated from the CCD chip, and the surface on which the CCD chip is formed never touches the outside again.
In this process, even if an alkaline etchant is used, the CCD portion is kept clean and the operation is ensured.

[0082]

As described above, according to the semiconductor energy detector of the present invention, the high-concentration layer in which the P ⁺ -type impurity is implanted is provided on the back surface of the P-type semiconductor thin plate. Therefore, this high-concentration layer not only plays a role of an etching stopper, but also negative ions attached to the back surface oxide film are removed and neutralized by irradiation with energy rays such as short-wavelength light, resulting in a depletion state. Absent. Therefore, it is possible to obtain the semiconductor energy detector in which the accumulation effect is maintained, the impurities are activated and the crystals are made defect-free, and the sensitivity to energy rays is improved.

[Brief description of drawings]

FIG. 1 is a schematic view showing a cross-sectional structure of a first embodiment according to the present invention.

FIG. 2 is a manufacturing process diagram of a first embodiment of a semiconductor energy detector according to the present invention.

FIG. 3 is a manufacturing process diagram of a first example of a semiconductor energy detector according to the present invention.

FIG. 4 is a diagram showing an apparatus for forming metal bumps.

FIG. 5 is a manufacturing process drawing of the first embodiment of the semiconductor energy detector according to the present invention.

FIG. 6 is a schematic view showing a sectional structure of a second embodiment according to the present invention.

FIG. 7 is a manufacturing process diagram of a second embodiment of the semiconductor energy detector according to the present invention.

FIG. 8 is a manufacturing process diagram of a second embodiment of the semiconductor energy detector according to the present invention.

FIG. 9 is a manufacturing process diagram of a second embodiment of the semiconductor energy detector according to the present invention.

FIG. 10 is a top view showing a configuration of a full frame transfer system.

FIG. 11 is a sectional view showing a main part of a full frame transfer system.

FIG. 12 is a diagram showing a read circuit diagram and a clock pulse output waveform.

FIG. 13 is a diagram showing a conventional backside illuminated detector.

FIG. 14 is a diagram showing a potential profile of a conventional backside illuminated detector.

[Explanation of symbols]

24 ... Epi layer, 25 ... Substrate, 27 ... P ⁺ layer,
29 and 35 ... Silicon wafer, 30 and 34 ... Metal wiring, 31 ... CCD, 32 ... Metal bump, 33 and 36
... Silicon nitride film, 38 ... Package, 39 ... Bonding, 40 ... Window material, 41 ... CCD wafer, 42 ... Ultrasonic vibrator, 43 ... Solder, 44 ... Stirrer, 45 ... Solder tank,
50 ... Resin.

Claims (3)

[Claims] 1. A semiconductor energy detector in which a charge read-out portion is formed on the surface of a P-type semiconductor thin plate, and energy rays are incident from the back surface of the P-type semiconductor thin plate, wherein Is a semiconductor energy detector characterized in that a P ⁺ -type high-concentration layer doped with impurities is formed. 2. The semiconductor energy detector according to claim 1, wherein the charge reading section is formed by arranging a plurality of charge transfer elements. 3. The semiconductor energy detector according to claim 1, wherein the energy beam is an electron beam.