JP3317740B2 - Semiconductor energy ray detector and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back-illuminated charge-transfer type semiconductor energy detector which is effective for irradiating an energy ray having an extremely large absorption coefficient, such as ultraviolet rays, .gamma. Rays, or charged particle rays. It is.

[0002]

2. Description of the Related Art A charge transfer device (CCD) sequentially transmits an analog charge group in one direction at a speed synchronized with a clock pulse from the outside. It is a very clever functional device that can be converted to a series signal. Generally, as a practical CCD image pickup device, there are three typical systems of a frame transfer (FT), a full frame transfer (FFT), and an interline transfer (IT) configuration. A full frame transfer method is used.

FIGS. 4 and 5 show a configuration of a full frame transfer system, FIG. 4 is a top view thereof, and FIG. 5 is a sectional view of a main part thereof. As shown in FIG. 4, in this method, a charge transfer channel is divided in a vertical direction by a channel stop diffusion layer 1 formed on a substrate, and a pixel column corresponding to the number of horizontal pixels is formed. On the other hand, a transfer electrode group 2 is arranged orthogonal to the channel stop diffusion layer 1. There is no storage unit in the full frame transfer type CCD,
During the charge transfer time, that is, during the reading time, the shutter is closed so that light does not enter the CCD. Note that three overflow drains 5 are formed between the four pixel columns in the vertical direction.

As shown in FIG. 5, one pixel is surrounded by a number of electrodes 20 and channel stop diffusion layers 1 corresponding to the number of phases (4) of clock pulses (φ _{1 to} φ ₄ ) constituting one stage of the CCD. Area. The vertical transfer clock pulse electrode group 2 supplies clock pulses φ _{1 to} φ ₄ to the polysilicon electrode 20. An interlayer insulating film 19 made of PSG (phosphorus glass) is deposited on the upper surface of the polysilicon electrode 20, and a gate oxide film 21 is interposed between the electrode 20 and the n-well 22 on the silicon substrate 48.

When light enters the light receiving region, as shown in FIG. 5, the excited signal charge is applied to one transfer electrode (storage electrode), that is, the potential under the polysilicon electrode 20 to which the rising clock pulse φ ₁ is applied. Collected in well 3.

When the charge storage time for converting the optical signal into the signal charge ends, the clock voltages φ _{1 to} φ ₄ applied to the vertical transfer electrode group 2 on the light receiving region sequentially rise, and the reading of the signal charge is started. You. However, in the full frame transfer CCD, there is no so-called storage unit different from the light receiving unit such as the FT-CCD as described above.
Therefore, if the input of the optical signal is not interrupted by closing the shutter or the like before starting the signal reading, the optical signal is newly mixed into the signal being transferred, and the signal purity is reduced. descend. However, in the case of capturing a one-shot phenomenon, it is considered that there is no new light input during the transfer of the signal charge, so that a shutter or the like is not required.

Here, a signal reading operation will be described with reference to FIG. The signal charges are sent downward one row at a time by pulses φ ₁ to φ ₄ applied to the clock pulse electrode group 2 for vertical transfer, and are transferred to the output terminal through the horizontal read register 6. That is, in the figure, first, the signal charges in the bottom row are simultaneously sent to the horizontal read register 6, and the clocks φ ₅ , φ ₆
And read from the output terminal as a time series signal. The horizontal transfer clocks φ ₅ and φ ₆ are applied from the horizontal transfer clock pulse electrode group 7. At this time, since the next signal charge has already moved one step below the vertical register, the signal charge enters the horizontal read register 6 at the next vertical transfer clock pulse and is read to the output terminal. Thus, the signal charges for one screen are all transferred to the horizontal readout register 6.
, The shutter is opened and a new signal accumulation operation is started. As described above, since the horizontal read register 6 operates at a higher speed than the vertical register, high-speed transfer is enabled by using the two-phase clock pulses φ ₅ and φ ₆ .

The feature of the full frame transfer method is that the light receiving section has a large area without a storage section, so that the utilization rate of light is high, and therefore, it is widely used for faint light use such as measurement. On the other hand, since the incident light is absorbed by the transfer electrode, the sensitivity to blue light having a short wavelength is significantly reduced. This is because the polysilicon electrode 20 covers the surface without any gaps, and the PSG reaches a thickness of several microns due to the separation of each electrode.
Since the films 19 are superimposed, light is absorbed by these films. In particular, polysilicon has a 40
It has the property of absorbing light and electrons having a wavelength of 0 nm or less.

For such a photodetector, the substrate 48
Is reduced to about 15 μm to about 20 μm so that light is irradiated from the back surface. The photoelectric conversion portion is provided below the gate oxide film 21 so that the polysilicon electrode 20 covers the gap without any gap and absorbs short-wavelength light. There is nothing, and high sensitivity to short wavelength light can be expected. This back-illuminated CCD has sensitivity to light having a short wavelength of about 0.1 nm, and is further applied to an electron impact CCD imaging device. This device can be used as a high-sensitivity imaging device because it can use the multiplication effect of signal charges generated by electron impact.

This back-illuminated CCD is a new type of C
Although there are few examples because it is a CD, the following are examples of the manufacturing process.

FIG. 6A shows a protection plate (substrate).
120 shows a sectional structure of the protective plate 12.
For the material of No. 0, a sintered ceramic or the like is used. A through hole 27 is provided in a portion of the protection plate where the CCD is formed later on the wafer, and a metal wiring 26 is provided in the ceramic portion 25.

FIG. 6B shows a cross section of the wafer 130 on which the CCD 31 is formed. This wafer 130 is formed by growing a P-type epi layer 29 on a P ⁺ -type wafer 28 and then forming a CCD 31 and a metal wiring (pad) 32 connecting the CCD 31 and an external circuit.

Here, a P / P ⁺ type epi wafer is used as the wafer 130, and the specific resistance and thickness of the epi layer 29 are 30 Ω-cm and 20 μm, respectively. P ⁺
The specific resistance and the thickness of the mold substrate 28 are 0.01 Ω-cm and 500 μm, respectively. CCD is usually P
/ P ⁺ type epitaxial growth wafer is used, but since the FET of the readout circuit with built-in CCD is N-channel, the on-resistance can be made smaller than that of P-channel FET, and the generated thermal noise (Johnson noise) is reduced. It is based on the reason that it can be reduced. further,
If the substrate is of the P / P ⁺ type, the lifetime of minority carriers in the bulk (wafer) is shortened, and the dark current component in the bulk is prevented from flowing into the potential well of the CCD and the dark current is suppressed from increasing. There is an advantage.

Usually, the oxygen concentration is high in the bulk region, and many crystal defects are excited in the bulk by the heat treatment during the process. However, a P ⁺ type region is formed on the wafer. This prevents the high-concentration layer from becoming a sink for defects, and suppresses the occurrence of crystal defects near the surface constituting the CCD.

The protective plate 120 and the wafer 130 are aligned, and the metal wiring 26 and the metal wiring 32 are wire-bonded and connected by a bonding wire 38a (FIG. 6C). Next, the through-hole 27 of the protection plate 120 is filled with a filler 33 such as low-melting glass or epoxy resin (FIG. 6D). The filler 33 is used for bonding the CCD substrate 130 and the protection plate 120, protecting the bonding wires,
Protection of CCD when forming thin film on D substrate 130, CC
It functions as a cooling medium for D cooling.

Then, the rear surface of the CCD substrate 130 is shaved to make it mechanically and chemically thin (FIG. 7 (e)). First,
Mechanical polishing with a grinder (Disco Corporation)
P until the remaining thickness of the CD substrate 130 becomes 30 to 40 μm.
^{The +} -type substrate 28 is shaved and mechanically etched to remove the high concentration defect layer in the bulk. The mechanical etching is performed first for the following reason. Chemical etching is microscopically a repetition of the oxidation-etching process, and the oxidation rate of the defective layer is different from that of pure silicon. If the thickness is reduced only by chemical etching, the surface after the etching will be uneven or cloudy, requiring a certain amount of time and effort. Therefore, good thinning is performed by performing mechanical etching to some extent in advance.

In addition, the reason why chemical etching is performed after mechanical etching is that the surface crushed layer always remains after mechanical etching and that removal is necessary, and the CCD substrate 130 is controlled to a predetermined thickness. This is because it is necessary to perform chemical etching with a hydrofluoric acid-nitric acid-acetic acid-based etchant. For example, HF: HNO ₃ : CH ₃
When an etching solution having a COOH ratio of 1: 3: 8 is used, etching is performed at a rate of several μm / min.
The P layer having a specific resistance of 68 Ω-cm or more is not etched. Therefore, if chemical etching is performed from the P / P ⁺ -type epitaxial wafer while leaving the P ⁺ layer 34 by mechanical etching, the epitaxially grown layer 29 of 20 μm completely remains, and the P ⁺ layer of 10 ¹⁸ cm ^-3 is further removed. Etching is stopped in a state where is left. By this process, 2
The control of the film thickness of 0 μm and the accumulation are performed at the same time, and the P ⁺ layer 34 functions as an accumulation layer (the accumulation will be described later).

When the energy beam is UV light, a Si oxide film 35 is formed as an antireflection film (reference numeral 35 in FIG. 7E). As the condition, oxidation is performed in steam at 120 ° C. for 48 hours.

Next, dicing is performed to divide the chips into individual chips 140 (FIG. 7F, reference numeral 35 denotes a dicing line). The divided individual chips 140 are assembled (FIG. 7F). First, the chip 140 is die-bonded to the ceramic package 37, and the metal wiring 26 of the chip 140 and the terminal 42 of the package 37 are wire-bonded and connected by a bonding wire 38b. Then, the chip 140 is sealed with a cooling block 40 for heat radiation through a filler 39 having a small heat capacity so as to be easily thermally connected to the filler 33 of the low-melting glass of the chip 140. Cooling the CCD to reduce the leak current and rms noise makes it suitable for measuring weak light.

The need for an accumulation layer in a backside illuminated CCD is based on the following reasons.

As described above, the backside illuminated CCD has a C
The back surface of the CD becomes the light incident surface. Usually, the thickness of the silicon wafer forming the CCD is 400 to 600 μm.
In addition, light having a wavelength of 200 nm to 300 nm has a very large absorption coefficient, and most of the light is absorbed at a position slightly entering the surface (specifically, about 0.01 μm). Therefore, even if a CCD having a thickness of several hundred μm is used as it is as a backside illumination type, the photoelectrons generated on the backside cannot diffuse into the potential well of the CCD on the front side, and most of them recombine. Lost. Also, even if some of them can reach the potential well, the signals are mixed while spreading along a long way, so that the so-called resolution is remarkably reduced. Therefore, in a backside illumination type CCD, the backside, which is the light receiving surface, is thinned by etching and polishing so that the generated electrons can reach the potential well on the front surface in the shortest distance.

However, oxide film charges and interface states always exist in the oxide film, and all of them work to deplete the surface of the P-type silicon substrate. Therefore, photoelectrons generated at a position shallow from the back surface cannot reach the potential well of the CCD, and are destined to be pushed to the interface between the back surface oxide film and silicon and wait for recombination. Therefore, by making the light receiving section thin and making the front surface of the P-type silicon into an accumulation state on the rear surface, photoelectrons generated at a shallow rear surface can efficiently reach the potential well of the CCD on the front surface side.

FIG. 8 shows a comparison of the potential profiles. The solid line shows the case without the accumulation layer and the dotted line shows the case with the accumulation layer. The left side shows the back side and the right side shows the front side. On the rear surface of the substrate 48, an oxide film 23 as a protective film is grown. In a typical detector, the silicon on the light receiving surface has a thickness of about 10 to 15 μm, and the oxide film 23 has a thickness of several tens Å to several hundred Å. As shown by the solid line, photoelectrons generated at a position shallow from the back surface are pushed to the interface between the back surface oxide film 23 and silicon and recombine, making it difficult to go to the accumulation potential well formed on the CCD surface. On the other hand, by performing a process for accumulation, as shown by a dotted line, the oxide film 23 on the back surface is formed.
, The potential for electrons increases, and a potential having a slope from the back surface to the electrode side is formed, so that photoelectrons can efficiently reach the front surface side.

In the above-described process, aluminum (A
l) All the CCD manufacturing processes including the wiring process have been completed. Therefore, compared to the case where aluminum wiring is applied after thinning of the light receiving portion silicon in a later step,
It is difficult to use the photolithography method for the thinned film part, and the problem that the thinned part may be broken during the aluminum wiring process is suppressed. Process

[0025]

However, there are the following problems. First, in FIG. 6 (c), it is necessary to position the protection plate 120 and the CCD substrate 130, but this work is very delicate, requires skill, and greatly reduces the work time and cost. It is difficult to reduce.

Second, the protective plate 12 is bonded with a bonding wire.
0 and the CCD substrate 130 are electrically connected, but an extra area is required in the horizontal direction of the drawing because of the wire loop formed by the bonding wires. For example, when wire bonding is performed on both sides of a chip, the chip becomes longer by about 2 mm in total. If one chip becomes larger, the number of chips taken from one wafer decreases, and the chip unit price increases. In addition, the whole device is enlarged by the size of the chip, and the heat capacity is increased accordingly. For this reason, the efficiency at the time of cooling deteriorates, which hinders downsizing and weight reduction of the device.

Third, in FIG. 6D, it is necessary to fill the filler 33, but in order to protect the bonding wire, the filler 33 has a thickness enough to cover the wire loop.
Needs to be satisfied. Therefore, the extra filler 33 is required by that much, and the whole apparatus becomes large by that much, and the heat capacity becomes large accordingly. For this reason, the efficiency at the time of cooling deteriorates, which hinders downsizing and weight reduction of the device.
From the viewpoint of reliability, protection of the bonding wire is indispensable, and the increase in the thickness is about 500 μm, which is about double.

Therefore, an object of the present invention is to provide a semiconductor energy detector which has solved the above-mentioned problems.

[0029]

In order to solve the above-mentioned problems, a semiconductor energy ray detector according to the present invention has a circuit having an imaging function formed on one surface thereof and detects energy rays incident from the other surface. A protection board that includes a board for detection, a package having lead wires for storing the board therein and electrically connecting to the outside, and a protection plate for protecting the board from one side; Is provided with a through hole, through which the circuit on the substrate and the lead wiring are electrically connected, and the circuit on the substrate and the lead wiring are connected by a metal bump and a thermosetting conductive material. It is characterized by being.

Further, in the semiconductor energy ray detector of the present invention, a circuit having an imaging function is formed on one surface of the semiconductor energy ray detector, and a substrate for detecting an energy ray incident from the other surface, and the substrate is placed inside the substrate. A package having lead wiring for storing and making electrical connection to the outside; and a protection plate for protecting the substrate from one side, wherein the protection plate is provided with a through hole. The circuit on the substrate and the lead wiring are electrically connected through the protective plate, the protective plate has an opening at a position corresponding to the circuit on the substrate, and the opening is filled with a cured filler. I do.

In this case, the package dissipates the heat generated on the substrate via the filler or the protection plate,
A heat medium for reducing thermal resistance may be applied between the package and the filler.

[0032]

The method of manufacturing a semiconductor energy ray detector according to the present invention includes a first step of forming a bump on a terminal of a circuit having an imaging function formed on one surface of the substrate; An opening is provided corresponding to the position of the circuit above, and a through hole is provided corresponding to the position of each terminal of the circuit and the lead wiring of the package. A second step of filling the opening with a curable fluid, and a fourth step of mechanically or chemically shaving the surface of the opposite substrate on which the circuit is formed. And, cutting the protection plate and the substrate for each circuit,
A method of manufacturing a semiconductor energy ray detector, comprising: a fifth step of placing the cut protection plate and the substrate in a package, connecting the circuit and the lead wiring via the bump, and sealing.

The fifth step may be characterized in that a thermosetting conductive material is injected into the lead wiring near the connection point with the bump, and then cured and connected.

The fifth step may be characterized in that a heat medium for reducing the thermal resistance is applied between the package and the filling.

[0036]

In the semiconductor energy ray detector according to the present invention, since the substrate is mechanically protected by the protective plate at the time of manufacture and during use, the substrate is thinned and the circuit on the substrate is easily cooled. Therefore, energy rays (for example, ultraviolet rays, soft X-rays, and electron beams) can be detected with higher sensitivity.

Here, the substrate, the protection plate, and the package are superposed and adhered, and the circuit of the substrate and the lead wiring are electrically connected, so that the area and volume of the protection plate, the substrate, and the package can be reduced. . In addition, since the protective plate is provided with the through-hole, the electrical connection and mechanical bonding can be more reliably performed and the size can be reduced accordingly.

Further, by filling the opening with the hardened filler, damage to the circuit on the substrate can be reduced, and cooling can be easily performed. Since the heat medium for lowering the thermal resistance is applied, heat can be more easily radiated. Further, by further providing a conductive material in the through-hole or the through-hole, electrical connection can be further ensured.

In the method for manufacturing a semiconductor energy ray detector according to the present invention, the through hole previously formed in the protection plate is aligned with the bump, so that the positioning of the substrate and the protection plate is simplified. Therefore, electrical connection and adhesion of the substrate, the protection plate, and the package are simplified. Since the protection plate protects the substrate mechanically, the surface of the substrate can be mechanically thinned, and the circuit is protected by the filler filled in the opening, so it can be chemically and precisely cut together You can also. Since the connection and adhesion are performed so that the protection plate and the substrate are overlapped by the bump, the area and volume of the protection plate, the substrate, and the package can be reduced.

[0040]

An embodiment of the present invention will be described with reference to the drawings.
The description of the same or equivalent components as those of the above-described conventional example will be simplified or omitted.

FIG. 1 shows the structure of an embodiment of the semiconductor energy ray detector according to the present invention. This detector includes a CCD substrate 130,
The package 37 has a protection plate 220, and a ceramic package is used as the package 37, so that heat generated in the circuit 31 on the substrate 130 can be radiated and cooled. Further, a through-hole is provided in the protective plate 220, and through this through-hole, CC
The feature is that the electrode 32 of the D substrate 130 and the electrode 42 of the lead wiring of the package 37 are electrically connected by the bump 143 and the cured conductive paste 142. As a result, the circuit on the internal CCD substrate 130 and the pin 5
2 is made.

The CCD substrate 130 is housed inside the package 37 with its bottom surface facing upward in the drawing, and the full-frame transfer type CCD 31 for imaging is formed on the surface. A poly-Si electrode,
PSG, which is an interlayer insulating film, is formed. Here, the surface side absorbs energy rays having a large absorption coefficient (for example, ultraviolet rays, soft X-rays, electron beams, etc.), and thus the front-side illuminated CCD has no sensitivity to such energy rays. Further, if the irradiation is performed forcibly, the gate oxide film forming the CCD suffers so-called irradiation damage, which causes damage such as a decrease in transfer efficiency and an increase in noise. FIG.
In order to make the detector sensitive to energy rays having a large absorption coefficient, the detector has a backside CCD structure.
An incident light hν from above is detected.

The thickness of the substrate for making a normal CCD is 4
On the other hand, in the detector of FIG. 1, the CCD substrate 130 is thinned to about 15 μm, and then the back surface is in an accumulation state by ion implantation or the like. If a normal substrate can be used as it is, the signal charge generated near the rear surface incident surface of the substrate must move by diffusion to the CCD potential well on the surface, and is lost by recombination on the way, or a long distance. While spreading, it spreads laterally, significantly reducing the resolution. However, in the detector shown in FIG.
The structure is such that it flows into the potential well, and the physical distance from the rear surface, which is the incident surface, to the CCD potential well, which is on the front surface, is shortened to suppress the deterioration in resolution. And
At the time of use, the CCD 31 is cooled by cooling the package 37 with a Peltier device or the like.
1 is intended to reduce noise.

The protection plate 220 is a thinned CCD substrate 1
30 protects both during assembly and during use.
A through hole is provided. Electrical connection is made through this through-hole, and the connection is made so as to overlap the CCD substrate 130, so that the entire device can be manufactured small. As a result, good cooling is performed, and the leak current and rms noise are reduced to make the device suitable for measuring weak light. Also, the CCD substrate 130 and the lead wiring 4
2, the number of connection points is small, and the reliability is further improved.

As described above, the detector of FIG. 1 has a structure capable of sufficiently protecting the thinned silicon CCD substrate 130 and sufficiently cooling to reduce dark current. To make a detector with this structure well,
The manufacturing process also requires that it be carefully considered. 2 and 3 show a process of assembling the detector of FIG. 1, and the process is as follows.

FIG. 2A shows a sectional structure of the protection plate 220 used in the detector shown in FIG. Protection plate 2
Reference numeral 20 denotes the CC of the CCD substrate 130 as in the above-described conventional example.
A through hole 127 is provided in a portion where D31 is formed, and a through hole 141d is provided in a portion of the CCD substrate 130 corresponding to the metal wiring (pad) 32. The through hole 141d is formed to have a sufficient size for the bump formed on the wiring 32. The protection plate 12
As the material of No. 0, an abrasive ceramic such as silicon, glass, or aluminum nitride can be used. It is more preferable to use a material having a coefficient of thermal expansion that is good with that of the CCD substrate 130. Is used.

FIG. 2 (b) shows a CCD substrate 130. The CCD substrate 130 has a P-type epitaxial layer 29 on a silicon P ⁺ -type wafer 28 as in the above-described conventional example.
Is formed, a CCD 31 is formed, and a metal wiring (pad) 32 for connecting to an external circuit is provided. Then, the metal bumps 1 are formed on the metal wires 32 of the CCD substrate 130.
43 are formed. The bump 143 has a diameter of 60 μm and a height of 80 μm by using a wire bonder.
μm can be easily formed. By forming bumps in the same place, they are stacked, and the height is doubled if formed twice and tripled if formed three times.

Then, the protection plate 220 (FIG. 2A)
The CCD substrate 130 on which the metal bumps 143 are formed (FIG. 2)
(B)) is superimposed (FIG. 2 (c)). At this time,
Since the through-hole 141d meshes with the bump 143, the alignment between the protection plate 220 and the CCD substrate 130 is easily performed. That is, no special equipment or skill is required. Further, since the bump 143 enters the through hole 141d, the thickness after bonding becomes smaller. Therefore, it can be made smaller.

Next, before curing, a liquid-phase filler 33 such as a low-melting glass, an epoxy resin, or a gel resin is filled with a depression (a hole 127 of the protection plate 220) formed by the protection plate 220 and the CCD substrate 130. ), The filler 33 is cured (FIG. 2D). The filling 33 needs to be electrically insulative, and furthermore, the protection plate 220 and the CC
It is important that the D substrate 130 has a coefficient of thermal expansion and good thermal conductivity, and that it withstands an etchant (acid or alkali) used for etching silicon, and has a temperature of several hundred degrees
It is further desirable to withstand the above high temperatures and to have no outgassing. This is because it can withstand a high temperature of several hundred degrees Celsius or more and is easy to perform heat treatment by accumulation after thinning, and if there is no outgas, it is suitable for sealing in an electron tube for electron bombardment.

Before the next thinning step, the filling 3
Since 3 is cured, even if the volume of the filler 33 is reduced during curing, no irregularities are generated on the CCD substrate, and irregularities are rarely generated on the incident surface after the thinning process. If there is no hole 127 in the protective plate 220, a large number of air layers will be present at the time of filling with the filling material 33. However, since the hole 127 is filled, air with poor heat conduction is formed. Prevents the formation of layers and fills 3
3 functions well as a cooling medium at the time of cooling.

Then, similarly to the above-described conventional example, the back surface of the CCD substrate 130 is shaved to make it mechanically or chemically thin (FIG. 3E). When thinning is performed only by chemical etching, the P ⁺ layer of the substrate has a high concentration defect layer, and the oxidation rate of the defect layer is different from the oxidation rate of pure silicon.
Irregularities and fogging occur on the surface after the etching, and a certain amount of time and effort are required. However, in this manufacturing process, since the filling 33 is filled and the CCD substrate 130 has a reinforced structure as a whole, it is possible to reduce the thickness by mechanical polishing using a grinder (Disco Corporation) or the like. ing. After thinning, accumulation and oxidation of the back surface are performed to form an accumulation layer 34 and an oxide film 36.

Next, dicing is performed to divide the chips into individual chips 140 (FIG. 3F, reference numeral 36 denotes a dicing line). Then, the divided individual chips 14
0 assembly.

FIG. 3 (g) shows the package 37, in which a lead pattern 42 for electrical connection with the pins 52 of the package 37 is formed, and a portion corresponding to the through hole 141d of the protection plate 220. Is provided with a concave portion 53. A thermosetting conductive paste 142 (for example, a conductive and liquid phase material such as silver glass before being cured) is put into the recess (FIG. 3 (h)). After the chip 140 is attached to the package with the back surface facing upward, the conductive paste 142 is thermally cured and filled with a filler 39 (for example, a silicone resin) having an insulating property and a high thermal conductivity (FIG. 3).
(I)) sealing. The connection is made using the conductive paste 142, so that the connection can be easily made without using a bump bonding machine. In addition, cooling is facilitated by the filling material 39.

As described above, in the present manufacturing process, first, since the alignment between the protection plate 220 and the CCD substrate 130 is performed by the through holes 141d and the bumps 143, an expensive and cumbersome flip chip bonder can be used. It can be easily assembled without using. Further, as in the conventional example, the protection plate 22
In the case where the electrical connection between the 0 and the CCD substrate 130 is made by wire bonding, extra space is required in the horizontal direction and the height direction for the wire loop, and the chip itself needs to be arranged at a distance. The number of wafers per sheet is reduced. In addition, the height, width, and height are all large, and it is difficult to reduce the size and weight. In addition, a cooling device (Peltier element) having a large heat capacity and a large power is required. However, in the present invention, the protection plate 2
20 and the CCD substrate 130 are electrically connected to the bumps 143.
Therefore, it can be configured to be thin and small, so that the size and weight can be reduced, the heat capacity is reduced, and the cooling efficiency is improved.
When a Peltier element is used, the power of the Peltier element is small.

Further, since the protection plate 220 and the lead wiring 42 are connected by the bumps 143, a space for a wire loop is not required as compared with the case where wire bonding is performed, so that the size and weight can be further reduced.

Further, in the present manufacturing process, the protective plate 220 and the CCD substrate 130 have a structure in which the filler 33 is filled during thinning. Therefore, the CCD on the CCD substrate 130 has a protected structure, and there is no unevenness on the incident surface after the thickness is reduced. Further, a portion where the CCD is located is provided with a hole in the protection plate 220, and since the protection of the CCD is performed by the filler 33, an air layer having a large thermal resistance enters between the protection plate 220 and the CCD substrate 130. There is almost no possibility. Therefore, the deterioration of dark current uniformity during cooling of the CCD is reduced. In addition, since the entire CCD substrate 130 is thinned, it is possible to perform almost all of the polishing by mechanical polishing and then to perform chemical etching in the final finishing, which may cause non-uniformity of the etching caused by the surrounding of the etching solution. Absent.

Further, since the heat is dissipated by the ceramic package, the number of assembly parts for heat dissipation is reduced, the structure is simplified, and the size and weight can be further reduced.

[0058]

As described above, according to the semiconductor energy ray detector of the present invention, the area and volume of the protective plate, the substrate and the package can be reduced, and the electrical connection is made by adjusting the positions of the through holes of the protective plate. Can be more reliably reduced in size, so that more sensitive energy rays can be detected.

According to the method for manufacturing a semiconductor energy ray detector of the present invention, electrical connection and adhesion between the package and the substrate are simplified, and the substrate is mechanically protected by the protective plate. Can be mechanically thinned so that the semiconductor energy ray detector can be manufactured small.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a semiconductor energy ray detector of the present invention.

FIG. 2 is a manufacturing process diagram of the embodiment.

FIG. 3 is a manufacturing process diagram of the embodiment.

FIG. 4 is a top view showing a configuration of a full frame transfer system.

FIG. 5 is a sectional view showing a main part of a full frame transfer method.

FIG. 6 is a manufacturing process diagram of a conventional example.

FIG. 7 is a manufacturing process diagram of a conventional example.

FIG. 8 is a diagram showing a potential profile of a conventional backside illumination type detector.

[Explanation of symbols]

31 ... CCD, 32 ... Wiring, 37 ... Package, 42 ...
Lead wiring, 126 ... wiring, 130 ... CCD board, 14
1d: through hole, 142: conductive paste, 143, 144
... metal bumps, 220 ... protective plate

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-159760 (JP, A) JP-A-4-10635 (JP, A) JP-A-3-209746 (JP, A) JP-A-2-209 270374 (JP, A) JP-A-2-260658 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/14

Claims (6)

(57) [Claims] A circuit having an imaging function is formed on one surface thereof, and a substrate for detecting energy rays incident from the other surface is stored in the substrate and electrically connected to the outside. And a protective plate for protecting the substrate from the one surface side. The protective plate has a through hole, and a circuit on the substrate is provided through the through hole. And the lead wiring are electrically connected, and the circuit on the substrate and the lead wiring are connected by a metal bump and a thermosetting conductive material. 2. A substrate having an imaging function formed on one surface thereof for detecting an energy ray incident from the other surface, and a substrate stored in the substrate and electrically connected to the outside. And a protective plate for protecting the substrate from the one surface side. The protective plate has a through hole, and a circuit on the substrate is provided through the through hole. And the lead wiring are electrically connected, the protection plate has an opening at a position corresponding to the circuit on the substrate, and the opening is filled with a cured filler. Semiconductor energy ray detector. 3. A heat medium for dissipating heat generated in the substrate via the filling material or the protection plate, and reducing a thermal resistance between the package and the filling material. The semiconductor energy ray detector according to claim 2, wherein is applied. 4. A first step of forming a bump on a terminal of a circuit having an imaging function formed on one surface of a substrate, and an opening corresponding to a position of the circuit on the substrate in a protective plate. And a through hole is provided corresponding to the position of each terminal of the circuit and the lead wiring of the package, and the protection plate and the substrate are overlapped by aligning the position of the through hole and the bump. A third step of filling the opening with a curable fluid, a fourth step of mechanically or chemically shaving the surface of the substrate on the opposite side where the circuit is formed, A fifth step of cutting the protection plate and the substrate for each circuit, placing the cut protection plate and the substrate in a package, connecting the circuit and the lead wiring via the bumps, and sealing; A method for manufacturing a semiconductor energy ray detector comprising: 5. The method according to claim 4, wherein in the fifth step, a thermosetting conductive material is injected into the lead wiring near the connection point with the bump, and then the lead wiring is cured and connected.
A manufacturing method of the semiconductor energy ray detector according to the above. 6. The semiconductor energy ray detector according to claim 4, wherein in the fifth step, a heat medium for reducing thermal resistance is applied between the package and the filling. Manufacturing method.