JPH0629475A - Mos field-effect transistor - Google Patents

Abstract

PURPOSE:To enable independent setting of the potential of a back gate region by forming a semiconductor layer or an insulator layer between a semiconductor substrate and the back gate region. CONSTITUTION:An N<-> type well 3a of P<-> channel MOSFET is isolated from an N<-> type silicon substrate 1a by a P type isolation layer 2b. Therefore the potential of the well 3a can be set independently of the silicon substrate 1a by a back gate terminal B. When a higher potential than the one of a drain terminal D is impressed on the back gate terminal B, a reverse bias in which only a minute current flows through mutual junctions of the well 3a, the isolation layer 2b and the silicon substrate 1a is brought forth and insulation isolation is attained between them. Since a potential difference between a source terminal S and the back gate terminal B can be held unvaried (inclusive of 0V), fluctuation of VT due to a back gate effect can be suppressed. A P<-> type well 3b is isolated in insulation likewise from a P<-> type silicon substrate 1b by an N<-> type isolation layer 2a and the potential can be set independently.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to MOS field effect transistors, and more particularly to CMOS integrated circuits.

[0002]

2. Description of the Related Art A conventional CMOS integrated circuit is shown in FIG.
A description will be given with reference to (a) and (b).

First, FIG. 4A shows the case where an N ⁻ type silicon substrate is used. A P-channel MOSFET is formed on the N ⁻ type silicon substrate 1a. A gate terminal G is formed on the gate electrode 5, and a source terminal S and a drain terminal D are connected to the P ⁺ type diffusion layer 4b. Further, a positive power supply terminal V _DD is connected to the N ⁺ type diffusion layer 4a.

On the other hand, an N channel M is formed in the P ^-- type well 3b.
The OSFET is formed. A source terminal S and a drain terminal D are connected to the N ⁺ type diffusion layer 4a, and a gate terminal G is connected to the gate electrode 5. A back gate terminal B is connected to the P ⁺ type diffusion layer 4b.

The potential of the P ^-- type well 3b, which is the back gate of the P-channel MOSFET, can be set independently of the positive power supply terminal V _DD . However, the potential of the N ⁻ type silicon substrate 1a which is the back gate of the N channel MOSFET is determined by the potential applied to the positive power supply terminal V _DD .

Therefore, the voltage of the source terminal S of the P-channel MOSFET and the voltage of the N ^-- type silicon substrate 1a varies depending on the drain current. The back gate effect also influences the threshold voltage V _T , the input / output dynamic range and the current amplification factor g _m are reduced, and the linearity of the output current with respect to the input voltage is deteriorated.

Next, FIG. 4B shows the case where a P ^-- type silicon substrate is used. The potential of the N ⁻ type well 3a, which is the back gate of the P channel MOSFET, can be set independently of the negative power supply terminal V _SS . However, N-channel MOS
The potential of the P ⁻ type silicon substrate 1b which is the back gate of the FET varies depending on the drain current. The back gate effect also affects the threshold voltage V _T , which reduces the input / output dynamic range and the current amplification factor g _m, and deteriorates the linearity of the output current with respect to the input voltage.

[0008]

In the conventional CMOS integrated circuit, when the conductivity type of the back gate of the P-channel MOSFET and the N-channel MOSFET matches the conductivity type of the semiconductor substrate, the potential of the back gate is the semiconductor substrate. It becomes the potential of.

Therefore, in a circuit configuration in which the potential of the source terminal and the potential of the back gate terminal of the MOSFET are different, | V _T | increases and the current amplification factor g _m decreases due to the back gate effect. Dynamic range is reduced, V
There is a problem that _T changes and the linearity of the input / output characteristics deteriorates.

[0010]

A MOS field effect transistor according to the present invention is formed in a one-conductivity-type semiconductor layer formed on one main surface of a one-conductivity-type semiconductor substrate with an opposite-conductivity-type semiconductor layer or an insulator layer. Therefore, the potential of the one conductivity type semiconductor layer connected to the back gate terminal can be set independently of the potential of the one conductivity type semiconductor substrate.

[0011]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (b) and.

First, FIG. 1A shows a P-channel MOSFET formed on an N ^- type silicon substrate. The N ⁻ type well 3a in which the P channel MOSFET is formed is P ⁻
The N ⁻ type silicon substrate 1a is separated by the type separation layer 2b. Therefore, the potential of the N ⁻ type well 3a can be set independently of the N ⁻ type silicon substrate 1a by the connected back gate terminal B. Then, a potential higher than the potential applied to the drain terminal D is applied to the back gate terminal B. As a result, N ^- -type well 3a, P ^-
The junction between the type separation layer 2b and the N ⁻ type silicon substrate 1a is reversely biased so that only a minute current flows and is insulated and separated.

Since the potential difference between the source terminal S and the back gate terminal B can be kept constant (including 0 V), the fluctuation of V _T due to the back gate effect can be suppressed.

On the other hand, N formed on the P ^-- type silicon substrate
The channel MOSFET is shown in FIG. The P ^- type well 3b in which the N-channel MOSFET is formed is separated from the P ^- type silicon substrate 1b by the N ^- type separation layer 2a. Therefore, the potential of the P ⁻ type well 3b can be set independently of the P ⁻ type silicon substrate 1b by the connected back gate terminal B. Then, a potential lower than the potential applied to the drain terminal D is applied to the back gate terminal B. As a result, the P ⁻ -type well 3b, the N ⁻ -type separation layer 2a, and the P ⁻ -type silicon substrate 1b are reverse-biased so that only a small current flows, and are isolated.

Since the potential difference between the source terminal S and the back gate terminal B can be kept constant (including 0 V), the fluctuation of V _T due to the back gate effect can be suppressed.

By forming a separation layer having the same potential as the source (or drain) and surrounding the back gate region, the back gate region and the semiconductor substrate can be electrically separated. This separation layer can be formed by diffusion such as vapor phase growth, ion implantation, and thermal diffusion. The well as the back gate region can be formed by well-known ion implantation or thermal diffusion.

Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).

First, FIG. 2A shows a P-channel MOSFET formed on an N ^- type silicon substrate. The N ⁻ type well 3a in which the P channel MOSFET is formed is P ⁻
The N ⁻ type silicon substrate 1a is separated by the type separation layer 2b. Therefore, the potential of the N ⁻ type well 3a can be set independently of the N ⁻ type silicon substrate 1a by the connected back gate terminal B. Then, a potential lower than that applied to the back gate terminal B (normally connected to a negative power source) is applied to the separation terminal I. As a result, N
The junction between the ⁻ type well 3a, the P ⁻ type separation layer 2b, and the N ⁻ type silicon substrate 1a becomes a reverse bias and is isolated.

Since the potential difference between the source terminal S and the back gate terminal B can be kept constant (including 0 V), the fluctuation of V _T due to the back gate effect can be suppressed.

On the other hand, N formed on the P ^-- type silicon substrate
The channel MOSFET is shown in FIG. The P ^- type well 3b in which the N-channel MOSFET is formed is separated from the P ^- type silicon substrate 1b by the N ^- type separation layer 2a. Therefore, the potential of the P ⁻ type well 3b can be set independently of the P ⁻ type silicon substrate 1b by the connected back gate terminal B. Then, a potential higher than that applied to the back gate terminal B (normally connected to a positive power supply) is applied to the separation terminal I. As a result, P ^-
The junction between the type well 3b, the N ⁻ type separation layer 2a, and the P ⁻ type silicon substrate 1b becomes a reverse bias and is insulated and separated.

Since the potential difference between the source terminal S and the back gate terminal B can be kept constant (including 0 V), the fluctuation of V _T due to the back gate effect can be suppressed.

Next, a third embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b).

First, a P-channel MOSFET formed on an N ^- type silicon substrate is shown in FIG. The N ⁻ type well 3a in which the P channel MOSFET is formed is separated from the N ⁻ type silicon substrate 1a by the insulator separation layer 2c. Therefore, the potential of the N ⁻ type well 3a can be set independently of the N ⁻ type silicon substrate 1a by the connected back gate terminal B.

The insulator separation layer 2c and the N ^-- type well 3a are
It can be formed by vapor phase growth of an oxide film or selective oxidation and etching. Further, the N ⁻ type well 3a can be formed by vapor phase growth.

On the other hand, N formed on the P ^-- type silicon substrate
The channel MOSFET is shown in FIG. The P ⁻ type well 3b in which the N channel MOSFET is formed is separated from the P ⁻ type silicon substrate 1b by the insulator separation layer 2c. Therefore, the potential of the P ⁻ type well 3b can be set independently of the P ⁻ type silicon substrate 1b by the connected back gate terminal B.

[0026]

EFFECTS OF THE INVENTION A semiconductor layer or an insulator layer having a different conductivity type is formed between a semiconductor substrate and a back gate region (well) for insulation. As a result, CMO
In the S integrated circuit, the potential of the back gate region can be set independently of the potential of the semiconductor substrate.

The back gate effect was eliminated by keeping the potential difference between the back gate terminal and the source (or drain) terminal constant (including 0 V). Threshold voltage ｜
The decrease of g _{m and} the decrease of the dynamic range due to the increase of V _T | are eliminated, and the distortion of the input / output characteristics due to the change of V _T can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 3 is a cross-sectional view showing a third embodiment of the present invention in process order.

FIG. 4 is a sectional view showing a conventional MOS integrated circuit in the order of steps.

[Explanation of symbols]

1a N ^- type silicon substrate 1b P ^- type silicon substrate 2a N ^- type isolation layer 2b P ^- type isolation layer 2c Insulator isolation layer 3a N ^- type well 3b P ^- type well 4a N ⁺ type diffusion layer 4b P ⁺ type diffusion layer Layer 5 Gate electrode V _DD Positive power supply terminal V _SS Negative power supply terminal S Source terminal G Gate terminal D Drain terminal B Back gate terminal I Separation terminal

Claims (1)

[Claims] 1. A MOS field effect transistor formed on a one-conductivity-type semiconductor layer, which is formed on one main surface of a one-conductivity-type semiconductor substrate with an opposite-conductivity-type semiconductor layer or an insulator layer therebetween.