JPH0629313A - Manufacture of locos offset drain - Google Patents
Manufacture of locos offset drainInfo
- Publication number
- JPH0629313A JPH0629313A JP3301764A JP30176491A JPH0629313A JP H0629313 A JPH0629313 A JP H0629313A JP 3301764 A JP3301764 A JP 3301764A JP 30176491 A JP30176491 A JP 30176491A JP H0629313 A JPH0629313 A JP H0629313A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- locos
- region
- offset
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 43
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 52
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 230000005684 electric field Effects 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＯＣＯＳオフセットド
レインの製造方法に係り、特にプロセスバラツキがあっ
ても安定した高耐圧を保証し得るＬＯＣＯＳオフセット
ドレインの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a LOCOS offset drain, and more particularly to a method of manufacturing a LOCOS offset drain capable of guaranteeing a stable high breakdown voltage even if there are process variations.
【０００２】[0002]
【従来の技術】約５０Ｖの電圧に耐える例えば高耐圧Ｍ
ＯＳＦＥＴにおいては、従来プレーナ型ドレイン（例え
ばＰ+領域）の両端部で電界集中を緩和するドレイン型
として図３及び図４でそれぞれ示す、オフセットドレイ
ン及びＬＯＣＯＳオフセットドレインが知られている。
図３に示すプレーナ型のオフセットドレインは、Ｎ型の
シリコン（Ｓｉ）基板１内に形成されたＰ+ドレイン領
域２の両側にＰ-拡散領域３を形成してドレインエッジ
の電界集中を防止するものであるが、Ｐ-の濃度分布や
その領域形成部位のバラツキにより、Ｐ+ドレイン領域
２の下部エッジ２ａを十分にカバーできず安定した電界
集中の防止ができなかった。2. Description of the Related Art For example, a high withstand voltage M that withstands a voltage of about 50V
In the OSFET, an offset drain and a LOCOS offset drain shown in FIGS. 3 and 4 are known as a drain type that alleviates electric field concentration at both ends of a conventional planar drain (for example, P + region).
In the planar type offset drain shown in FIG. 3, P − diffusion regions 3 are formed on both sides of a P + drain region 2 formed in an N type silicon (Si) substrate 1 to prevent electric field concentration at the drain edge. However, the lower edge 2a of the P + drain region 2 cannot be sufficiently covered due to the P − concentration distribution and the variation in the region forming region, and stable electric field concentration cannot be prevented.
【０００３】そこで、図３のオフセットドレイン型の改
良型として図４に示したＬＯＣＯＳオフセットドレイン
が提案された。Therefore, the LOCOS offset drain shown in FIG. 4 has been proposed as a modification of the offset drain type shown in FIG.
【０００４】図４のＬＯＣＯＳオフセットドレインは、
Ｎ型シリコン基板１にＬＯＣＯＳ酸化層５によって挟ま
れてＰ+ドレイン領域２が形成されており、またＰ-拡散
領域３がＬＯＣＯＳ酸化層５の端部直下で、しかもＰ+
ドレイン領域２と接して形成され、Ｐ+ドレイン領域２
の下部エッジ２ａの電界集中部をカバーして耐圧の向上
を図っていた。The LOCOS offset drain of FIG.
A P + drain region 2 is formed by being sandwiched by a LOCOS oxide layer 5 on an N-type silicon substrate 1, and a P − diffusion region 3 is located immediately below an end of the LOCOS oxide layer 5 and is P +.
P + drain region 2 formed in contact with drain region 2
The electric field concentration portion of the lower edge 2a was covered to improve the breakdown voltage.
【０００５】上記図４に示したＬＯＣＯＳオフセットド
レイン（ＬＯＤ）の製造方法を図５に示した工程断面図
を用いて説明する。A method of manufacturing the LOCOS offset drain (LOD) shown in FIG. 4 will be described with reference to process sectional views shown in FIG.
【０００６】まず、図５（ａ）に示すようにＮ型Ｓｉ基
板１上にゲート酸化膜６を形成し、ＣＶＤ（化学気相成
長）法によりシリコン窒化膜（Ｓｉ3Ｎ4）７をパターニ
ング形成し、次に図５（ｂ）に示す様に、所定位置にレ
ジストパターン９を配し、Ｐ型不純物イオン、例えばボ
ロン（Ｂ+）を低濃度にイオン注入しイオン注入領域を
形成し、レジストパターン９を剥離除去した後、所定温
度でアニールして該イオン注入領域を拡散させてオフセ
ット拡散領域としてＰ-拡散領域３を形成する。このア
ニールでＳｉ基板上の露出部のゲート酸化膜６は更に厚
くなりＬＯＣＯＳ酸化層５となる（図５（ｃ））。First, as shown in FIG. 5A, a gate oxide film 6 is formed on an N-type Si substrate 1, and a silicon nitride film (Si 3 N 4 ) 7 is patterned by a CVD (chemical vapor deposition) method. Then, as shown in FIG. 5B, a resist pattern 9 is arranged at a predetermined position, and P-type impurity ions such as boron (B + ) are ion-implanted at a low concentration to form an ion-implanted region, After removing the resist pattern 9 by peeling, the ion implantation region is diffused by annealing at a predetermined temperature to form a P − diffusion region 3 as an offset diffusion region. By this annealing, the gate oxide film 6 on the exposed portion on the Si substrate becomes thicker and becomes the LOCOS oxide layer 5 (FIG. 5C).
【０００７】次にシリコン窒化膜７を除去した後、通常
通りポリシリコン（Ｐｏｌｙ−Ｓｉ）ゲート電極１０を
形成し、薄いゲート酸化膜６を通じて高濃度Ｂ+イオン
を注入してＰ+ドレイン領域２及びＰ+ソース領域２３を
形成する（図５（ｄ））。Next, after removing the silicon nitride film 7, a polysilicon (Poly-Si) gate electrode 10 is formed as usual, and high concentration B + ions are implanted through the thin gate oxide film 6 to form the P + drain region 2. And P + source regions 23 are formed (FIG. 5D).
【０００８】[0008]
【発明が解決しようとする課題】このように図５（ａ）
〜図５（ｄ）に示した工程によって得られた、Ｐ+ドレ
イン領域２とＰ-拡散領域３とからなるＬＯＣＯＳオフ
セットドレインは、Ｐ-拡散領域３の濃度分布のバラツ
キやＬＯＣＯＳ酸化層５の膜厚のバラツキ等のプロセス
バラツキにより、Ｐ+ドレイン領域２の下部エッジ２ａ
（図中のＢ内）をＰ-拡散領域３でカバーできず、耐圧
を保証できない場合が生じる。The problem to be solved by the invention is shown in FIG.
The LOCOS offset drain formed of the P + drain region 2 and the P − diffusion region 3 obtained by the process shown in FIG. 5D has the unevenness in the concentration distribution of the P − diffusion region 3 and the LOCOS oxide layer 5. Due to process variations such as variations in film thickness, the lower edge 2a of the P + drain region 2
In some cases, the P - diffusion region 3 cannot cover (inside B in the figure) and the breakdown voltage cannot be guaranteed.
【０００９】そこで本発明は半導体装置製造プロセスの
バラツキがあっても、耐圧を保証し得るＬＯＣＯＳオフ
セットドレインの製造方法を提供することを目的とす
る。Therefore, an object of the present invention is to provide a method of manufacturing a LOCOS offset drain capable of guaranteeing a breakdown voltage even if there are variations in the semiconductor device manufacturing process.
【００１０】[0010]
【課題を解決するための手段】上記課題は本発明によれ
ば、１導電型のシリコン基板上に酸化膜を形成した後、
該酸化膜上の所定位置に少なくとも２つの窒化膜パター
ンを形成する工程と、前記窒化膜パターンをマスクとし
て前記酸化膜をエッチングし、且つ前記シリコン基板の
（１１１）面に沿うエッチングを含むエッチングを行っ
て前記シリコン基板に凹部を形成する工程と、前記シリ
コン基板の凹部上方から該シリコン基板内へ反対導電型
の不純物を導入し、熱処理することによって該反対導電
型のオフセット拡散領域を形成する工程と、前記窒化膜
を除去した後、前記凹部にＬＯＣＯＳ酸化層を形成する
工程と、前記ＬＯＣＯＳ配化層の一方の側面上を含む位
置にゲート電極を形成する工程、及び前記ゲート電極を
マスクとして、前記酸化膜を通して前記反対導電型の不
純物を導入し、熱処理することによって前記ＬＯＣＯＳ
酸化層の側面側に該反対導電型のドレイン拡散領域を形
成する工程を含むことを特徴とするＬＯＣＯＳオフセッ
トドレインの製造方法によって解決される。According to the present invention, the above-mentioned problem is solved by forming an oxide film on a silicon substrate of one conductivity type,
Forming at least two nitride film patterns at predetermined positions on the oxide film, and etching the oxide film using the nitride film pattern as a mask, and etching including etching along the (111) plane of the silicon substrate. And a step of forming a recess in the silicon substrate, and a step of introducing an impurity of an opposite conductivity type into the silicon substrate from above the recess of the silicon substrate and performing a heat treatment to form an offset diffusion region of the opposite conductivity type. A step of forming a LOCOS oxide layer in the recess after removing the nitride film, a step of forming a gate electrode at a position including one side surface of the LOCOS layer, and using the gate electrode as a mask The LOCOS is formed by introducing impurities of the opposite conductivity type through the oxide film and performing heat treatment.
This is solved by a method of manufacturing a LOCOS offset drain including a step of forming a drain diffusion region of the opposite conductivity type on a side surface side of an oxide layer.
【００１１】[0011]
【作用】本発明によれば、ドレインとゲート電極間のシ
リコン基板１間に（１１１）面に沿う異方性エッチング
を利用するエッチングによって船型の凹部（溝）２０を
作り、その凹部２０にオフセット拡散領域１３を形成
し、その後その凹部をほぼ埋め、且つその底部を下広が
りになるようなＬＯＣＯＳ酸化層１５を形成しているた
め上記のオフセット拡散領域１３がより下方及び横方向
へ拡大する。そのために後に形成するドレイン領域１２
の下部エッジ１２ａをそのオフセット拡散領域１３で覆
うことができる。According to the present invention, a boat-shaped concave portion (groove) 20 is formed between the drain and the gate electrode between the silicon substrate 1 by utilizing anisotropic etching along the (111) plane, and the concave portion 20 is offset. Since the diffusion region 13 is formed, and thereafter the recess is almost filled, and the bottom portion thereof is formed with the LOCOS oxide layer 15 which is spread downward, the offset diffusion region 13 is further expanded downward and laterally. Therefore, the drain region 12 to be formed later is formed.
The lower edge 12a of the can be covered with the offset diffusion region 13.
【００１２】[0012]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は本発明に係るＬＯＣＯＳオフセット
ドレインを製造する方法の一実施例を示す工程断面図で
ある。FIG. 1 is a process sectional view showing an embodiment of a method of manufacturing a LOCOS offset drain according to the present invention.
【００１４】まず、図１（ａ）に示す様に、Ｎ型（１０
０）シリコン（Ｓｉ）基板１１上に熱酸化法により５０
ｎｍの厚さのゲート酸化膜６を形成し、ＣＶＤ法により
厚さ１００ｎｍのシリコン窒化膜（Ｓｉ3Ｎ4）７をパタ
ーニング形成した。窒化膜７間の距離を３μｍとした。First, as shown in FIG. 1A, an N type (10
0) 50 on the silicon (Si) substrate 11 by the thermal oxidation method
A gate oxide film 6 having a thickness of nm is formed, and a silicon nitride film (Si 3 N 4 ) 7 having a thickness of 100 nm is patterned by the CVD method. The distance between the nitride films 7 was 3 μm.
【００１５】次に図１（ｂ）に示す様に、シリコン窒化
膜７をマスクとしてアンモニア等のアルカリ液を用い
て、ゲート酸化膜６及びＮ型（１００）Ｓｉ基板１１を
異方性エッチングし、特にＮ型（１００）Ｓｉ基板１１
の側面に（１１１）面を露出する船型状の凹部（溝深さ
３００ｎｍ）２０を形成する。Next, as shown in FIG. 1B, the gate oxide film 6 and the N-type (100) Si substrate 11 are anisotropically etched using an alkaline solution such as ammonia with the silicon nitride film 7 as a mask. , Especially N-type (100) Si substrate 11
A boat-shaped concave portion (groove depth 300 nm) 20 exposing the (111) plane is formed on the side surface of the.
【００１６】次に図１（ｃ）に示す様に所定位置にレジ
ストパターン１９を配し、ボロン（Ｂ+）を２５ＫｅＶ
で低濃度にイオン注入し、Ｐ-イオン注入領域を形成
し、レジストパターン１９を剥離除去した後、約１００
０℃で熱処理を行い、Ｐ-イオンを拡散して図１（ｄ）
に示す様にＰ-拡散領域１３を形成した。本熱処理では
Ｐ-拡散領域１３上にはゲート酸化膜６と略平坦化され
たＬＯＣＯＳ酸化層１５が船型状溝２０を埋め込み、更
に船底を下広がりに拡大した状態に形成される。このＬ
ＯＣＯＳ酸化層１５の膜厚は約６００ｎｍであり、また
得られたＰ-拡散領域１３の深さは０．２μｍであっ
た。Next, as shown in FIG. 1C, a resist pattern 19 is arranged at a predetermined position, and boron (B + ) is added at 25 KeV.
After ion-implanting at a low concentration with P to form a P − ion-implanted region and peeling and removing the resist pattern 19, about 100
Heat treatment is performed at 0 ° C. to diffuse P − ions, and FIG.
A P - diffusion region 13 was formed as shown in FIG. In this heat treatment, the gate oxide film 6 and the substantially flattened LOCOS oxide layer 15 are formed on the P − diffusion region 13 so as to fill the boat-shaped groove 20 and further expand the bottom of the boat downward. This L
The OCOS oxide layer 15 had a thickness of about 600 nm, and the obtained P − diffusion region 13 had a depth of 0.2 μm.
【００１７】最後に図１（ｅ）に示す様に、シリコン窒
化膜７を除去した後、ＣＶＤ法によりＰｏｌｙ−Ｓｉを
約４００ｎｍの厚さに被着し、パターニングして幅６μ
ｍのＰｏｌｙ−Ｓｉゲート電極２１を形成する。その
後、Ｐｏｌｙ−Ｓｉゲート電極２１をマスクとして上方
から高濃度でＢ+を注入し、拡散してドレイン領域１２
及びＰ+ソース領域２３を形成する。Ｐ+ドレイン領域１
２及びＰ+ソース領域２３の深さは共に約４００ｎｍ幅
は共に約１０μｍであった。このようにして得られたＰ
-拡散領域１３とＰ+ドレイン領域１２のカバー状態を説
明するために図１（ｅ）のＡ部を拡大して図２に示す。Finally, as shown in FIG. 1 (e), after removing the silicon nitride film 7, Poly-Si is deposited to a thickness of about 400 nm by the CVD method and patterned to have a width of 6 μm.
m Poly-Si gate electrode 21 is formed. Then, using the Poly-Si gate electrode 21 as a mask, B + is injected at a high concentration from above and diffused to diffuse the drain region 12
And a P + source region 23 are formed. P + drain region 1
The depths of the 2 and P + source regions 23 were both about 400 nm and the width was about 10 μm. P thus obtained
In order to explain the covering state of the diffusion region 13 and the P + drain region 12, the portion A of FIG. 1 (e) is enlarged and shown in FIG.
【００１８】図２に示す様に、動作時、特に電界集中を
生ずるＰ+ドレイン領域１２の下部エッジ１２ａは本実
施例で形成したＰ-拡散領域１３によってゆとりを持っ
てカバーされている。As shown in FIG. 2, the lower edge 12a of the P + drain region 12 which causes electric field concentration during operation is covered with a space by the P − diffusion region 13 formed in this embodiment.
【００１９】本実施例では（１００）Ｓｉ基板をエッチ
ングして（１１１）面を露出させる船型状の溝（凹部）
を形成する異方性のウェットエッチングエッチャントと
してアンモニアの他にＫＯＨ等のアルカリが用いられ
る。In this embodiment, a (100) Si substrate is etched to form a boat-shaped groove (recess) to expose the (111) surface.
In addition to ammonia, an alkali such as KOH is used as an anisotropic wet etching etchant for forming.
【００２０】[0020]
【発明の効果】以上説明した様に、本発明によればＰ-
拡散領域（オフセット拡散領域）がＰ+ドレイン領域の
下部エッジを十分に覆うことができるために、半導体装
置製造のバラツキ依存性のない安定した耐圧のＬＯＣＯ
Ｓオフセットドレインを得ることができ、本ドレインを
例えば高耐圧ＭＯＳＦＥＴの製造に好適に利用できる。
なお、本発明ではＬＯＣＯＳ酸化膜の平坦化も図られる
利点がある。As has been described above, according to the present invention, P according to the present invention -
Since the diffusion region (offset diffusion region) can sufficiently cover the lower edge of the P + drain region, the LOCO has a stable breakdown voltage that does not depend on variations in semiconductor device manufacturing.
An S offset drain can be obtained, and this drain can be suitably used for manufacturing a high breakdown voltage MOSFET, for example.
The present invention has an advantage that the LOCOS oxide film can be flattened.
【図１】本発明の一実施例（ＬＯＣＯＳオフセットドレ
イン）を示す工程断面図である。FIG. 1 is a process sectional view showing an embodiment (LOCOS offset drain) of the present invention.
【図２】Ｐ-拡散領域（オフセット拡散領域）とＰ+ドレ
イン領域のカバー状態を示す拡大図である。FIG. 2 is an enlarged view showing a cover state of a P − diffusion region (offset diffusion region) and a P + drain region.
【図３】従来技術であるオフセットドレインを示す断面
図である。FIG. 3 is a cross-sectional view showing a conventional offset drain.
【図４】従来技術であるＬＯＣＯＳオフセットドレイン
を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional LOCOS offset drain.
【図５】従来技術を説明するための工程断面図である。FIG. 5 is a process sectional view for explaining a conventional technique.
１ Ｎ型シリコン（Ｓｉ）基板 ２，１２ Ｐ+ドレイン領域 ２ａ，１２ａ Ｐ+ドレイン領域の下部エッジ ３，１３ Ｐ-拡散領域（オフセット拡散領域） ５，１５ ＬＯＣＯＳ酸化層 ６ ゲート酸化膜 ７ シリコン窒化膜（Ｓｉ3Ｎ4） ９，１９ レジストパターン １０，２１ Ｐｏｌｙ−Ｓｉゲート電極 １１ Ｎ型（１００）シリコン（Ｓｉ）基板 ２０ 溝（凹部） ２３ Ｐ+ソース領域1 N-type silicon (Si) substrate 2, 12 P + drain region 2a, 12a P + lower edge of drain region 3, 13 P − diffusion region (offset diffusion region) 5, 15 LOCOS oxide layer 6 gate oxide film 7 silicon nitride Film (Si 3 N 4 ) 9,19 Resist pattern 10,21 Poly-Si gate electrode 11 N-type (100) silicon (Si) substrate 20 Groove (recess) 23 P + source region
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年２月６日[Submission date] February 6, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【特許請求の範囲】[Claims]
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１０】[0010]
【課題を解決するための手段】上記課題は本発明によれ
ば、１導電型のシリコン基板上に酸化膜を形成した後、
該酸化膜上の所定位置に少なくとも２つの窒化膜パター
ンを形成する工程と、前記窒化膜パターンをマスクとし
て前記酸化膜をエッチングし、且つ前記シリコン基板の
（１１１）面に沿うエッチングを含むエッチングを行っ
て前記シリコン基板に凹部を形成する工程と、前記シリ
コン基板の凹部上方から該シリコン基板内へ反対導電型
の不純物を導入し、熱処理することによって該反対導電
型のオフセット拡散領域を形成する工程と、前記窒化膜
をマスクとして、前記凹部にＬＯＣＯＳ酸化層を形成す
る工程と、前記窒化膜を除去した後、前記ＬＯＣＯＳ酸
化層の一方の側面上を含む位置にゲート電極を形成する
工程、及び前記ゲート電極をマスクとして、前記酸化膜
を通して前記反対導電型の不純物を導入し、熱処理する
ことによって前記ＬＯＣＯＳ酸化層の側面側に該反対導
電型のドレイン拡散領域を形成する工程を含むことを特
徴とするＬＯＣＯＳオフセットドレインの製造方法によ
って解決される。 ─────────────────────────────────────────────────────
According to the present invention, the above-mentioned problem is solved by forming an oxide film on a silicon substrate of one conductivity type,
Forming at least two nitride film patterns at predetermined positions on the oxide film, and etching the oxide film using the nitride film pattern as a mask, and etching including etching along the (111) plane of the silicon substrate. And a step of forming a recess in the silicon substrate, and a step of introducing an impurity of the opposite conductivity type into the silicon substrate from above the recess of the silicon substrate and performing a heat treatment to form an offset diffusion region of the opposite conductivity type. A step of forming a LOCOS oxide layer in the recess using the nitride film as a mask; a step of removing the nitride film and then forming a gate electrode at a position including one side surface of the LOCOS oxide layer; By using the gate electrode as a mask and introducing the impurity of the opposite conductivity type through the oxide film, and performing a heat treatment, It is solved by the manufacturing method of the LOCOS offset drain, characterized in that the side surface of the OCOS oxide layer includes a step of forming a drain diffusion region of the reflected Taishirube conductivity type. ─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年６月２日[Submission date] June 2, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００２[Name of item to be corrected] 0002
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００２】[0002]
【従来の技術】約５０Ｖの電圧に耐える例えば高耐圧Ｍ
ＯＳＦＥＴにおいては、従来プレーナ型ドレイン（例え
ばＰ+領域）の両端部で電界集中を緩和するドレイン型
として図４及び図５でそれぞれ示す、オフセットドレイ
ン及びＬＯＣＯＳオフセットドレインが知られている。
図３に示すプレーナ型のオフセットドレインは、Ｎ型の
シリコン（Ｓｉ）基板１内に形成されたＰ+ドレイン領
域２の両側にＰ-拡散領域３を形成してドレインエッジ
の電界集中を防止するものであるが、Ｐ-の濃度分布や
その領域形成部位のバラツキにより、Ｐ+ドレイン領域
２の下部エッジ２ａを十分にカバーできず安定した電界
集中の防止ができなかった。2. Description of the Related Art For example, a high withstand voltage M that withstands a voltage of about 50V
In the OSFET, an offset drain and a LOCOS offset drain shown in FIGS. 4 and 5, respectively, are known as a drain type that alleviates electric field concentration at both ends of a conventional planar drain (for example, P + region).
In the planar type offset drain shown in FIG. 3, P − diffusion regions 3 are formed on both sides of a P + drain region 2 formed in an N type silicon (Si) substrate 1 to prevent electric field concentration at the drain edge. However, the lower edge 2a of the P + drain region 2 cannot be sufficiently covered due to the P − concentration distribution and the variation in the region forming region, and stable electric field concentration cannot be prevented.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００３[Name of item to be corrected] 0003
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００３】そこで、図４のオフセットドレイン型の改
良型として図５に示したＬＯＣＯＳオフセットドレイン
が提案された。Therefore, the LOCOS offset drain shown in FIG. 5 has been proposed as a modification of the offset drain type shown in FIG.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００４[Correction target item name] 0004
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００４】図５のＬＯＣＯＳオフセットドレインは、
Ｎ型シリコン基板１にＬＯＣＯＳ酸化層５によって挟ま
れてＰ+ドレイン領域２が形成されており、またＰ-拡散
領域３がＬＯＣＯＳ酸化層５の端部直下で、しかもＰ+
ドレイン領域２と接して形成され、Ｐ+ドレイン領域２
の下部エッジ２ａの電界集中部をカバーして耐圧の向上
を図っていた。The LOCOS offset drain of FIG.
A P + drain region 2 is formed by being sandwiched by a LOCOS oxide layer 5 on an N-type silicon substrate 1, and a P − diffusion region 3 is located immediately below an end of the LOCOS oxide layer 5 and is P +.
P + drain region 2 formed in contact with drain region 2
The electric field concentration portion of the lower edge 2a was covered to improve the breakdown voltage.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Name of item to be corrected] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００５】上記図５に示したＬＯＣＯＳオフセットド
レイン（ＬＯＤ）の製造方法を図６に示した工程断面図
を用いて説明する。A method of manufacturing the LOCOS offset drain (LOD) shown in FIG. 5 will be described with reference to process sectional views shown in FIG.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００６】まず、図６（ａ）に示すようにＮ型Ｓｉ基
板１上にゲート酸化膜６を形成し、ＣＶＤ（化学気相成
長）法によりシリコン窒化膜（Ｓｉ3Ｎ4）７をパターニ
ング形成し、次に図６（ｂ）に示す様に、所定位置にレ
ジストパターン９を配し、Ｐ型不純物イオン、例えばボ
ロン（Ｂ+）を低濃度にイオン注入しイオン注入領域を
形成し、レジストパターン９を剥離除去した後、所定温
度でアニールして該イオン注入領域を拡散させてオフセ
ット拡散領域としてＰ-拡散領域３を形成する。このア
ニールでＳｉ基板上の露出部のゲート酸化膜６は更に厚
くなりＬＯＣＯＳ酸化層５となる（図６（ｃ））。First, as shown in FIG. 6A, a gate oxide film 6 is formed on an N-type Si substrate 1, and a silicon nitride film (Si 3 N 4 ) 7 is patterned by a CVD (chemical vapor deposition) method. Then, as shown in FIG. 6B, a resist pattern 9 is arranged at a predetermined position, and P-type impurity ions such as boron (B + ) are ion-implanted at a low concentration to form an ion-implanted region, After removing the resist pattern 9 by peeling, the ion implantation region is diffused by annealing at a predetermined temperature to form a P − diffusion region 3 as an offset diffusion region. By this annealing, the gate oxide film 6 on the exposed portion on the Si substrate becomes thicker and becomes the LOCOS oxide layer 5 (FIG. 6C).
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００７】次にシリコン窒化膜７を除去した後、通常
通りポリシリコン（Ｐｏｌｙ−Ｓｉ）ゲート電極１０を
形成し、薄いゲート酸化膜６を通じて高濃度Ｂ+イオン
を注入してＰ+ドレイン領域２及びＰ+ソース領域２３を
形成する（図６（ｄ））。Next, after removing the silicon nitride film 7, a polysilicon (Poly-Si) gate electrode 10 is formed as usual, and high concentration B + ions are implanted through the thin gate oxide film 6 to form the P + drain region 2. And P + source region 23 are formed (FIG. 6D).
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００８[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００８】[0008]
【発明が解決しようとする課題】このように図６（ａ）
〜図６（ｄ）に示した工程によって得られた、Ｐ+ドレ
イン領域２とＰ-拡散領域３とからなるＬＯＣＯＳオフ
セットドレインは、Ｐ-拡散領域３の濃度分布のバラツ
キやＬＯＣＯＳ酸化層５の膜厚のバラツキ等のプロセス
バラツキにより、Ｐ+ドレイン領域２の下部エッジ２ａ
（図中のＢ内）をＰ-拡散領域３でカバーできず、耐圧
を保証できない場合が生じる。As shown in FIG. 6 (a).
The LOCOS offset drain composed of the P + drain region 2 and the P − diffusion region 3 obtained by the process shown in FIG. 6D has a variation in the concentration distribution of the P − diffusion region 3 and the LOCOS oxide layer 5. Due to process variations such as variations in film thickness, the lower edge 2a of the P + drain region 2
In some cases, the P - diffusion region 3 cannot cover (inside B in the figure) and the breakdown voltage cannot be guaranteed.
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１３[Correction target item name] 0013
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１３】図１及び図２は本発明に係るＬＯＣＯＳオ
フセットドレインを製造する方法の一実施例を示す工程
断面図である。FIGS. 1 and 2 are process sectional views showing an embodiment of a method of manufacturing a LOCOS offset drain according to the present invention.
【手続補正９】[Procedure Amendment 9]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】次に図２（ａ）に示す様に所定位置にレジ
ストパターン１９を配し、ボロン（Ｂ+）を２５ＫｅＶ
で低濃度にイオン注入し、Ｐ-イオン注入領域を形成
し、レジストパターン１９を剥離除去した後、約１００
０℃で熱処理を行い、Ｐ-イオンを拡散して図２（ｂ）
に示す様にＰ-拡散領域１３を形成した。本熱処理では
Ｐ-拡散領域１３上にはゲート酸化膜６と略平坦化され
たＬＯＣＯＳ酸化層１５が船型状溝２０を埋め込み、更
に船底を下広がりに拡大した状態に形成される。このＬ
ＯＣＯＳ酸化層１５の膜厚は約６００ｎｍであり、また
得られたＰ-拡散領域１３の深さは０．２μｍであっ
た。Next, as shown in FIG. 2A, a resist pattern 19 is arranged at a predetermined position, and boron (B + ) is added at 25 KeV.
After ion-implanting at a low concentration with P to form a P − ion-implanted region and peeling and removing the resist pattern 19, about 100
Heat treatment is performed at 0 ° C. to diffuse P − ions and then, as shown in FIG.
A P - diffusion region 13 was formed as shown in FIG. In this heat treatment, the gate oxide film 6 and the substantially flattened LOCOS oxide layer 15 are formed on the P − diffusion region 13 so as to fill the boat-shaped groove 20 and further expand the bottom of the boat downward. This L
The OCOS oxide layer 15 had a thickness of about 600 nm, and the obtained P − diffusion region 13 had a depth of 0.2 μm.
【手続補正１０】[Procedure Amendment 10]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１７[Correction target item name] 0017
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１７】最後に図２（ｂ）に示す様に、シリコン窒
化膜７を除去した後、ＣＶＤ法によりＰｏｌｙ−Ｓｉを
約４００ｎｍの厚さに被着し、パターニングして幅６μ
ｍのＰｏｌｙ−Ｓｉゲート電極２１を形成する。その
後、Ｐｏｌｙ−Ｓｉゲート電極２１をマスクとして上方
から高濃度でＢ+を注入し、拡散してドレイン領域１２
及びＰ+ソース領域２３を形成する。Ｐ+ドレイン領域１
２及びＰ+ソース領域２３の深さは共に約４００ｎｍ幅
は共に約１０μｍであった。このようにして得られたＰ
-拡散領域１３とＰ+ドレイン領域１２のカバー状態を説
明するために図２（ｂ）のＡ部を拡大して図３に示す。Finally, as shown in FIG. 2B, after removing the silicon nitride film 7, Poly-Si is deposited to a thickness of about 400 nm by the CVD method and patterned to have a width of 6 μm.
m Poly-Si gate electrode 21 is formed. Then, using the Poly-Si gate electrode 21 as a mask, B + is injected at a high concentration from above and diffused to diffuse the drain region 12
And a P + source region 23 are formed. P + drain region 1
The depths of the 2 and P + source regions 23 were both about 400 nm and the width was about 10 μm. P thus obtained
In order to explain the cover state of the diffusion region 13 and the P + drain region 12, the portion A of FIG. 2B is enlarged and shown in FIG.
【手続補正１１】[Procedure Amendment 11]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１８[Correction target item name] 0018
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１８】図３に示す様に、動作時、特に電界集中を
生ずるＰ+ドレイン領域１２の下部エッジ１２ａは本実
施例で形成したＰ-拡散領域１３によってゆとりを持っ
てカバーされている。 ─────────────────────────────────────────────────────
As shown in FIG. 3, the lower edge 12a of the P + drain region 12 which causes electric field concentration particularly during operation is covered with a space by the P − diffusion region 13 formed in this embodiment. ─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年９月２日[Submission date] September 2, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施例（ＬＯＣＯＳオフセットドレ
イン）を示す前半工程断面図である。FIG. 1 is a sectional view of a first half process showing an embodiment (LOCOS offset drain) of the present invention.
【図２】本発明の一実施例の後半工程断面図である。FIG. 2 is a cross sectional view of a second half process of an embodiment of the present invention.
【図３】Ｐ-拡散領域（オフセット拡散領域）とＰ+ドレ
イン領域のカバー状態を示す拡大図である。FIG. 3 is an enlarged view showing a cover state of a P − diffusion region (offset diffusion region) and a P + drain region.
【図４】従来技術であるオフセットドレインを示す断面
図である。FIG. 4 is a cross-sectional view showing a conventional offset drain.
【図５】従来技術であるＬＯＣＯＳオフセットドレイン
を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional LOCOS offset drain.
【図６】従来技術を説明するための工程断面図である。FIG. 6 is a process sectional view for explaining a conventional technique.
【符号の説明】 １ Ｎ型シリコン（Ｓｉ）基板 ２，１２ Ｐ+ドレイン領域 ２ａ，１２ａ Ｐ+ドレイン領域の下部エッジ ３，１３ Ｐ-拡散領域（オフセット拡散領域） ５，１５ ＬＯＣＯＳ酸化層 ６ ゲート酸化膜 ７ シリコン窒化膜（Ｓｉ3Ｎ4） ９，１９ レジストパターン １０，２１ Ｐｏｌｙ−Ｓｉゲート電極 １１ Ｎ型（１００）シリコン（Ｓｉ）基板 ２０ 溝（凹部） ２３ Ｐ+ソース領域[Description of Reference Signs] 1 N-type silicon (Si) substrate 2, 12 P + drain region 2a, 12a P + drain region lower edge 3, 13 P − diffusion region (offset diffusion region) 5, 15 LOCOS oxide layer 6 gate Oxide film 7 Silicon nitride film (Si 3 N 4 ) 9,19 Resist pattern 10,21 Poly-Si gate electrode 11 N-type (100) silicon (Si) substrate 20 Groove (recess) 23 P + source region
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】全図[Correction target item name] All drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１】 [Figure 1]
【図２】 [Fig. 2]
【図３】 [Figure 3]
【図４】 [Figure 4]
【図５】 [Figure 5]
【図６】 [Figure 6]
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/316 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H01L 21/316
Claims (1)
成した後、該酸化膜上の所定位置に少なくとも２つの窒
化膜パターンを形成する工程と、 前記窒化膜パターンをマスクとして前記酸化膜をエッチ
ングし、且つ前記シリコン基板の（１１１）面に沿うエ
ッチングを含むエッチングを行って前記シリコン基板に
凹部を形成する工程と、 前記シリコン基板の凹部上方から該シリコン基板内へ反
対導電型の不純物を導入し、熱処理することによって該
反対導電型のオフセット拡散領域を形成する工程と、 前記窒化膜を除去した後、前記凹部にＬＯＣＯＳ酸化層
を形成する工程と、 前記ＬＯＣＯＳ配化層の一方の側面上を含む位置にゲー
ト電極を形成する工程、及び前記ゲート電極をマスクと
して、前記酸化膜を通して前記反対導電型の不純物を導
入し、熱処理することによって前記ＬＯＣＯＳ酸化層の
側面側に該反対導電型のドレイン拡散領域を形成する工
程、 を含むことを特徴とするＬＯＣＯＳオフセットドレイン
の製造方法。1. A step of forming an oxide film on a silicon substrate of one conductivity type, and then forming at least two nitride film patterns at predetermined positions on the oxide film; and using the nitride film pattern as a mask, the oxide film. To form a recess in the silicon substrate by performing etching including etching along the (111) plane of the silicon substrate, and impurities of opposite conductivity type from above the recess in the silicon substrate into the silicon substrate. And then heat treating to form an offset diffusion region of the opposite conductivity type; removing the nitride film, forming a LOCOS oxide layer in the recess; Forming a gate electrode at a position including a side surface, and using the gate electrode as a mask, impurities of the opposite conductivity type through the oxide film Introduced, heat treatment LOCOS offset drain method for producing characterized in that it comprises a step, to form a drain diffusion region of the reflected Taishirube conductivity type on the side surface side of the LOCOS oxide layer by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3301764A JPH0629313A (en) | 1991-11-18 | 1991-11-18 | Manufacture of locos offset drain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3301764A JPH0629313A (en) | 1991-11-18 | 1991-11-18 | Manufacture of locos offset drain |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629313A true JPH0629313A (en) | 1994-02-04 |
Family
ID=17900892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3301764A Pending JPH0629313A (en) | 1991-11-18 | 1991-11-18 | Manufacture of locos offset drain |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629313A (en) |
Cited By (6)
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|---|---|---|---|---|
| JP2002170888A (en) * | 2000-11-30 | 2002-06-14 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
| US7223648B2 (en) | 2005-06-17 | 2007-05-29 | Seiko Epson Corporation | Method for manufacturing a semiconductor element |
| JP2008258640A (en) * | 2008-05-07 | 2008-10-23 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US7629238B2 (en) | 2005-07-26 | 2009-12-08 | Dongbu Electronics Co., Ltd. | Device isolation structure of a semiconductor device and method of forming the same |
| US8404547B2 (en) | 2008-07-29 | 2013-03-26 | Seiko Instruments Inc. | Semiconductor device and manufacturing method thereof |
| JP2015506578A (en) * | 2011-12-29 | 2015-03-02 | 無錫華潤上華半導体有限公司 | Manufacturing method of semiconductor device |
-
1991
- 1991-11-18 JP JP3301764A patent/JPH0629313A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002170888A (en) * | 2000-11-30 | 2002-06-14 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
| US7224037B2 (en) | 2000-11-30 | 2007-05-29 | Renesas Technology Corp. | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs |
| US7541661B2 (en) | 2000-11-30 | 2009-06-02 | Renesas Technology Corp. | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs |
| US7790554B2 (en) | 2000-11-30 | 2010-09-07 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs |
| US7223648B2 (en) | 2005-06-17 | 2007-05-29 | Seiko Epson Corporation | Method for manufacturing a semiconductor element |
| US7629238B2 (en) | 2005-07-26 | 2009-12-08 | Dongbu Electronics Co., Ltd. | Device isolation structure of a semiconductor device and method of forming the same |
| JP2008258640A (en) * | 2008-05-07 | 2008-10-23 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US8404547B2 (en) | 2008-07-29 | 2013-03-26 | Seiko Instruments Inc. | Semiconductor device and manufacturing method thereof |
| JP2015506578A (en) * | 2011-12-29 | 2015-03-02 | 無錫華潤上華半導体有限公司 | Manufacturing method of semiconductor device |
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