JPH06291954A - Picture processor - Google Patents

Abstract

PURPOSE:To quicken the processing such as compression, expansion and code conversion. CONSTITUTION:A line memory required for each processing by a decoder 1300, a picture conversion section 1400 and a coder 1500 is preserved in an internal RAM 200. Data are transferred between the line memory and each section through DMA transfer. Data input from an external bus, data output to an external bus, coding, picture conversion and coding are executed in parallel. An address counter and an address register corresponding to the line memory are in existence in an internal bus DMA control section 300 and a working register 500. Data transmission reception between line memories are executed momentarily through exchange of contents of the address registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for handling image data or coded data thereof, and particularly compression of image data required for a facsimile machine, expansion of image coded data, conversion of image data (enlargement / reduction). ), An image processing device for converting image code data into another code.

[0002]

2. Description of the Related Art An image processing apparatus of this kind is required in a facsimile apparatus, other image communication apparatus, image file system and the like.

FIG. 35 shows an example of a conventional facsimile apparatus. In this facsimile apparatus, two compression / decompression devices (# 1) 8001 and (# 2) 8002 for decompressing received code data or compressing image data, and for enlarging / reducing image data (image conversion) are used. Image conversion device 8
003, which interface with both the system bus 8005 and the image bus 8006.

The received code data demodulated by the modem 8007 is buffered in the compressed data memory 8009 on the system bus 8005 and then decoded by, for example, the compression / expansion device (# 1) 8001, and the restored image data is converted into the image bus 8006. Upper image page memory 8010
Be deployed to. RAM8016 is used as a reference line memory.

When the image data of one page is restored and parameters such as the number of lines thereof are obtained, the enlargement / reduction ratio of this image data is determined and designated to the image conversion apparatus 8003. Then, the image conversion device 8003 executes enlargement / reduction processing of the image data on the image page memory 8010, and the processed image data is recorded image processing unit 80.
It is transferred to the printer 8012 via 11 and printed on the recording paper.

When a transmission original reading request is issued during the receiving operation, the transmission original image data read by the image scanner 8014 and processed by the read image processing unit 8015 is sent to the RAM (line buffer) 8016 on the image bus 8006. The other compression / decompression device (# 2)
It is encoded by 8002. The coded data is stored in the compressed data memory 8009. The RAM 8016 is used as an encoding line memory and a reference line memory.

Conventionally, such a compression / expansion device is shown in FIG.
The configuration was as shown in. In FIG. 36, 8050
Is an image bus unit for interfacing with the image bus, and 8051 is a system bus unit for interfacing with the system bus. These bus section 805
Through 0 or 8051, image data or code data is input / output as 16-bit or 8-bit parallel word data.

Regarding the encoding process, the reference line changing pixel detecting unit 805 for detecting the changing pixel address of the reference line.
2, a coding line change pixel detection unit 8053 that detects a change pixel address of a coding line, a coding mode determination unit 8054 that determines a coding mode (vertical, horizontal, pass) using these change pixel address information, A code table search unit 8055 that performs code allocation based on this determination result
And a code table (ROM) 8056.

Further, regarding the decoding process, the decoding table search unit 8058 for code analysis and the decoding table (RO
M) 8059, an a0 address calculation unit 8060 for calculating the starting point of the decoding line or the reference change pixel a0 (see CCITT recommendation T.4), and an image data drawing unit 8061 for drawing the image data of the decoding line. Reference numeral 8062 denotes a control unit that monitors and controls the state of the entire compression / expansion device.

[0010]

In the conventional compression / decompression device configured as described above, in the case of the compression operation, the image data is input in units of one word, the change pixel address is detected, encoded, and encoded. Since a series of processing of outputting data is performed serially, the compression processing time is expressed by the following equation. Processing time = image input time + coding processing time + code output time (Equation 1) The coding line memory and the reference line memory are placed in the external memory (RAM 8016 in FIG. 35) on the image bus, but the access time of the image bus Is quite large. This bus access time determines the lower limit of the time in the second term of Expression 1, and therefore there is a limit to the speedup.

Particularly, when a plurality of compression / expansion devices, and further an image conversion device are placed on a common bus as in the example of the facsimile apparatus shown in FIG. 35, the load on the common bus becomes heavy, so that it depends on the bus access time. The increase in processing time becomes remarkable.

When processing a coarse image, the second term of Equation 1
Since the time of the third term is smaller than that of the first term, the entire processing time is almost determined by the image input time of the first term. In contrast,
When processing a fine image, the encoding processing time of the second term increases, and since the code data also increases, the code output time of the third term also increases, so the overall processing time is long. Also,
The entire processing time greatly varies depending on the content of the processed image.

The same applies to the decompression operation. As is clear from the description of the operation of the facsimile apparatus shown in FIG. 35, when the image conversion of the restored image data is necessary, it is necessary to obtain the parameter for determining the enlargement / reduction ratio, and the image is reproduced until the entire page is restored. Cannot start conversion. Therefore, a large-capacity memory (image page memory 80 in FIG. 35) that can store one page of restored image data is stored.
10) is required.

Further, the image conversion device is independent of the compression / expansion device, and when the image conversion and the compression process or the expansion process are performed serially, the external bus must be accessed for the image conversion. In this respect also, there is a limit to the speeding up of processing.

The present invention has been made in view of the above problems, and is an image processing apparatus for executing at high speed a compression process, a decompression process, an image conversion process, and further a code conversion process which are necessary in a facsimile machine or the like. The main purpose is to provide.

[0016]

In order to solve the above-mentioned problems, the present invention provides, in one aspect, a processing block for decoding processing, a processing block for decoding processing, and image conversion in the main scanning direction. A processing block for processing, an internal memory for providing a plurality of line memories necessary for processing by these processing blocks, an external bus control block for interfacing with an external bus, each block and the internal An internal bus for transferring data to the memory, a DMA transfer control block for controlling DMA transfer of the line memory on the internal memory, and an external bus to the decoding processing block by controlling each block. Input operation of code data, input operation of image data from external bus to line memory in the internal memory, decoding A plurality of operations selected from a physical operation, an operation of the image conversion processing, an operation of the encoding processing, and an operation of outputting image data from the line memory on the internal memory or from the encoding processing block to an external bus. And a device control block for executing the above operation in parallel.

The present invention is not limited to such a configuration. As can be understood from the description of the claims and the description of the entire specification, the present invention includes various aspects and has a characteristic configuration in each aspect.

[0018]

The image processing apparatus of the present invention has the above-described configuration to perform an operation as a compression apparatus for executing the encoding process or the image conversion and the combination process of the encoding, the decoding process or the combination process of the decoding and the image conversion. Any of an operation as a decompression device to be executed, a combination process of decoding and encoding or a decoding, and an operation as a code conversion device to perform a combination process of image conversion and encoding are possible.

In any operation, the line memory on the internal memory is used to execute the processing, and the access to the external bus, which is required when the line memory is external, is unnecessary. Further, data can be transferred at high speed between the line memory and the processing block by DMA transfer. Furthermore, each processing of image conversion, encoding and decoding, and data input / output with an external bus are executed in parallel. Image conversion can be performed simultaneously inside the device in any of compression, decompression, and code conversion operations, and the external bus access required when performing image conversion separately outside the device is eliminated. According to this, extremely high-speed compression, decompression, and code conversion are possible.

[0020]

1 is a block diagram showing the schematic construction of an example of a compression / expansion device according to the present invention. The compression / decompression device 1 is an image processing device that combines the functions of a compression device, a decompression device, an image conversion (enlargement / reduction) device, and a code conversion device.

Structure of Facsimile Apparatus FIG. 2 shows an example of a facsimile apparatus using the compression / expansion apparatus 1. The compression / expansion device 1 is connected to the system bus 10 and the image bus 11.

In FIG. 2, on the system bus 10,
A processor block 13 including a microprocessor (MPU) and a DMA controller (DMAC) for controlling the entire facsimile apparatus and controlling the facsimile procedure.
A peripheral circuit block 14 including a gate array such as an address decoder, a memory block 15 including a ROM and a RAM for storing a control program and data, and compressed data mainly used for storing compressed data of a transmission document or a reception document. A memory 16, an operation panel 18 including switches and a display for operating the facsimile apparatus, a modem 19 for modulating and demodulating a line signal, and the like are also provided. Reference numeral 20 is a network control circuit (NCU), through which the facsimile apparatus is connected to a public telephone line network or the like.

The read image processing unit 2 is provided on the image bus 11.
1, a recording image processing unit 22 and a RAM 28. This R
The AM 28 is used as a line buffer for inputting / outputting image data by the compression / expansion device 1, and the required memory capacity may be about several lines.

The read image processing unit 21 processes an analog image signal input from the image scanner 23 and inputs it to the image bus 11, and a RAM as a work memory.
Has 27. The read image processing unit 21 performs A / D conversion on an analog image signal, shading correction on a digital image signal, MTF correction (edge emphasis), binary smoothing, multilevel smoothing, error diffusion (halftone). Processing) etc. are included.

The image scanner 23 scans a document and reads image information. The CCD image sensor 24,
The CCD image sensor 24 illuminates the original and gives an optical image.
The lens / light source unit 25 for forming an image on the document, and the reading mechanism control unit 26 for controlling the sub-scan feed mechanism for the document. The recording image processing unit 22 takes in image data from the image bus 11, performs necessary processing such as resolution conversion, and then supplies the image data to a laser beam printer (LBP) 29 for printing.

Overall Configuration of Compression / Expansion Device Next, referring to the system configuration shown in FIG.
The configuration of the compression / expansion device 1 will be described.

In FIG. 1, reference numeral 100 is an image bus control unit which realizes an interface function with the image bus 11. A RAM 200 is used as a line memory and parameter register for internal processing. This R
The AM 200 can also be accessed from the MPU (FIG. 2) of the processor block 13. Reference numeral 300 denotes an internal bus DMA control unit for controlling DMA transfer to the RAM 200 by an internal data bus (BE data bus) 1700, and 400.
Is a system bus control unit for interfacing with the MPU (FIG. 2).

Reference numeral 500 is a working register used as various registers, and RAM is actually used. Reference numerals 600 to 800 denote change pixel detection units for detecting change pixel addresses of 16-bit width data, and 900 to 1
100 is a FI for temporarily storing the changed pixel address information
FO buffer, 1200 is an arithmetic and logic unit used in connection with execution of internal processing, 1300 is MH / MR / MM
An R decoder, 1400 is an image conversion unit that performs image conversion (enlargement / reduction) in the main scanning direction of the image, and 1500 is MH / M.
An R / MMR encoder 1600 is a microprogram controller for controlling device operation.

The changed pixel detection units 600 to 800 and F
The IFO buffers 900-1100 can also be included in the corresponding processing blocks 1300-1100. However, in this case, since the changed pixel detection unit 600 and the FIFO buffer 900 are shared by the two processing blocks 1300 and 1500, it is necessary to add the same one.

Reference numeral 1700 is a DMA control bus, which comprises a DMA transfer request signal line from each section and a DMA transfer permission signal line to each section. Internal data bus (BE data bus) 18
00 is a 16-bit bus mainly used for transferring image data. 1900 is also a 16-bit internal data bus (BC data bus), which is mainly used for transfer of code data.

Although not shown in FIG. 1, a micro program control bus exists between the micro program control unit 1600 and each unit in the apparatus (see FIG. 6 and the like).

Encoder Configuration FIG. 3 is a block diagram of encoder 1500. In FIG. 3, the changed pixel address control unit 1502 outputs the changed pixel address of the reference line from the FIFO buffer 900 to the FI.
The change pixel addresses of the encoded lines are fetched from the FO buffer 1100, ordered, and input to the encoding mode determination unit 1504.

The coding mode determination unit 1504 determines the coding mode (pass, vertical, horizontal mode) based on the input changed pixel address information. The code table search unit 1506 searches the internal code table based on the result of the determination of the coding mode and assigns the code.

The packing processing unit 1508 converts the variable length code output from the code table search unit 1506 into 16-bit / word code data (word packing).
And output to the internal data bus 1900 or 1800 in word units. Reference numeral 1510 is a main sequencer for overall control of the encoder 1500. Internal RAM
A request for DMA transfer with 200 is issued from the main sequencer 1510. 1512 to 1518 are the corresponding processing units 1502 under the control of the main sequencer 1510.
It is a sub sequencer that controls 1508.

The encoder 1500 also has a register 1520 in which the width of one line (the number of words of image data of one line) is set through an internal data bus (BE data bus) 1800 and the number of codes of one line (of the code data of one line). It has a counter 1522 for counting the number of words). The value of this counter 1522 is the internal data bus 180.
Can be output to 0.

Reference numeral 1524 is a comparator provided in connection with MG3 encoding (described later), and compares the value of the register 1520 with the value of the counter 1800. This comparison output is reflected in the status signal of the microprogram control bus 1602. The micro program control unit 1600 can perform control such as designation of a coding mode and activation of the encoder 1500 via the micro program control bus 1602.
Moreover, the state of the encoder 1500 can be acquired.

Configuration of Decoder FIG. 4 is a block diagram of the decoder 1300. In FIG. 4, the code shift unit 1302 shifts the code data taken in from the internal data bus (BC data bus) 1900 by the code length for which decoding has been completed, and always provides the code analysis unit 1304 with undecoded code data. Code analysis unit 1304
Searches the internal decoding ROM according to the code data and sends the decoded code to the drawing unit 1308. However, MG3
When an extension code for encoding is detected, the input image data is transferred from the code shift unit 1302 to image data to the drawing unit analysis unit 1308.

Here, the MG3 coding means that one line of image data is coded into facsimile standard code data (MH, MR or MMR code) and the length of one line of code data is the length of the original image data ( Alternatively, when the total length of the image data and the extension code) is exceeded, it is an encoding method in which data obtained by adding the extension code (tens of bits) to the original image data is encoded and output. This MG3 encoding system is based on Japanese Patent Application No.
It is specifically described in the specification and drawings of No. 2669.

The a0 address operation unit 1306 is a FIFO
From the changed pixel address information of the reference line input from the buffer 900 and the decoded code input from the code analysis unit 1304, the start point of the encoded line or the address of the reference changed pixel a0 (see CCITT Recommendation T.4) is calculated. The drawing unit generates image data from the a0 address and white / black information, and outputs the generated image data to the internal data bus (BE data bus) 1800 in units of words (16 bits).

Reference numeral 1310 is a main sequencer for performing overall control of the decoder 1300, and 1312 to 1318 are corresponding functional blocks 1 under the control of the main sequencer 1310.
It is a sub-sequencer that controls 302 to 1318.
The DMA transfer request is issued from the main sequencer 1310.

The decoder 1300 also includes a comparator 1320 for detecting white data (words in which all bits are white bits) from the restored image data, and a continuous EOL number and one line width (code number) as internal data. Bus (BE data bus) 1
It has registers 1322 and 1324 which are set from 800. Based on the comparison result by the comparator 1320, the main sequencer displays a white line (a line in which all bits are white pixels).
The determination result is output to the microprogram control bus 1602 as a status signal.

Further, the main sequencer 1310 checks the decoding error for each line. The check result is output as a status signal. The micro program control unit 1600 has a micro program control bus 1
Through 602, control such as designation and activation of a decoding mode and status monitoring can be performed for the decoder 1300.

Structure of Image Conversion Unit FIG. 5 is a block diagram of the image conversion unit 1400. In FIG. 5, the register 1402 is a FIFO buffer 1000.
The change pixel address (14 bits) to be further input and color information (B / W) are held, and the register 1404 has an enlargement / reduction rate set through an internal data bus (BE data bus) 1800. The multiplier 1406 obtains the changed pixel address after the enlargement / reduction by multiplying the changed pixel address by the enlargement / reduction ratio.
Give to 408.

The drawing unit 1408 generates image data after scaling based on the given change pixel address and the color information given by the register 1402. This image data is output to the internal data bus (BE data bus) 1800 in word units via the register 1410. Reference numeral 1412 is a register in which the one-line width (word number) before conversion is set via the internal data bus 1800, and 1414 is a register for counting the one-line width (word number) after conversion. Reference numeral 1416 is a sequencer that controls each unit in the image conversion unit 1400, and also issues a DMA transfer request.

Arrangement of Arithmetic and Logical Operation Unit, Working Register, etc. FIG. 6 shows an arithmetic and logic operation unit 1200, a working register (RAM) 500 and its peripheral configuration, and a connection configuration with other functional blocks. In FIG. 6, 12
Reference numeral 02 is a 16-bit ALU (including a shifter) that forms the center of the arithmetic logic operation unit 1200.

As is apparent from the figure, the data from the RAM 200 or the like can be loaded into the ALU 1202 to perform the necessary calculation, and the calculation result can be written into the RAM 200 or the like. Also, a working register (RAM) 500
Operations and checks on the above registers can be performed via the ALU 1202.

In FIG. 6, 1204 and 1206 are ALs.
U1202 input registers, 1207 and 1207 are AL
A selector for selecting an input of U1202, 1210 is a local bus of the arithmetic logic operation unit 1200, and 1211 is an output buffer to the local bus 1210. 1212 and 1213 are a local bus 1210 and an internal data bus (B
E data bus) 1800 is a buffer for data transfer with the 1800.

Reference numeral 1214 is the microprogram control bus 1
A decoder that decodes the peripheral address on 602 and outputs a control signal for the ALU 1202 peripheral, 1216 is an R / W control circuit (decoder) that controls the read / write of the working register 500, and 1218 is an address controlled by the microprogram controller 1600. A pointer (counter) 1220 is a selector which selects the value of the address pointer 1218 or the address given from the microprogram control bus 1602 and outputs it to the address bus 1220.

Configurations of Micro Program Control Unit and System Bus Control Unit FIG. 7 is an explanatory diagram of the configurations of the micro program control unit 1600 and the system bus control unit 400.

The compression / expansion device 1 has two processing channels for encoding and decoding, and can perform processing by switching the channel for each line. In order to facilitate such processing execution, the system bus control unit 4
Register set 40 for channel 0 (CH0) at 00
2 and register set 404 for channel 1 (CH1)
There is. Further, the system bus control unit 400 includes a system bus timing control unit 406, a data buffer 408, and a DMA controller 41 as shown in FIG.
0, clock generator 412, etc. are also included.

The microprogram control unit 1600 has a general structure. In addition to a microROM 1601 storing a microprogram for processing various commands, a program counter 1603, a stack 1604, and a stack for controlling microprogram execution are provided. Pointer 1605, instruction register 1606, instruction decoder 160
Including 7.

The micro program control unit 1600 further inputs the macro command set in the command register in the macro ROM 1608 and the register sets 402 and 404, which stores the start address of the micro program for each macro command, to the macro ROM 1608. Selector 1609, micro ROM 1602
A multiplexer 1610 for switching the input of, a multiplexer 1611 for inputting a status signal on the microprogram control bus 1602 and an activation signal from the system bus control unit 400 to the multiplexer 1610 as a control signal.

Method of Using Internal RAM FIG. 8 is an explanatory diagram of a method of using the RAM 200. RAM
The linear address space of 200 is channel 0 (CH
0) A parameter register set area 201, a channel 1 (CH1) parameter register set area 204, and an image memory area 206 are used by being divided. Parameter register set area 20 for each channel
2, 204 are divided into coding command, decoding command, other commands, and parameter register areas 208 to 214 for DMA.

The image memory area 206 is divided into a plurality of line memory areas, and the divided areas are used as various line memories according to processing contents, as described later with reference to FIGS.

Configuration of Image Bus Control Unit FIG. 9 is a block diagram of the image bus control unit 100.
The image bus control unit 100 includes a DMA controller 102 for DMA transfer of image data, an address counter 104, and a data buffer 106. Under the control of the image bus control unit 100, the following four types of image data can be DMA-transferred. a) Transfer from I / O device (read image processing unit 21) on image bus to memory (ROM 28) b) I / O from memory (RAM 28) on image bus
Transfer to device (recorded image processing unit 22) c) Transfer from memory (RAM 28) on image bus to compression / expansion device 1 d) Memory on image bus (RA from compression / expansion device 1)
M28) transfer The address counter 104 corresponds to 4 for each DMA transfer.
It is composed of a set of address registers 110 and an incrementer 112. Similarly, the DMA controller 102
Includes four sets of transfer number registers 116 and decrementer 11
6 is included. The DMA controller 102 also has a D
A priority control 118 and a timing control unit 120 for priority control of the MA request are included.

Structure Related to Line Memory FIGS. 10, 11 and 12 show the internal bus DMA control unit 3.
00, the address register 50 defined on the working register 500 by the microprogram.
2 is a diagram for explaining the breakdown of the line memory 216 defined in the image memory area 206 of the RAM 2 and the RAM 200 and the corresponding relationship between them.

FIG. 10 shows the case of the encoded command processing, FIG. 11 shows the case of the decoded command processing, and FIG.
Indicates the case of code conversion command processing. In the following description, if necessary to distinguish the address register 502 and the line memory 216 from each other, FIG.
Names INPUT to D1R shown in FIG. 11 or FIG.
To use.

The internal bus DMA control unit 300 has the same number of address counters (A to J) 30 as the line memories 216.
2. DMA for controlling DMA transfer between the RAM 200 and processing blocks such as the encoder 1500 and the decoder 1300
A control unit 304, a selector 306 for selecting the address counter 302, and the like are included.

The area of the line memory 216 on the RAM 200, the address counter 302 and the address register 50.
2 corresponds one-to-one. Since the reference line line memories for the encoding process and the decoding process are for two channels, the external MPU is the encoder 150 in the image processing apparatus 1.
0, it is easy to operate as if there were two decoders 1300.

FIG. 13 shows the structure of the address register 502 defined on the working register 500. IN
Although the PUT address register is shown as an example, the structure of other address registers 502 is similar.

As shown, the lower 11 bits of the address register 502 are the head address of the line memory.
The upper 4 bits (A to E) are flag bits, and their meanings are as follows. A: "1" indicates that the corresponding line memory has valid data. B: "1" indicates that the content of the corresponding line memory is reduction target data. When C: "1", the content of the corresponding line memory is the final line data. D: The meaning differs depending on the register. E: "1" indicates that the content of the corresponding line memory is the enlargement target data.

The microprogram can operate and check these flag bits by using the arithmetic and logic unit 1200.

Operation of Compression / Expansion Device FIG. 2 shows the compression / expansion device 1 configured as described above.
The operation when used in the facsimile apparatus shown in FIG.

The image data input / output path of the compression / expansion device 1 is as follows. a) read image processing unit 21 → compression / expansion device 1 b) read image processing unit 21 → RAM 28 → compression / expansion device 1 c) compression / expansion device 1 → recorded image processing unit 22 d) compression / expansion device 1 → RAM 28 → recorded image processing The image bus control unit 100 of the compression / expansion device 1 supports the DMA transfer of such image data, but the read image processing unit 1 transfers the data to the RAM 28 by the DMA channel 0 and the recorded image processing from the RAM 28. The DMA channel 1 is transferred to the unit 22 (see FIG. 1).

Description of Compressing Operation (Outline) The MPU (FIG. 1) of the processor block 13 is
By issuing a macro command to the compression / expansion device 1, an operation instruction is given. The MPU first sets various registers in the system bus control unit 400. This also includes designation of coded channels CH0 and CH1.

After completion of the register setting, the command register 4 of the designated channel in the system bus control unit 400
Write the encoded command to 02A or 404B (FIG. 7). This command is decoded by the macro ROM 1608 through the selector 1609, and the start address of the encoding program is output. Micro R from this address
The encoding program in the OM 1601 is executed. Each processing block in the compression / expansion device 1 has a micro ROM 16
It is controlled by the program written in 01.

As already described, the line memory 216 and the address register 502 defined in the case of the encoded command processing are as shown in FIG. The contents or roles of each line memory are as follows. INPUT: Image data of input line (input buffer) CONVR: Image data of line before main scanning conversion CONVW: Image data of line after main scanning conversion CODING: Image data of encoded line BC1: Code data (output buffer) BC: Code Data (output buffer) C0R: reference line image data for coding channel 0 C1R: reference line image data for coding channel 1 D0R: reference line image data for decoding channel 0 D1R: decoding channel 1 Image data of reference line for reference (explanation along FIG. 16) FIG. 16 shows a simplified example of the flow of the encoding program. The compression operation will be described in detail along this flow.

When the encoded command is issued, the process 20
The parameter required by 01 is set in the parameter register set area 202 (CH0) or 204 (CH) of the RAM 200.
Load the working register 500 from 1). The start address of the area of the line memory 216 having the same name is set in the address register 502. Process 2002, Process 2
At 003, a DMA transfer request on the image bus 11 (transfer request from the read image processing unit 21 to the RAM 28, RAM 2
8), a DMA transfer process is performed. The micro program is
If there is a DMA transfer, the start address is set in the start address register 110 and the transfer word number is set in the transfer number register 114 of the image bus control unit 100, and the start flag is set to "1" (Fig. 9). After that, the image bus control unit 100 executes the DMA transfer.

In the next step 2004, the compression / decompression device 1 is read from the RAM (line buffer) 28 on the image bus 11.
Is a process of inputting one line of image data to the INPUT line memory on the RAM 200.

(Description with reference to FIG. 17: image data input)
The flow of this image data input processing is shown in FIG. Figure 1
In step 7, the microprogram executes the processes 2101 and 21.
In 02, it is confirmed that the image bus control unit 100 is not in operation and the activation flag of the image bus control unit 100 is in the reset state. If this is confirmed, in process 2103, the start address of the INPUT line memory is set in the address counter A (FIG. 10) in the internal bus DMA controller 300 via the internal data bus 1800 from the INPUT address register. In process 2104, the address of the external RAM 28 is set in one of the address registers 104 (FIG. 9) of the image bus controller 100.

Here, the read image processing unit 21 → RAM 2
It is assumed that image data is input through the route of 8 → compression / decompression device 1.

In process 2105, the image bus control unit 10
The number of words in one line is set in one of the transfer count registers 114 (FIG. 9) in 0. In processing 1706, the image bus control unit 100 is set to the memory read mode, and processing 21
It is started in 07, and the start flag is set to "1" in process 2108.

After the start-up, every time the image bus control unit 100 reads 1-word data, the incrementer 112
Increments the memory read address, and the decrementer 116 decrements the number of transfer words.

The image data read by the image bus control unit 100 is transferred to the INPUT line memory on the RAM 200 via the internal data bus (BE bus) 1800. This transfer is performed by the image bus control unit 100 in the RAM.
The DMA control unit 304 in the internal bus DMA control unit 300 issues a DMA transfer request to the internal data bus 18
This is executed by giving the control right of 00 to the image bus control unit 100. When the image data of 1 word is transferred to the INPUT line memory, the address counter A in the internal bus DMA control unit 300 is also incremented.

The above operation is repeated until the number of transfer words set in the image bus control unit 100 becomes zero. During the transfer, the process 2101 immediately returns.

When the transfer of one line is completed, INPUT
Image data for one line is stored in the line memory. Process 2
The processing after 109 is processing after one line is input.

In process 2109, the activation flag set in process 2108 is reset. In process 2110, the start address of the external RAM 28 containing the next line is calculated. In process 2111, the number of lines to be continuously processed by the encoded command is decremented, and the remaining number of processed lines is calculated. In process 2112, it is determined whether the line input immediately before the result of process 2111 is the final line. In the case of the final line, the C flag of the INPUT address register is set to "1" in process 2113. In processing 2114, the A flag of the INPUT address register is set to "
Set to 1 ". The state of these A and C flags is
As will be described later, in the process of exchanging the contents of the address register, it is delivered to the subsequent processing.

FIG. 14 shows a state when one line of data is stored in the INPUT line memory.
Here, it is assumed that the INPUT line memory is the memory area 216A starting from the address XXX. When the image data is completely input, the A flag of the INPUT address register is set to "1", and it can be seen that there is valid data in the INPUT line memory. Since the CONVR address register indicates YYY and its A flag is "0", it can be seen that the CONVR line memory is vacant in the memory area 216B starting from the address YYY.

(Continuing from the description according to FIG. 16) Returning to the flow of FIG. The microprogram I in step 2005
Check A = 1 in the NPUT address register,
If = 1, in step 2006, the CONVR address register is checked for A = 0.

INPUT A = 1 and CONVR A =
If it is 0, that is, if there is valid data in the INPUT line memory and the CONTVR line memory is empty, in step 2007, the INPUT address register and CO
Swap the contents of the NVR address register.

(Data Transfer between Line Memories) Data transfer between the line memories will be described with reference to FIGS. 14 and 15. FIG. 14 shows a state before execution of the process 2007. FIG. 15 shows address registers INPUT and CO
This is the state after the contents of the NVR have been exchanged. In FIG. 15, the CONVR address register is a memory area 216.
Of the memory area 216B, and the INPUT address register points to the start address YYY of the memory area 216B. In effect, the data input to the INPUT line memory is passed to the CONVR line memory,
This means that an empty area has been passed to the T-line memory.

As described above, since the method does not involve the actual data movement on the RAM 200, the data transfer between the line memories is instantaneously performed.

(Continuing from the description with reference to FIG. 16) Next processing 2
Reference numeral 008 denotes an enlargement / reduction (image conversion) process in the main scanning direction. In this process, the data in the CONVR line memory is converted and written in the CONVW line memory.

In this process 2008, the microprogram makes the following settings before activating the image conversion unit 1400. The address counters CONVR and CONV are provided to the address counters B and C in the internal bus DMA control unit 300.
Load the start address set in W (Fig. 1
0). The enlargement / reduction rate set in the parameter register 208 in the RAM 200 by the MPU (FIG. 1) of the processor block 13 is set in the register 1 in the image conversion unit 1400.
404 (FIG. 5). The number of words of the CONVR line is set in the register 1412. After such initial settings, the microprogram activates the image conversion unit 1400 and exits the processing 2008.

The image data in the CONVR line memory is DMA-transferred to the changed pixel detection unit 700 and converted into changed pixel data, and its address information is input to the register 1402. Registers 1402, 1 by multiplier 1406
The contents of 404 are multiplied to obtain the changed pixel address data after conversion. Based on this data and the color information in the register 1402, the drawing unit 1408 creates converted image data. The obtained converted image data is DMA-transferred to the CONVW line memory. In this case, the method of the DMA transfer from the CONVR line memory and the DMA transfer to the CONVW line memory is performed by the image bus control unit 100.
Is the same as the DMA transfer from the RAM to the RAM 200. When the conversion of one line is completed, the A flag of the CONVW address register is set to "1".

When reduction in the sub-scanning direction is required, determination is made as to whether or not the line data on the CONVW line memory is a thinning line and flag control is performed following the one-line main scanning conversion. The contents of this processing will be described later. When it is determined that the line is the thinning line, the A flag of the CONVW address register is not set.

In processes 2009 and 2010, it is determined whether or not there is valid data after conversion and whether or not the coding CODING line memory is empty. CONVW address register A = 1 and CODING address register A =
When it is 0, the address register C is processed in the next processing 2011.
By exchanging the contents of ONVW and CODING and loading the head address after the exchange into the corresponding address counter 302, the line memories CONVW and CODIN are exchanged.
Transfer data between G. In the case of thinning lines, this exchange is not done.

The process 2012 is a code process of data in the CODING line memory. If the encoder 1500 is not in operation, the microprogram sets the encoding mode (MH, MR, MMR, MG3) for the encoder 1500, sets one line width in the register 1520, and activates the encoder. However, in the case of the thinning line, since the A flag of the CONVW address register is "0", the encoder 1
Do not start 500.

The activated encoder 1500 has a CODIN
The image data in the G line memory is encoded by referring to either data in the encoded reference line memories C0R (CH0) and C1R (CH1), and the result is written in the encoded data memory BC1. Data reading from the CODING line memory and data writing to the BC1 line memory are performed through the internal bus DMA control unit 300. The operation of the internal bus DMA control unit 300 is the same as the case of data transfer from the image bus control unit 100 to the RAM 200.

The changed pixel address of the encoded line is detected by the changed pixel detecting section 800, and the changed pixel address of the reference line is detected by the changed pixel detecting section 600.

When the encoding of one line is completed, the A flag of the BC1 address register is set to "1". C
ODING address register and address counter C0R
The reference line is updated by exchanging the contents of (CH0) or C1R (CH1).

The microprogram is processed in steps 2013 and 2.
When the end of encoding and the vacancy of the BC line memory are confirmed in 014, the address registers BC1, BC are processed in processing 2015.
By exchanging the contents of the line memory BC1,
Transfers BC data.

In process 2016, code data is output from the BC line memory to the system bus 10 by DMA transfer. At this time, it is necessary to know the code amount to be output, but at the end of encoding, the counter 152 in the encoder 1500
The code amount can be known by referring to the contents of 2 (FIG. 3).

In processing 2017, it is judged whether or not the encoding of the set number of lines is completed, and if it is not completed, the processing 2
Return to 002. If the encoding is completed, the process 2018
Then, the processing of the encoded command is ended after waiting for all the code data to go out.

At the end of the encoded command, the C flag is "
Judgment is made based on whether or not the encoding of the final line set to 1 "has been completed. The state of the C flag is propagated through the address register as follows: INPUT, C = 1 → CONVR, C = 1 C = 1 of CONVR Then, after the image conversion is completed, CONV
W, C = 1 → CODING, C = 1 (Summary of compression operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, the image data input process (process 2004), the image conversion process (process 2008), the encoding process (process 2012), and the code data output process (process 2016) are performed in parallel. Operate. In addition, the DMA transfer (process 2002, process 2003) on the side of the image bus can be performed in a floating manner.

Therefore, the compression processing time of the main compression / expansion device 1 can be approximately expressed by the following equation. Processing time = max {image input time, image conversion time, coding time, code output time} (Equation 2) FIG. 18 shows how to use the line memory in the coding command processing. As can be seen from this figure, the line memories INPUT, CONVR are used for toggle, the line memories CONVW, CODING, C0R / C1R are used for circulation, and the line memories BC1, BC are used for toggle.

If the main scanning conversion is not performed, the process shown in FIG.
As noted at 8, the data in the CONVW line memory is passed directly to the CODING line memory.

Although the image data is input from the image bus 11 side in the above description, the compression / expansion device 1 can also input the data to be encoded from the system bus 10 as shown in FIG. Similarly, in the above description, the encoded data is transmitted via the RAM 200 to the system bus 10
However, it is also possible to output directly to the system bus 10 from the encoder 1500.

Description of Decompression Operation (Outline) The MPU of the processor block 13 first sets various registers relating to the decoding command processing.
In this, decoding channels 0, 1 (CH0, CH
The designation of 1) is also included.

After this register setting is completed, the MPU writes the decryption command in the command register 402A or 404A in the system bus control unit 400. This command is decoded by the macro ROM 1608 and the start address of the decoding program is output. The decoding program in the micro ROM 1601 is executed from this address.

As described above, the line memory 216 and the address register 502 defined in the case of the encoded command processing are as shown in FIG. The contents or roles of each line memory are as follows. DECODE: Image data of restored line D0R: Image data of reference line for decoding channel 0 D1R: Image data of reference line for decoding channel 1 CONVR: Image data of line before conversion CONVW: Image data of line after conversion OUT2: Output Line buffer OUT1: Output line buffer OUT: Output line buffer Code data is line memory D0R (CH0) or D1
The data restored by decoding with reference to the data of R (CH1) is expanded in the DECODE line memory. When the decoding of one line is completed, the contents of the DECODE line memory are transferred to the line memory D0R or D1R and are referred to when decoding the next line. At the same time, the contents of the line memory D0R or D1R are stored in the line memory CONV.
It is passed to R for image conversion. Image conversion is CO
This is performed for the data in the NVR line memory, and the converted image data is written in the CONVW line memory.

The converted data in the CONVW line memory immediately reaches OU if the OUT2 line memory is empty.
Passed to T2 line memory. The data in the OUT2 line memory is immediately transferred to the OUT1 line memory if the OUT1 line memory is empty. If the OUT line memory is empty, the data in the OUT1 line memory is
Immediately, this data is output to the OUT line memory and output to the outside.

In this way, CONVW, OUT2, OU
Each T1 and OUT line memory is a line-by-line FIFO
Acts as a buffer.

(Description along FIG. 19) FIG. 19 shows an example of the flow of the decoding program. Following this flow,
The decryption command processing will be described.

In process 3001, the parameters necessary for the decryption command process are set as the parameter register set 202 (CH0) or 204 in the RAM 200 as an initial setting.
The working register 500 is loaded from (CH1).

Decoding of one line is performed in process 3002, and this process will be described later in detail with reference to FIG.

In process 3003, the A flag of the DECODE address register is checked to determine whether the restoration of one line is completed. In process 3004, it is determined whether the CONVR line memory is empty. DECODE
If A = 1 of the E address register and A = 0 of the CONVR address register, the address register CONVR and the address register D0R or D1R are processed in processing 3005.
Of the address register D0R or D1R and the address register DECODE in step 3006.
The contents of are exchanged and data is exchanged between line memories.

As a result, the line memory D0R or D
The restored data is passed to 1R, and the next line is ready to be restored. The data that has been used as a reference line is passed to the CONVR line memory, and the memory area of the data that has been converted is passed to the DECODE line memory.
Now you are ready to restore the next line and the next image conversion.

In processes 3007 and 3008, the presence or absence of data to be converted and the availability of the CONVW line memory are checked.

In process 3009, the image conversion unit 1400 performs image conversion in the main scanning direction. The contents of this process are the same as the process 2008 of FIG. When sub-scanning direction conversion is necessary, thinning line determination and flag control are performed subsequent to main scanning conversion, the details of which will be described later.

Process 3010 is control of the line buffer. The details will be described later with reference to FIG.

It is checked in step 3011 if there is data to be output. In process 3012, the data in the OUT line memory is externally output. In processing 3013.3014, when there is a request for DMA transfer on the image bus side,
The transfer process is performed. This is the process 2 shown in FIG.
The same as 002 and 2003.

In step 3015, the end of the decryption command is determined, and if the end condition is not satisfied, step 3002
Return to. When the end condition is satisfied, in process 3016,
The data transferred to the CONVR line memory is returned to the line memory D0R or D1R in preparation for the next decoding command.

(Description with reference to FIG. 20: 1 line encoding)
FIG. 20 is a flow of the 1-line decoding process 3002 of FIG. In process 3101, the status signal indicating that the decoder 1300 is in operation is checked. If it is not in operation, in step 3102, the decoder 13
Check the start flag of 00. If it is confirmed that the startup flag is set (started), the process proceeds to step 3103, and if the startup flag is reset, the process proceeds to step 3115. When the decoder 1300 is in operation, it immediately returns.

The processing flow when the decoder 1300 is not in operation is as follows. In process 3115, the decoder 1
The internal bus DMA control unit 3 prepares to start the 300.
Address counter A and address counter I or J in 00, address register DECODE and address register D0R or D1R on the working register 500.
Load the contents of each.

After that, these address counters are automatically incremented each time one word is accessed in response to the DMA transfer request from the decoder 1300, and the write address of the restored data and the read address of the reference line data are designated.

In process 3116, the number of words in one line is set in the register 1324 of the decoder 1300 and the internal register (not shown) of the reference line change pixel detection unit 600. After such preparation, the decoder 1300 is started in the process 3117, the start flag of the decoder 1300 is set to "1" in the process 3118, and the process returns. The above is the line head processing.

After the process 3103, the decoder 1300 is set to 1
The data for the line is decrypted and the restored data is DECODE
It is a processing part after being obtained in the line memory.

In process 3103, the activation flag set in process 3118 is reset. In the process 3104, the status signal of the decoder 1300 indicating whether there is a decoding error is checked.

If there is a decryption error, a decryption error process is performed in process 3119. For example, a process of replacing the line having an error with the immediately preceding line or the white line is performed.

If there is no decoding error, the error-free data is restored in the DECODE line memory.
In order to indicate this, the A flag of the DECODE address register is set to "1" in process 3105.

In process 3106, the status signal of the decoder 1300 indicating that the restored line is a white line (all pixels are white) is checked. Each time the decoder 1300 restores one word, the comparator 1320 (FIG. 4) checks whether or not the data is white data, and when one line has been decoded, it is determined from the status signal that the line is a white line by a microprogram. You can check on the side.

If the line is a white line, step 3107 is executed.
A counter for counting continuous white lines at the upper end of one page or a counter for counting continuous white lines at the lower end of the page (both counters are prepared on the working register 500) is incremented.

In process 3108, the status signal of the decoder 1300 indicating whether the RTC code is detected is checked. In process 3109, it is determined whether to output the restored data to the outside. This judgment is made by register set 402 (CH0) or 40 in the system bus control unit 400.
4 (CH1) by referring to a specific register. The bit contents of this register are set by the MPU of the processor block 13.

When the line is not output, the process 31
At 10, set the B flag of the DECODE address register to "
1 ". Lines with the B flag set are
When outputting data, the data is ignored and not output to the outside. By such control, it is possible to perform control such that the MPU side cuts the white line at the upper end or the lower end of the page.

In process 3112, the number of lines to be continuously processed set by the MPU is decremented to obtain the number of remaining lines. Then, in processing 3113, the number of remaining lines is checked. If this is 0, processing 3114 determines DECOD.
Set the C flag indicating the last line of the E address register to "
Set to 1 ". If the number of remaining lines is not 0, return immediately.

In process 3120, the counter for the number of restored lines (prepared on the working register 500) is incremented. With this counter value, the number of lines on one page can be obtained. The number of lines is stored in the decoding command parameter register area 210 for the corresponding channel of the RAM 200 by the microprogram when the processing of one page is completed. This area can be directly accessed from the MPU.

(Description of FIG. 21: Line Buffer Control) FIG. 21 is a flowchart of the process 3010 (line buffer control) of FIG. In processing 3201 and 3202, CO
After confirming that A = 1 of the NVW address register and A = 0 of the OUT2 address register, the contents of the address registers CONVW and OUT2 are exchanged in process 3203.

As a result, the data in the CONVW line memory enters the OUT2 line memory, and the empty area extends to the CONVW line memory. The flag states of the address register are A = 1 for OUT2 and A = 0 for CONVW.

Data is exchanged between the line memories OUT2 and OUT1 in processes 3208, 3204 and 3205, and data is exchanged between the line memories OUT1 and OUT in processes 3209, 3206 and 3207. Process 32
At 07, the A flag of the OUT address register is set to "1". With the above processing, CONVW, OUT2, OU
Each T1 and OUT line memory is a line unit FIFO
It will be used as a buffer.

(Description with reference to FIG. 22: image data output)
22 is a flow of the image data output process 3012 of FIG. In process 3301, the image bus control unit 3301
Check whether or not is in operation, and if it is in operation, return. If it is not operating, it is checked in process 3302 whether the activation flag of the image bus control unit 100 is set. If the activation flag is "1", it means that the image bus control unit 100 has been activated and is not in operation. Therefore, the process proceeds to the process 3311 and subsequent line end processes.

If it has not been activated, the line head processing is started. In processing 2303, the B flag of the OUT address register is checked to determine whether to output the data of the OUT line memory.

If the B flag is not "1", the data is data to be output, and therefore, preparation for output by the DMA transfer is made. First, in process 3304, the start address is loaded from the OUT address register into the address counter 302 corresponding to the OUT line memory in the internal bus DMA control unit 300. In process 3305, the address of the external RAM 28 is set in one of the address registers 104 in the image bus control unit 100. In process 3306, the number of words in the output line is set in one of the transfer word number registers 114 in the image bus controller 100. In process 3307, the operation mode of the image bus control unit 100 is set. Here, the memory write mode is set. Then, in process 3308, the image bus control unit 100 is activated. In process 3309, the start flag in the memory write mode of the image bus control unit 100 is set to "1", and the process returns.

When the B flag is "1" in the process 3303, the data is not output, and the A flag of the OUT address register is reset to "0" in the process 3310 to ignore the contents of the OUT line memory. . This process achieves line thinning.

The process 3311 and subsequent processes are line end processes. In process 3311, the activation flag of the image bus control unit 100 set in process 3309 is reset. In process 3312, the E flag of the OUT address register is checked to determine whether the output line is the enlargement target line in the sub-scanning direction.

If it is not the enlargement target (E = 0), the second output of the data in the OUT line memory is unnecessary.
In processing 3313, the A flag of the OUT address register is set to "
It is reset to 0 "and the OUT line memory is released. If the line is an enlargement target line (E = 1), OU is reached in processing 2314.
Reset the E flag in the T address register. That A
Since the flag is "1", this data is output again, and as a result, enlargement in the sub-scanning direction (line interpolation) is achieved. In process 3315, the address of the external RAM 28 is updated to output the next line, and the process returns.

The end of the decoding command is judged by whether or not the data in which the C flag is set to "1" is output. The C flag (final line flag) is propagated as follows by exchanging the address register. DECODE, C = 1 → CONVR, C = 1 If CONVR, C = 1, after image conversion is completed CONV
W, C = 1 → OUT, C = 1 (Summary of decompression operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, a decoding process (process 3002) and an image conversion process (process 300) are performed.
9), the image data output process (process 3012) operates in parallel. Further, DMA transfer processing on the image bus side (processing 3
013, process 3014) can also operate in parallel with these.

Therefore, the expansion processing time of the compression / expansion device 1 can be approximately represented by the following equation. Processing time = max {decoding time, image conversion time, image data output time} (Equation 3) FIG. 23 shows how to use the line memory in the decoding command processing. As you can see from this figure, DECOD
Each line memory of E, D0R / D1R, and CONVR is cyclically used, and CONVW, OUT2, OUT1, O
Each line memory of the UT is also used cyclically.

Description of Code Conversion Operation Next, the code conversion operation will be described. This code conversion is to input a certain code data and convert it to another code data. For example, conversion from MR code to MMR code.

In the case of the code conversion operation, the code data to be converted is input from the system bus 10, decoded by the decoder 1300, and the restored data is written in the DECODE line memory. By the decoding operation already described, C
The data in the ONVR line memory is converted into an image. Up to this point, the decompression operation is exactly the same.

After that, the data in the CONVW line memory is the object of encoding. After that, the compression operation is exactly the same.

The above decoding, image conversion, and encoding processes can be repeated in order for each line to convert the code data for one page into another code.

In the case of this code conversion processing, the address register 502 and the line memory 216 shown in FIG. 12 are defined as already described. FIG. 25 is an explanatory diagram of how to use the line memory.

FIG. 24 is a flow of the code conversion program. Since the processes having the same numbers as those in the flow of FIG. 16 or FIG. 19 have the same contents, the description thereof will be omitted.

The following can be easily understood from the flow of FIG. a) Decoding process, image conversion process, encoding process, and two DMA transfer processes on the image bus side operate in parallel. b) Even if a decoding error occurs, the decoding error is checked and the decoding error process (process 3119 in FIG. 20) is performed in the 1-line decoding process (process 3002). The conversion is performed. Therefore, the coded data after conversion does not include a decoding error.

In the code conversion operation or the decompression operation, the number of lines in one page and the number of continuous white lines at the upper and lower edges of the page are obtained in the decoding process (process 3002) (processes 3120 and 3107 in FIG. 20). When the operation is completed, it is stored in the decryption command parameter register area 210 on the RAM 200. The MPU can read these parameters and use them for determining the enlargement / reduction ratio and the cut lines at the upper and lower ends of the page.

Description of image conversion (reduction) in the sub-scanning direction Reduction in the sub-scanning direction is realized by thinning out one line for every constant number of lines, and enlargement in the sub-scanning direction is for copying one line for every certain number of lines ( It is realized by performing (interpolation).

Here, the reduction operation in the sub-scanning direction will be described in detail centering on the method of determining thinning lines.

FIG. 26 is a conceptual diagram of the processing of the sub-scanning direction conversion operation. Related parameters (working register 5
00 are provided in the registers 551 to 557 prepared as follows) (however, for channel 0). C0-VCONV (sub-scan conversion ratio): register 551 C0-ZLINE (constant line number, which will be described later): register 552 C0-VCWRK (work register): register 553 C0-ZLWRK (work register): register 554 register X ( Register indicating address of RAM 200): Register 555 Non-white word counter: Register 556 N (constant): Register 557 (Description of algorithm that does not give priority to white line) CONV
Every time one line of valid data is obtained in the W line memory, C0-VCONV is integrated by the 16-bit ALU 1202. This integrated value is C0-VCWRK. The line in which the carry occurs when the ALU 1202 overflows when integrated is the target of thinning.

The carry of the 16-bit ALU 1202 comes out once every 65536 / (C0-VCONV) lines. If M = 65536 / (C0-VCONV), one line is thinned out to M lines, and the reduction ratio R is R = (M-1) / M = 1- (1 / M).

From this relationship, the MPU of the processor block 13 determines C0-VCONV from the reduction ratio R and sets it to the compression / expansion device 1.

FIG. 27A is an explanatory view of the integration process of CO-VCONV, which shows the lines of the image and the integrated value CO of each line.
-VCWRK is shown side by side. In the example shown here, since carry occurs on the fifth line, this line is set as a thinning line.

Such an algorithm is conventionally known. The copy line in the case of enlargement in the sub-scanning direction can be determined by the same algorithm, and the integration process is shown in FIG. 27 (b). In this example, since carry occurs on the 5th line, the 5th line is the enlargement target line, and this is encoded twice.

In the compression / expansion device 1, both the above algorithm and the improved algorithm described below can be selected.

(Explanation of Improved Algorithm) FIG. 28
FIG. 6 is an explanatory diagram of this improved sub-scanning direction reduction algorithm. The arrow indicates the position of the carry line. According to the above-mentioned conventional algorithm, the lines with carry are unconditionally thinned, so that there is a drawback that thin ruled lines are lost and the image quality is deteriorated.

This improved algorithm prevents such image quality deterioration by preferentially thinning out white lines. That is, C0-ZLINE is set to be smaller than the line thinning interval, a white line is searched in the range of C0-ZLINE from the line where the carry occurs, and the white line is thinned. CO-ZILI
If there is no white line in the NE range, the last (C0-ZLINE) line in this range is thinned out.

The white line referred to here is the number of non-white words ≦
A line that satisfies N. N is a value set by the MPU. If N = 0, all words are searched for a white word line as a white line.

(Explanation with reference to FIGS. 29 and 30) FIG. 29 is a flow of processing for determining thinning lines and setting flags. This processing is realized by a micro program written in the micro ROM 1601.
It is executed every time one line of data is generated in the VW line memory (immediately after the main scanning conversion process is completed in the process 3009 of FIG. 19 or FIG. 24 or the process 2008 of FIG. 16). In accordance with the flag information set here, lines are actually thinned in the subsequent restored data output process (process 3012 in FIG. 19 in the case of a decoding operation).

In FIG. 29, C0-Z is executed in processing 4001.
Decrement the LINE. Process 4002, 4003
To add to C0-VCONV and C0-VCWRK (update integrated value). In process 4004, it is checked whether a carry of the ALU 1202 (included in the status signal of the ALU 1202) has occurred.

Processing 4005A when carry is out
Then, when the carry is not output, the process is 4005B, and M
It is checked whether the PU sets the specific registers (402, 404) in the system bus control unit 400 to the white line priority thinning (the above-mentioned improved algorithm). When it is determined in the process 4005B that the white line priority thinning is not performed (when the above-described conventional algorithm is selected), the process returns, and when it is determined that the white line priority thinning is performed, the process proceeds to a process 4007.

When it is judged in the processing 4005A that the white line is to be thinned out, the CO-ZLWRK is processed in the processing 4006.
Is set to the initial value C0-ZLINE, and the processing 4007 is performed. If it is determined in the processing 4005 that the white line is prioritized thinning, the processing immediately proceeds to the processing 4007.

This processing 4007 is to check the data in the CONVW line memory and determine whether or not the condition for the thinning line is satisfied, the content of which is shown in FIG. This determination result is used as the next processing 4008.
Check with. If it is determined to be a white line, process 4
At 010, it is judged whether or not the range of C0-ZLINE has been checked, and if not checked, the process returns.

If it is determined that the inside of the range of CO-ZLINE has been checked, or if it is determined in step 4008 that the line is a white line, the B flag of the CONVW address register is set to "1" in step 4009 and the process returns. Now, in the subsequent process (process 3013 in FIG. 19), CONVW
The data in the line memory is treated as a thinned (reduction target) line.

FIG. 30 is a flow chart of the process 4007. In process 4101, the start address of the CONVW line memory is set in the register X. In process 4102, ALU1
The content of the address pointed to by register X is loaded into the accumulator (ACCA) of 202. This is a process of reading one word (16 bits) of data from the RAM 200 through the internal data bus 1800 (FIG. 1).

In process 4103, it is determined whether the data is white data in which all 16 bits are white pixels or non-white data including black pixels even with 1 bit. If it is non-white data, the non-white word counter (register 55
6) is incremented. In process 4106, it is determined whether or not the check for one line is completed. If it is not completed, the register X is incremented in process 4105 and the process 41
The process is repeated from 02.

When the check of one line is completed, the process 4
At 107, it is determined whether the count value of the non-white word counter is less than or equal to the set value N. If N or less, a flag indicating a white line is set in process 4108. Process 4
In 008 (FIG. 29), this flag is checked.

As is clear from the above description,
The compression / expansion device 1 can also perform only image conversion. It is also possible to perform the decompression operation without outputting the data at all, and to check the code data for an error or to detect the number of lines and the number of white lines at the upper and lower ends of the page at high speed.

Example of Operation of Facsimile Apparatus Next, an example of operation of the facsimile apparatus shown in FIG. FIG. 31 shows an explanatory flow.

In process 4500, the received code data for one line is transferred from the modem 19 to the compressed data memory 16. The received code data is facsimile standard code data. In process 4501, the compression / expansion device 7 performs code conversion of the reception code data of one line, and the conversion code data is transferred to the compression data memory 16. The encoding and decoding channels used at this time are designated by the MPU.

In processing 4502, the end of reception of one page is checked. If it is determined that the processing is not completed here, the processing 450
At 3, the presence / absence of a request for reading and reading the image data of the transmission original is checked. If there is a read request, in process 4505, the compression / expansion device 1 reads the transmission original image data from the RAM 28 or directly from the read image processing device 9 and compresses it, and the code data is transferred to the compressed data memory 16. This compression is executed for one line. The coding channel used at this time is designated by the MPU.

When the process 4505 is completed, the process returns to the process 4500. If it is determined in process 4503 that there is no read request, the process directly returns to process 4500.

When the reception of one page is completed, the processing 450
In step 4, it is judged whether or not the code conversion for one page is completed, and if it is not completed, the code conversion of the remaining received code data is continuously executed by the compression / expansion device 1 in step 4501a (step 501a).

When the code conversion of one page is completed, the compression / expansion device 1 executes the expansion and transfer of the decompressed image data to the recorded image processing section 22 for one line of the converted code data in the compressed data memory 16. . At this time MPU
Determines the enlargement / reduction ratio for adjusting the recording image size to the recording paper size of LBP based on the number of lines of one page obtained by the compression / expansion device 1 at the time of code conversion, and specifies it to the compression / expansion device 1. Similarly, white line cuts at the upper and lower edges of a page can be designated based on the number of continuous white lines at the upper and lower edges of the page obtained by the compression / expansion device 1. Also specify the decoding channel to use.

When the processing 4507 is completed, the processing completion of one page is checked in the processing 4508, and if not completed, the transmission original image read request is examined in the processing 4503a.
If there is no request, the process returns to the process 4506. If there is a request,
After one line of the transmission document image data is compressed in processing 4505a, the processing returns to processing 4506. Process 4508
If it is determined that the expansion recording of one page is completed in step 4, processing 4
At 503b, it is checked whether or not there is a request to read the transmission original image data. If there is a request, the continuous processing 4505b of image data input and compression up to the final line of the transmission original by the compression / expansion device 1 is started, and the end is waited in the processing 4509 and 4510.

As described above, the compression / expansion device 1 of the present invention is
By using only the table, the code conversion of the received code data or the expansion and recording of the converted code data and the compression operation of the transmission original image data can be performed in parallel. Further, since the parameters necessary for determining the enlargement / reduction ratio and the cuts of the upper and lower white lines at the time of code conversion are obtained, the necessary enlargement / reduction and white line cut processing are performed simultaneously with the decompression operation of the converted code data. be able to. LBP2 is usually 1m
Recording is performed at a constant speed of about s / line, but the compression / expansion device 1 of the present invention can easily follow this speed. Therefore, a large-capacity image page memory for accumulating the restored image of one page is not required.

When transmitting the code data of the transmission original stored in the compressed data memory 16, the compression / decompression device 1 converts the code data into the code data according to the capability of the destination facsimile machine, and the modem 19 modulates the code data to the line. Will be sent.

In this facsimile machine,
The original read by the image scanner 23 is LBP29.
Copy operation for printing with (1x copy, reduced copy,
Multi-copy) is possible. This will be briefly described.

The same size copying is performed by any of the following methods. In the first method, the original image data is read under the control of the image bus controller 100 of the compression / expansion device 1.
This is a method of performing DMA transfer to the recording image processing unit 22 via the AM 28. In the second method, the original image data is directly transferred from the read image processing unit 21 to the internal RAM 2 of the compression / expansion device 1.
00, and directly transfer this image data to the recorded image processing unit 22.

In the reduction copy, the original image data is input to the internal RAM 200 of the compression / decompression device 1 via the external RAM 28, the image data is reduced, and then the external RAM is used.
This is achieved by outputting to the recorded image processing unit 22 via 28.

In the case of multi-copy, the compression / expansion device 1 compresses the original image data and the compressed data memory 16
To store. Next, the compression / expansion device 1 expands the code data and transfers the restored data to the recording image processing unit 22, and the necessary number of copies is repeated. Reduction multi-copy is also possible by performing reduction during this decompression operation.

Another Embodiment (Structure) FIG. 32 is a block diagram of a compression / decompression device according to another embodiment of the present invention.

In this compression / expansion device 1A, a local bus control unit 5000 is added in order to connect a local memory dedicated to the compression / expansion device to the outside.
The local bus control unit 5000 is capable of performing DMA transfer of data with a local memory, and includes a data buffer 5001, an address bus interface 5002,
A DMA controller 5003 is included.

In order to extend the line memory on the internal RAM 200 to an external local memory, the internal configuration of the internal bus DMA control unit 300A differs from that of the internal bus DMA control unit 300 (FIG. 10) of the above-described embodiment. has been changed. The configuration other than this is the same as that of the compression / expansion device 1 of the above-mentioned embodiment.

FIG. 32 is a block diagram of the internal bus DMA control unit 300A. In FIG. 32, 350 is an address unit (A to J), which has a one-to-one correspondence with the line memory on the RAM 200. Each address unit 3
50 has the same internal configuration,
2. End address register 353 and comparator 354. The address counter (A to J) 352 in the address unit (A to J) 350 corresponds to the address counter (A to J) 302 in FIG.
00 for generating the address of the corresponding line memory area on 00.

Comparator 35 in each address unit 350
4 outputs "1" when the value of the address counter 352 matches the value of the end address register 353. This comparison output is given to the address counter 352 in the same address unit and is also output to the outside of the unit.

Corresponding to the address units (A to J),
Address counter (AE to JE) 355 for generating the address of the line memory extension area on the local memory
There is. The output of the comparator 354 in the corresponding address unit 350 is input to these address counters 354.

Besides this, there are an OR circuit 356 and a bus selector 357. The OR circuit 356 gives the OR signal of the output of the comparator 354 in each address unit 350 to the bus selector 357 as a selection signal. Bus selector 3
57 is an internal data bus 180 when the selection signal is "0"
0 is connected to the internal RAM 200 side and the internal data bus 1800 is connected to the local bus control unit 50 when the selection signal is "1".
Connect to the 00 side.

The address counter 352, end address register 353, and address counter 355 can be initialized through the internal data bus 1800.

The DMA control unit 304 and the address counter selection selector 306 are the same as those in FIG. However, the selection target of the selector 306 is the address unit 35.
An address counter 352 within 0 and an end address register 353.

Reference numeral 30 denotes an external RAM (local memory dedicated to the compression / expansion device) connected to the compression / expansion device 1A.

(Operation) Next, a specific operation of the compression / expansion device 1A will be described. The overall operation is the same as that of the compression / expansion device 1 of the above embodiment.

Here, the operation of inputting image data into the line memory on the RAM 200 will be described. FIG. 34
FIG. 4 is an explanatory diagram of memory access.

After initial setting of image bus control unit 100A, internal bus DMA control unit 300A is initialized. In this default setting, the microprogram
The address counter A and the end address register A 352 of the address unit A 352 have a start address (IN
PUT-START and end address (INPUT-
END) is set. Also, the address counter AE3
The start address (INPUT-EXT) of the INPUT line memory expansion area on the external RAM 30 is set in 55. The end address (INPUT-END)
And the start address (INPUT-EXT) are calculated or the working register 50
0 is prepared in advance in the register.

When activated in this state, the image data input from the image bus controller 100 through the internal data bus 1800 is written to the start address of the INPUT line memory area on the internal RAM 200. The address counter A352 is incremented each time one word is input. Therefore, IN on the internal RAM 200
Data is written in order from the beginning of the PUT line memory area.

The value of the address counter A 352 is INPU.
When incremented to T-END, the output of the comparator A354 becomes "1", the address counter A352 is disabled, and the address counter AE35
5 is enabled. Further, the bus selector 357 connects the internal data bus 1800 to the local bus control unit 5
Switch to the 000 side.

After that, the image data input through the internal data bus 1800 is written to the address on the external RAM 30 designated by the address counter AE357. Address counter AE355 each time 1 word is input
Is incremented. Therefore, the subsequent image data is written in order from the beginning of the INPUT line memory expansion area on the external RAM 30.

In this way, the writing is performed by automatically switching from the internal RAM 200 to the external RAM 30 while inputting the image data of one line. As a result, as shown in the lower part of FIG. 34, a long INPUT line memory that exceeds the memory area on the internal RAM 200 can be handled as if it exists on the internal RAM 200. Although the INPUT line memory has been described here, the same applies to other line memories. By such expansion, the restriction on the line memory length in the compression / expansion processing and the expansion / contraction processing is reduced.

Since the access to the extended area of the line memory is the access to the external RAM, it takes a longer time than the access to the memory area of the internal RAM 200. However, compared to a case where a line memory of the same length is secured in the internal RAM 200, there is a great advantage that the increase in the circuit scale of the compression / expansion device and the increase in cost are small.

Instead of comparing the memory address and the end address, the number of words is counted, and the count value is compared with a fixed value to compare the internal RAM 200 and the external R.
You may switch to AM30.

The present invention is not limited to the embodiments described above. According to the present invention, it is possible to realize a device that performs at least one of compression, decompression, and code conversion at high speed. The compression / expansion device according to the present invention is most suitable for an image communication device typified by a facsimile device, but is also suitable for similar image processing applications in an image file system, other systems or devices.

[0201]

As is clear from the above description, the present invention has the following effects.

Since the line memory required for image processing is on the internal memory, the number of times the external bus is accessed is greatly reduced, and since image processing and data input / output operations with the external bus are performed in parallel, processing speed is increased. Can be significantly speeded up.

Since the area obtained by dividing the linear address space of the internal memory according to the processing contents is used as the line memory, it is possible to flexibly deal with image processing of various contents.

Encoding processing is performed using the line memory on the internal memory, and data transfer with the line memory is DMed.
High-speed compression operation is possible by performing high-speed processing by A and executing internal processing and data input / output with the external bus in parallel.

By executing the image conversion process using the line memory on the internal memory, it is possible to perform image conversion at the same time as image data compression.

Decoding processing is performed using the line memory on the internal memory, and data transfer with the line memory is DMed.
A high-speed decompression operation is possible by performing high-speed processing by A and executing internal processing and data input / output with the external bus in parallel.

By executing the image conversion process using the line memory on the internal memory, the image conversion can be performed at high speed simultaneously with the decompression.

Image data compression, code data decompression, or code conversion can be performed at high speed by executing the decoding, coding, and image conversion processes using the line memory on the internal memory, and at the same time. Image conversion can also be performed at high speed.

By providing a line memory area on the internal memory, an address register holding the start address and flag information, and a DMA transfer address counter in a one-to-one correspondence, it is possible to perform compression, decompression or code conversion. Control of parallel operation of internal processing and data input / output with the external bus becomes easy.

By passing data between the line memories without actually transferring the data between the line memories, the overhead for the transfer between the line memories can be eliminated and the processing can be further speeded up.

When data input / output of the image processing apparatus is performed via the line buffer on the external bus, the data transfer operation between the line buffer and the I / O device can be performed without interrupting the operation of the image processing apparatus. Because you can
It is possible to avoid a decrease in processing speed due to waiting for data.

At the time of code conversion in which the decoding process and the encoding process are combined, the number of lines of one page and the number of white lines at the upper and lower ends of the page are obtained as the attribute of the conversion code, and this is read by the controller side on the external bus. be able to. Therefore, for example, when the image processing device is used as a compression / expansion device of a facsimile device, the control device uses the number of lines to reduce the image size to match the recording paper size before expanding the conversion code data. It is possible to determine the rate and cut line, execute image conversion for image size adjustment at the same time when decompressing, restore the image data after size adjustment directly, and record this directly. Does not require a large amount of image page memory to store.

By controlling the data output line by line, it is possible to cut continuous white lines at the top or bottom of the page or to perform a decompression operation in which no data is output.

By performing the error processing of the decoding error, it is possible to obtain the data which does not include the decoding error in the decompression operation or the code conversion operation. Moreover, since the decoding error is checked and the error processing is performed inside the apparatus, the processing speed is increased. The drop can be avoided.

The expansion or contraction in the sub-scanning direction can be performed simultaneously with the decompression operation or the code conversion operation.

Preserving the thin ruled lines on the image can be improved by preferentially thinning out lines having few black pixels in the reduction in the sub-scanning direction.

By switching the encoding and decoding channels, it is possible to easily operate one image processing device as two compression devices or decompression devices or code conversion devices from an external control device.

By preparing the external memory for expansion, it becomes possible to process a long line exceeding the limit of the storage capacity of the internal memory, and it is possible to suppress an increase in the storage capacity of the internal memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a compression / decompression device according to the present invention.

FIG. 2 is a block diagram showing an example of a facsimile apparatus using the compression / expansion device according to the present invention.

FIG. 3 is a block diagram of an encoder.

FIG. 4 is a block diagram of a decoder.

FIG. 5 is a block diagram of an image conversion unit.

FIG. 6 is a block diagram of an arithmetic logic operation unit and its peripherals.

FIG. 7 is a block diagram of a micro program control unit and a system bus control unit.

FIG. 8 is an explanatory diagram of how to use the internal RAM.

FIG. 9 is a block diagram of an image bus control unit.

FIG. 10 is a line memory for processing encoded commands,
Illustration of address counter and address register

FIG. 11: Line memory for decoding command processing,
Illustration of address counter and address register

FIG. 12 is an explanatory diagram of a line memory, an address counter, and an address register for code conversion processing.

FIG. 13: Contents of address register

FIG. 14 is a diagram showing a state before executing data transfer between line memories.

FIG. 15 is a diagram showing a state after data is transferred between line memories by exchanging contents of address registers.

FIG. 16 is a flowchart of a compression operation.

FIG. 17 is a flowchart for inputting image data.

FIG. 18 is a diagram showing usage and data flow of a line memory during compression operation.

FIG. 19 is a flowchart of a decompression operation.

FIG. 20 is a flowchart of 1-line decoding.

FIG. 21 is a flowchart of line buffer control.

FIG. 22 is a flowchart of image output.

FIG. 23 is a diagram showing how the line memory is used and the data flow during decompression operation.

FIG. 24 is a flowchart of a code conversion operation.

FIG. 25 is a diagram showing how the line memory is used and the data flow during a code conversion operation.

FIG. 26 is an explanatory diagram of parameters for image conversion in the sub-scanning direction.

27A is an explanatory diagram of a thinning line determination method for reducing in the sub-scanning direction, and FIG. 27B is an explanatory diagram of a copy line determination method for expanding in the sub-scanning direction.

FIG. 28 is an explanatory diagram of a thinning line determination method using an improved algorithm.

FIG. 29 is a flowchart of sub-scanning reduction.

FIG. 30 is a flowchart for checking data in the CONVW line memory.

FIG. 31 is a flowchart for explaining an operation example of a facsimile device.

FIG. 32 is a block diagram showing another example of the compression / decompression device according to the present invention.

FIG. 33 is a block diagram showing changes in the configuration due to expansion of the line memory.

FIG. 34 is an explanatory diagram of expansion of a line memory.

FIG. 35 is a block diagram showing an example of a conventional facsimile apparatus.

FIG. 36 is a block diagram of a conventional compression / expansion device.

[Explanation of symbols]

 1 Compression / Expansion Device 10 System Bus 11 Image Bus 13 Processor Block (MPU) 16 Compressed Data Memory 21 Read Image Processing Unit 22 Recorded Image Processing Unit 23 Image Scanner 28 RAM 29 Laser Beam Printer 30 External RAM 100 for Expansion 100 Image Bus Control Unit 102 DMA controller 104 Address counter 200 Internal RAM 216 Line memory 300 Internal bus DMA control unit 300A Internal bus DMA control unit 302 Address counter 350 Address unit 352 Address counter 352 End address register 354 Expansion judgment comparator 355 Expansion address counter 356 OR circuit 357 Bus selector 400 System bus control unit 500 Working register 502 Address register 600 Change screen 1600 microprogram control unit 1700 DMA control bus detection unit 700 changes the pixel detector 800 changes pixel detection unit 1200 arithmetic logic unit 1300 decoder 1400 image conversion unit 1500 encoder 1800 internal data bus 1900 internal data bus 5000 the local bus controller

Claims (18)

[Claims] 1. One or more processing blocks for specific image processing, a plurality of line memories necessary for executing the processing of the processing blocks, a control block for interfacing with an external bus, and the line memory. And an internal bus for transferring data to the block, and by controlling each of the blocks, to execute processing of the processing block, data input from the external bus, and data output to the external bus in parallel. And an image processing device having a control block. 2. The image processing apparatus according to claim 1, wherein the line memory comprises an area in which a linear address space of an internal memory is divided according to processing contents of the apparatus. apparatus. 3. A processing block for encoding image data, an internal memory for providing a plurality of line memories for accumulating image data or encoded data related to the encoding process, and an external bus. An external bus control block for interfacing with, an internal bus for data transfer to each of the blocks and the internal memory, a DMA control block for DMA transfer control of a line memory on the internal memory, By controlling a block, an input operation of image data from an external bus to a line memory on the internal memory, an operation of the encoding process, and a line memory on the internal memory, or for the encoding process. A device control block for executing the output operation of code data from the processing block to the external bus in parallel An image processing apparatus having: 4. A processing block for image conversion processing of image data in the main scanning direction, a processing block for image data encoding processing, image data related to the image conversion processing and the encoding processing, or An internal memory for providing a plurality of line memories for accumulating code data, an external bus control block for interfacing with an external bus, and an internal bus for data transfer to each block and the internal memory. A DMA control block for controlling DMA transfer of a line memory on the internal memory, and an input operation of image data from an external bus to a line memory on the internal memory by controlling each block, the image conversion Operation of the process, operation of the encoding process, and from the line memory on the internal memory, or the encoding From the processing block for processing,
An image processing apparatus having an apparatus control block for executing code data output operations to an external bus in parallel. 5. A processing block for decoding encoded data of image data, an internal memory for providing a plurality of line memories for storing image data related to this decoding processing, and an external bus. An external bus control block for interfacing with, an internal bus for data transfer to each of the blocks and the internal memory, a DMA control block for DMA transfer control of a line memory on the internal memory, By controlling the block, input operation of code data from the external bus to the processing block, operation of the decoding process, and image data from the line memory on the internal memory or from the processing block to the external bus And an apparatus control block for executing the output operations of the above in parallel. 6. A decoding processing block for decoding encoded data of image data, a processing block for image conversion processing of image data in a main scanning direction, and the decoding processing and the image conversion processing. An internal memory for providing a plurality of line memories for storing related image data, an external bus control block for interfacing with an external bus, and an internal bus for data transfer to each of the blocks and the internal memory. And a DMA control block for controlling DMA transfer of a line memory on the internal memory, and an input operation of code data from an external bus to the decoding processing block by controlling each block, and the decoding processing. Operation, the operation of the image conversion processing, and the output of image data from the line memory on the internal memory to the external bus. And an apparatus control block for executing operations in parallel. 7. A processing block for decoding encoded data of image data, a processing block for image conversion processing of image data in the main scanning direction, and a processing block for performing encoding processing of image data. And the decryption process,
An internal memory for providing a plurality of line memories for storing image data or coded data related to the image conversion process and the encoding process; an external bus control block for interfacing with an external bus; An internal bus for data transfer to each block and the internal memory, and a DMA of a line memory on the internal memory
A DMA control block for transfer control and an input operation of code data from an external bus to a processing block for the decoding process by controlling each block, and an external bus to a line memory on the internal memory Image data input operation, the decoding operation, the image conversion operation, the encoding operation, the line memory on the internal memory, or the processing block for the encoding processing from the external bus. And an apparatus control block for executing a plurality of operations selected in parallel from the output operation of the image data to the external bus from the processing block for the encoding processing Processing equipment. 8. The image processing apparatus according to claim 3, wherein the internal memory is divided into a plurality of line memory areas, and the DMA control block has the same number as the line memory areas. The device control block includes an address counter for creating a DMA transfer address, and the device control block includes the same number of address registers as the area of the line memory for holding flag information related to the head address of the area of the line memory. ,
The device control block loads the start address from the corresponding address register to the address counter corresponding to the area of the line memory required for the operation of the device, and uses the flag information of the address register to An image processing device characterized by managing a line memory. 9. The image processing device according to claim 8, wherein the device control block includes means for exchanging data between the line memories by exchanging contents between the address registers. Image processing device. 10. The image processing apparatus according to claim 3, wherein the external bus control block is provided on the external bus in parallel with internal processing and data input / output operations of the apparatus. DM between external device and external memory
An image processing apparatus comprising means for controlling A transfer. 11. The image processing device according to claim 5, 6 or 7, wherein the device control block obtains the number of lines of image data of one page restored by the decoding process, and the line number is obtained from an external bus. An image processing apparatus comprising means for storing in an accessible storage area. 12. The image processing device according to claim 5, 6, 7 or 11, wherein the device control block includes a number of continuous white lines at the top or bottom of the page of the image data restored by the decoding process. And an image processing apparatus including means for storing the data in a storage area accessible from an external bus. 13. The image processing apparatus according to claim 5, 6 or 7, wherein the control block includes means for controlling permission or prohibition of output of image data to an external bus for each line. An image processing device characterized by: 14. The image processing apparatus according to claim 5, 6 or 7, wherein the control block confirms, for each line, occurrence of a decoding error in the decoding process, and checks for a line where a decoding error occurs. An image processing apparatus comprising means for performing error processing. 15. The image processing device according to claim 3, wherein the device control block includes:
An image processing apparatus comprising means for controlling thinning or interpolation of lines for image conversion in the sub-scanning direction. 16. The image processing apparatus according to claim 15, wherein the device control block preferentially selects a line having a small number of words including black pixels as a thinning line for image conversion in the sub-scanning direction. An image processing apparatus comprising: 17. The image processing apparatus according to claim 8, wherein the line memory and the address register for a reference line of the encoding process or the decoding process are two.
An image processing apparatus, characterized in that there is a set, and means for selecting the set is included in the apparatus control block. 18. The image processing apparatus according to claim 3, wherein a means for interfacing with an external memory for expanding the line memory, and expansion for each line memory on the internal memory. And a means for expanding the line memory that needs to be expanded on the external memory.