JP3203352B2 - Data decompression processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decompression processing device, and more particularly to a data decompression processing device for decoding image data compressed and encoded for transmission or recording.

[0002]

2. Description of the Related Art Conventionally, as a data decompression processing apparatus, Japanese Patent Application Laid-Open No. 61-284178 and Japanese Patent Application Laid-Open
No. 76 is disclosed. This will be described below.

Generally, image signal data obtained by decomposing and expressing an image by two-dimensional scanning of a scanning line by horizontal (or vertical) main scanning and a vertical (or horizontal) sub-scanning direction orthogonal to the main scanning. As a code data format aimed at reducing the amount of data handled during data transmission or recording by compressing the amount, a modified Huffman code (hereinafter referred to as MH code) as a one-dimensional coding method using the scanning line as a unit is described. In order to further increase the data compression rate, a modified read code (hereinafter referred to as an MR code) is used as a two-dimensional encoding method utilizing the correlation between adjacent main scanning lines by the sub-scanning.

FIG. 14 is a block diagram showing an example of a general MH code decoder.

Conventionally, this type of MH code decoder includes a code memory 1401 and an MH decoding circuit 14 as shown in FIG.
02, pixel generation circuit 1403, image memory 1404
It is composed of

The code memory 1401 is a memory for storing MH code data. The MH decoding circuit 1402 reads, from the code memory 1401, the MH code of the decoding line for which decoding processing is to be performed, and outputs a white or black run length. The pixel generation circuit 1403 includes the MH decoding circuit 1
A continuous white or black pixel corresponding to the run length information output by 402 is generated and written to the image memory 1404. The image memory 1404 is an image data storage unit that stores at least one page of image data (the set of pixels).

The MH code data is divided into a plurality of
For example, Japanese Patent Application Laid-Open No. 61-284178 is known as a one-dimensional code decoding circuit that performs parallel processing by an H code decoder.

This is a one-dimensional code decoding circuit in a raster scan facsimile apparatus for decoding a one-dimensional code (that is, an MH code) from a higher-level device,
An EOL detection circuit for detecting the presence or absence of an EOL used for line synchronization; a code data storage circuit for storing at least one page of the one-dimensional code; and an output result of the EOL detection circuit for determining a next bit of the EOL last bit. A data address arithmetic circuit for calculating a storage address and a bit position in a word in the code data storage circuit, an index register for storing a storage address of a scan line first bit and a bit position in a word for each predetermined line, The EOL detection circuit is composed of two one-dimensional code decoding circuits and a control unit, and the EOL detection circuit stores at least two code registers for storing one word and m bits of the transferred one-dimensional code, and the code registers stored in the code registers. 12-bit input each for detecting whether EOL exists in the data of two words. (2m-11) zero detectors that output a low level when the EOL is detected by the bit output, and which zero detector detects one of the zero detectors when the zero detector becomes a low level. A binary encoder for outputting a binary code, wherein the control unit performs an address control of the code data storage circuit and a data set control to the code register and the index register. It is a code decoding circuit.

Next, the one-dimensional code decoding circuit will be described with reference to FIG.

In the following description, the MH for one page is taken as an example.
This is for the case where code data is divided into two areas A1 and A2.

In FIG. 16, an MH code decoding circuit includes a code data storage circuit 2, an MH code decoding circuit 3,
It comprises an L detection circuit 4, a data address operation circuit 5, an index register 6, and a control unit 7. The MH code data is transferred from the host device 1 to the code data storage circuit 2 and the EOL detection circuit 4 via the code data bus. The MH code data is stored in the EOL detection circuit 4 by the set signal b from the control unit 7, and is simultaneously stored in the code data storage circuit 2 by the write / read signal c and the address information d. At this time, if the EOL detection circuit 4 does not detect EOL (11 consecutive theoretical values "0" and one subsequent theoretical value "1"), the next MH code data is stored in the above procedure. If EOL is detected, EOL
The detection circuit 4 notifies the control unit 7 of the EOL detection signal h and transfers the EOL detection information g to the data address operation circuit 5. The data address calculation circuit 5 determines the next dot of the EOL from the storage address information 1 in the code data storage circuit 2 of the data stored in the EOL detection circuit 4 given in advance from the control unit 7 and the EOL detection information g, that is, The storage address information i and the in-word position information j of the head MH code data of the next scan line in the code data storage circuit 2 are calculated and output.

The control unit 7 stores the total scanning line number information a given from the host device 1 in advance, and
A write control signal e for storing the address information j output from the data address arithmetic circuit 5 when the number of the detection signals h reaches half the number of the scanning lines and storing the address information j in the index register 6 is output. And j. Since the MH code data of the code data storage circuit 2 is divided into areas A1 and A2 at the EOL by the value of the index register 6, the code data of the MH code data is used as decoding start address information of the area A1 at the time of decoding. By giving the write start address information to the storage circuit 2 and the address information i stored in the index register 6 as the read start address information of the area A2, the MH code data of the areas A1 and A2 is read by the write / read signal c. , MH of area A1
The code data is the MH code decoder B1 of the MH code decoding circuit 3.
And the MH code data of the area A2 is the MH code decoder B
2 to execute decoding and output video data.
When decoding of the area A2 is started, the bit position information j in the word is given by the address information d, and the decoding is executed after shifting to the bit position.

In the Japanese Patent Application Laid-Open No. 61-284178, the EOL detection circuit is described with an example, but is omitted.

Next, the processing of the MH code decoder B1 and the MH code decoder B2 of the MH code decoding circuit 3 will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 17 shows a block diagram of the MH code decoder.

FIG. 17 is a block diagram showing a configuration of the parallel-to-vertical conversion register 101, the decoding table storage circuit 102, and the video data generation circuit 10.
3. It is composed of a timing control circuit 104.

The parallel-to-parallel conversion register 101 shifts the MH code data one bit at a time according to the signal c ₁ from the timing control circuit 104, and supplies the data to the decoding table storage circuit 102. The decoding table storage circuit 102 stores the parallel register 1
The output 1 bit of 01 is stored in the input order, and when the content of the bit string matches a certain value stored in the decoding table storage circuit 102, binary run length data is output. With reference to the binary run length data output from the decoding table storage circuit 102, the video data generation circuit 103 at the next stage outputs white or black video data corresponding to the run length.

In FIG. 17, at the time of MH code decoding, MH code data is stored in the parallel / translation register 101 by a set signal f from the control unit 7 (shown in FIG. 16), and the code data storage circuit 2 (shown in FIG. 16) The MH code decoder B2 (shown in FIG. 16) that decodes the area A2 of ()) obtains the number of shifts (m−j) from the address information d from the control unit 7, ie, the bit position information j, and obtains (m−j) before decoding. ) By shifting the parallel-to-parallel conversion shift register 101, the area A2
Is obtained.

In this manner, since the two areas A1 and A2 are decoded in parallel, the decoding can be performed in a time that is close to 1/2 compared with the case where the entire area is decoded by one decoding circuit.

In the above description, the distribution area and M
Although the number of H code decoders is limited to two, the MH code decoder can also have (R + 1) by having R pairs of index registers, so that even faster code decoding can be performed.

Next, the case of processing by the MR code decoder will be described.

In the encoding by the two-dimensional encoding method (MR code), one scanning line is encoded by a one-dimensional encoding code, and each of the subsequent K-1 scanning lines is encoded by:
The encoding is performed by referring to the preceding scanning line (hereinafter referred to as a reference line).

FIG. 15 is a block diagram showing an example of a general MR code decoder. In the figure, an MR code decoder includes an image memory 1505 for storing binary image information,
A code memory 1501 for storing code data, a reference line image data read from the image memory 1505, a change point detection circuit 1503 for detecting a change point, and an MR code of a decode line to be decoded from the code memory 1501 to be read from the code memory 1501. Change point detection circuit 15 according to
MR that calculates the white or black run length by referring to the change point address of the reference line sent from 03
The decoding circuit 1502 includes a pixel generation circuit 1504 which generates white or black continuous pixels corresponding to the run from the run length obtained by the MR decoding circuit 1502 and writes the pixels on the image memory 1505.

The MR decoding circuit 1502 reads the code of the decoding line from the code memory 1501, and cuts out the continuous codes one by one.

If the extracted code is in the horizontal mode, the subsequent code is decoded as an MH code until two runs are obtained.

If the extracted code is not in the horizontal mode, the white or black run length is calculated with reference to the change point address of the reference line sent from the change point detection circuit 1503. There are three processes, and after the process is performed, the process proceeds with the code cut out or by selecting and executing the process.

Japanese Patent Application Laid-Open No. 1-212076 is known as an apparatus for shortening the time required for MR decoding processing by performing parallel processing of MR code data by a plurality of decoding means.

In this method, a plurality of decoding means are provided, an MR code is divided by detecting an end-of-line signal by a detection means for detecting an end-of-line which is a horizontal synchronization signal of the MR signal, and the decoding means is sequentially switched. The decoding of the MR signal is performed. The division of the MR code is performed such that the number of lines indicated by the K parameter of the MR code is processed by the same decoding means.

As described above, a high-speed image signal output can be obtained by dividing an MR code for each EOL code and decoding the MR code in parallel by a plurality of code decoding circuits.

[0030]

The first problem is that the speed is not increased as expected even if a plurality of decoding circuits are used. In the conventional technique, one page of code data (MH code, MR code) is converted into scan line units (M code).
In the case of an R code, the data is divided into units of the number of lines indicated by the K parameter) and processed in parallel by a plurality of code decoding circuits.
The processing time of each code decoding circuit is not uniform.

That is, in one page of code data,
The compression ratio of code data for each scanning line is different.
In a specific code decoding circuit (MH code decoding circuit and MR code decoding circuit), the expansion processing time of the code data changes depending on the compression rate of the code data and the code data amount. Therefore, when code data is equally divided by the number of scanning lines, the amount of code data processed by each code decoding circuit differs for each code decoding circuit, and the processing time of each code decoding circuit is not equalized. This is because the processing time of the code decoding circuit that requires the most processing time among the code decoding circuits is the processing time of the code data of one page, and each code decoding circuit does not always function optimally.

[Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to provide a data decompression processing device which can improve characteristics and performance at high speed.

[0033]

SUMMARY OF THE INVENTION A data decompression processing apparatus according to the present invention uses a compression ratio of a code data and a code data compression ratio in order to operate a plurality of decoding circuits in parallel and uniformly. Vary according to amount.

More specifically, as shown in the block diagrams of FIGS. 1-4, an EOL detection circuit (4 in FIG. 3) for detecting the presence / absence of an EOL used for line synchronization is provided with at least one page. A code data storage circuit (2 in FIG. 2) for storing a code, and a storage address and a word in the code data storage circuit for the next bit of the EOL last bit from the output result of the EOL detection circuit (4 in FIG. 3). A data address operation circuit (5 in FIG. 3) for calculating a bit position; an index register A (17 in FIG. 3) for storing a storage address of a scan line first bit and a bit position in a word for each predetermined line; The storage address and the bit position in a word (hereinafter, the value 1 of the index register A) of a certain scanning line first bit stored in the index register A and the next stored value The storage address of the first bit of the scanning line and the bit position in the word (the storage address of the first bit of the scanning line after the predetermined line and the bit position in the word, hereinafter referred to as value 2 of the index register A) and the predetermined line between them The compression ratio (compression ratio 1) of the code data (hereinafter referred to as code data 1) between the value 1 of the index register A and the value 2 of the index register is output from the number and the run length after the expansion of the code data given in advance. Compression rate calculation circuit (8 in FIG. 3), a compression rate register (9 in FIG. 3) for storing the result, and the processing performance of the code decoding circuit (15 in FIG. 2) given in advance and the code to be processed. A processing performance table storage circuit (1 in FIG. 4) for storing a processing performance table indicating a relationship with a data compression ratio.
0), the value stored in the processing performance table storage circuit (10 in FIG. 4) and the value of the compression ratio register (9 in FIG. 3) (the compression ratio 1), and its code data (the code data 1). A processing time calculation circuit (11 in FIG. 4) that calculates and outputs a processing time when the encoding / decoding circuit processes the following, a processing time register (12 in FIG. 4) that stores the result, and a processing time register (FIG. 4). A code for calculating the code data processing time for one page (total of the values stored in the processing time register) from the value stored in 4) 12), and processing the code data processing time for one page in parallel. A value obtained by dividing by the number of decoding circuits (hereinafter, an average value A by an average value of processing time required for one code decoding circuit) is obtained, and then the value stored in the processing time register (12 in FIG. 4) is calculated. The above average is added sequentially from the top Every time the value becomes closest to A, the storage address of the first bit of the scanning line and the bit position in the word stored in the index register A (17 in FIG. 3) corresponding thereto are selected and output by the number of code decoding circuits. A division point arithmetic circuit (13 in FIG. 4) for outputting the storage address at the end of the code data and the bit position in the word; an index register B (14 in FIG. 4) for storing the result; and at least two code decoding units It includes a circuit (15 in FIG. 4), an image memory (16 in FIG. 1), and a control unit (7 in FIG. 3).

[Operation] According to the present invention, the code data (MH compression code, MR compression code) constituting one image is divided into a plurality of codes, and the divided code data is subjected to a code data decompression process of a number equal to the number of divisions. The present invention is directed to a system in which blocks simultaneously perform code expansion processing and draw an image in a bitmap memory.

When one entire image is viewed in detail, the compression ratio of code data differs for each main scanning line. In general, the expansion processing time of the code data changes depending on the compression rate of the code data and the amount of the code data. Therefore, when the code data is equally divided by the number of main scanning lines, the processing time of each code data decompression processing block is not equalized, and the code that requires the most processing time among the code data decompression processing blocks is used. The processing time of the data decompression processing block becomes the processing time of the entire image, and a problem occurs that each code data decompression processing block does not function optimally.

Therefore, the processing time of each code data decompression processing block can be made uniform by optimizing the relationship between the processing performance of the code data decompression processing block and the compression rate and code data amount of the code data. .

That is, according to the present invention, the code data size processed by each code data decompression processing block is changed according to the compression rate of the code data, and the processing time of each code data decompression processing block is made uniform, so that the entire system is processed. An object of the present invention is to provide a code data decompression processor for optimizing a processing time.

[Configuration] The configuration of the present invention includes, for example, a control unit, an EOL code detection unit, a stack table, a processing performance table, a storage unit, a code data expansion processing block 1, a code data expansion processing block 2, and a code data expansion processing. Block 3.

[Operation] Next, the operation will be described. An EOL code is added to the code data at the beginning of the code and after the code string of one main scanning line.
OL + tag bit).

When data is received, the division point of the code data can be detected by detecting the EOL code. For example, when an EOL code is detected for every eight lines from the head of the image, the address from the head of the image is stored in the stack table. By referring to this stack table after receiving the code data of all the images, the compression rate of the code data for every eight lines can be known. In addition, the relationship between the compression rate of the code data measured in advance and the processing performance is stored in the processing performance table.

From these two pieces of information, the code expansion processing time for every eight lines and the expansion processing time for all code data can be known.
By dividing the expansion processing time of all the code data by the number of divisions, the processing time of one averaged code data expansion processing block can be obtained.

The processing time for every eight lines is added from the top, and the processing range of one code data decompression processing block until reaching the processing time of one averaged code data decompression processing block is determined. The processing time from eight lines is added, and the processing range of one code data decompression processing block is set to reach the processing time of one averaged code data decompression processing block. The processing range of the data decompression processing block is determined. In this way, the processing time of each code data decompression processing block is averaged.

In this example, the compression rate of the code data is determined in units of 8 lines. However, the unit for determining the compression rate of the code data is made finer (for MR compression codes,
A unit that can be divided is limited by a parameter), and a more appropriate division range can be determined by further subdividing the relationship between the compression ratio of code data and processing performance.

[Effect] According to the present invention, code data (MH compression code, MR compression code) constituting one image is divided into a plurality of pieces, and the divided code data is simultaneously processed by a number of processing blocks equal to the number of divisions. In a system that performs code decompression processing and draws an image in a bitmap memory, the code data size processed by each code data decompression processing block is changed according to the compression ratio of the code data, and the processing time of each code data decompression processing block is reduced. By uniforming, it is possible to optimize the processing time as a whole.

The details will be described below with reference to the means of the present invention.

The index register A stores the storage address of the first bit of the scanning line and the bit position in the word for each predetermined line from the top of the code data.

The compression ratio calculation circuit sequentially stores the storage address and the bit position in a word (hereinafter, the value 1 of the index register A) of one scanning line head bit stored in the index register A and the next. The scan address and the bit position in the word (hereinafter referred to as index register A value 2), the predetermined number of lines between them, and the run length (code) The compression ratio (compression ratio 1) of the code data (code data 1) between the value 1 of the index register A and the value 2 of the index register A is output from the data decoded image is a rectangle.

The compression ratio register stores the result.

The processing performance table gives the relationship between the compression rate of the code data to be processed and the processing performance of the code decoding circuit given in advance.

The processing time calculation circuit calculates the values of the processing performance table and the compression ratio register (compression ratio 1) and the code data amount thereof (the two indices used when calculating the compression ratio based on the data amount of the code data 1). The processing time of the code data (code data 1) is calculated from the difference between the values of the register A.)

The processing time register stores the result.

The division point calculation circuit obtains the code data processing time for one page (total of the values stored in the processing time register) from the value stored in the processing time register. Next, a value obtained by dividing the code data processing time for one page by the number of code decoding circuits for parallel processing (hereinafter referred to as an average value A by an average value of the processing time required by one code decoding circuit) is obtained. Next, the values stored in the processing time register are sequentially added from the top, and each time the value becomes closest to the average value A, the storage address of the scan line head bit stored in the corresponding index register A is added. And the number of bit positions in the word are selected and output by the number of code decoding circuits, and finally the storage address at the end of the code data and the bit position in the word are output.

The index register B stores the result.

The code decoding circuit performs MH code decoding or MR code decoding in accordance with the storage address of the first bit of the scanning line stored in the index register B and the bit position in the word, and writes the result to the image memory.

As described above, the functioning of each unit allows
The processing time of each code decoding circuit is substantially uniform, and the processing time of one page of image data can be optimized.

[0057]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a data decompression processing device according to an embodiment of the present invention. In FIG. 1, 1
Is a higher-level device, 20 is a decoding unit, 21 is a dividing unit, 16
Is an image memory.

FIG. 2 is a detailed block diagram of the decoding unit 20 of FIG.

In FIG. 2, 2 is a code data storage circuit, and 15 is a code decoding circuit.

FIGS. 3 and 4 are detailed block diagrams of the dividing section 21 of FIG.

In FIG. 3, reference numeral 4 denotes an EOL detection circuit;
Is a data address operation circuit, 7 is a control unit, 17 is
The index registers A and 8 are compression ratio calculation circuits, and 9 is a compression ratio register.

In FIG. 4, 10 is a processing performance table storage circuit, 11 is a processing time operation circuit, 12 is a processing time register, 13 is a division point operation circuit, and 14 is an index register B.

The overall processing flow of the present invention is briefly described as follows.

The code data is transferred from the host device 1 to the code data storage circuit 2 and the end of line (EOL) detection circuit 4 and stored therein. Detection circuit 4, control unit 7,
The data address arithmetic circuit 5 stores, in the index register A17, the stored address information i and the bit position information j in the word of the leading code of the next scanning line in the circuit 2 for each predetermined number of scanning lines. Code data of the circuit 2 is divided from the region D ₀ to D _m by the value of the index register A17. Compression ratio calculation circuit 8, compression ratio register 9, processing performance table storage circuit 10, processing time calculation circuit 11, processing time register 12, division point calculation circuit 13, index register A1
7, assigns the region D ₀ as the processing time of each code decoding circuit is averaged by an index register B14 of the D _m in each code decoding circuit. The code decoding circuit 15 processes the code data of the circuit 2 in parallel and writes the code data in the image memory 16.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.

Code data (MH code data or MR code data) from the host device 1 via the code data bus
Is transferred to the code data storage circuit 2 and the EOL detection circuit 4. The code data is stored in the EOL detection circuit 4 by the set signal b from the control unit 7, and is simultaneously stored in the code data storage circuit 2 by the write / read signal c and the address information d. At this time, the EOL detection circuit 4 outputs EOL (11 consecutive logical values “0” and 1
If one logical value "1" is not detected, the next code data is stored in the above procedure.

If an EOL code is detected, EOL
The detection circuit 4 notifies the control unit 7 of the EOL detection signal h and transfers the EOL detection information g to the data address operation circuit 5.

The data address operation circuit 5 stores the information 1 and E stored in the code data storage circuit 2 of the data stored in the EOL detection circuit 4 given from the control unit 7 in advance.
Based on the OL detection information g, the next address of the EOL, that is, the storage address information i and the in-word position information j of the leading MH code data of the next scan line in the code data storage circuit 2 are calculated and output.

The control section 7 stores the total scanning line number information a given from the host device 1 in advance, and outputs the first EOL detection signal h (EOL added to the head of the code data of one page). Upon reception, the address information i and the bit position information j output from the data address arithmetic circuit 5
Is a write control signal e to be stored in the index register A17.
Is output. Thereafter, the number of times of the EOL detection signal h is counted and the address information i and the bit position information output from the data address arithmetic circuit 5 when the number of scanning lines reaches a predetermined number of scanning lines (hereinafter referred to as the number of scanning lines V). A write control signal e for storing j in the index register A17 is output.

The EO added to the end of the code data
L (the RTC is added to the end of the code data of one page, and this EOL is a part thereof). The address information i output from the data address arithmetic circuit 5 when the EOL detection signal h detecting the EOL detection signal h is detected. And a write control signal e for storing the bit position information j in the index register A17 and storing the information i and j. The above process is repeated until the reception of the code data of one page is completed. Code data code data storage circuit 2 is divided from D ₀ to D _m bordering the EOL for each scanning line number V by the value of the index register A17.

Next, the control unit 7 outputs an operation instruction signal p for causing the compression ratio operation circuit 8 to execute the operation, and the compression ratio operation circuit 8 outputs the start address of the scanning line stored in the index register A17. The information i and the bit position information j are sequentially processed from the beginning, and the storage address of the first bit of the scanning line and the bit in the word are stored for the address information i and the bit position information j at the beginning of two consecutive scanning lines. The difference between the position and the storage address of the first bit of the scanning line stored next and the bit position in the word (that is, the amount of code data between the address information i and bit position information j at the beginning of two consecutive scanning lines) and scanning The number of lines V, and the run length of the pre-given one-scan-line code data after decompression (the post-decompression image is assumed to be rectangular; Calculates and outputs each to receive an operation instruction signal p compression ratio of the code data from the L), to set the compression ratio register 9.

That is, the first address information of the code data is set as address information i ₀ and bit position information j ₀ , and the index register A
The address information and bit position information stored in 17 are address information i _n , bit position information j _n (n = _{1 to m} ), the address information at the end of the code data is address information im _{+ 1} , and the bit position information is bit address information. When the bit position information j _{m + 1} is set, the compression ratio D _0c of D ₀ is as follows: D _0c = number of bits after decompression of code data / number of bits of code data = run-length L × number of scan lines V / ((i ₁₋ i ₀ ) × the number of bits of one word + (j ₁ −j ₀ )) Similarly, the compression ratio D _mc of D _m is D _mc = the number of bits after decompression of the code data / the number of bits of the code data = It is given as the run length L × scan line number _{V / ((i m + 1} -i m) × 1 number of words bits _{+ (j m + 1 -j m} )).

The compression ratio register 9 stores the result.

The processing performance table is a relation between the compression rate of the code data to be processed by the code decoding circuit described later and the processing performance, and is given in advance. (One example is shown in FIG. 5.) Hereinafter, description will be made based on the drawings.

FIG. 5 is a diagram showing a processing performance table of the data decompression processing device of the present invention.

In general, the code data decoding processing performance of a code decoding circuit is unique to the circuit, and varies depending on the compression ratio of the code data to be processed.

In the figure, the compression ratio is expressed by the ratio of the data amount of the encoded data to the original image as a result of decoding the encoded data, and is as follows.

[0079] Further, the processing performance is a value obtained by dividing the processing time when decoding a certain set of code data by the code data amount (the number of bits), and comparing the result with the compression rate of the code data. When calculating the processing performance, in a general document, there is little change in black and white (white: logical value “0”, black: logical value “1”) with respect to the scan line of the original image (run for one code data). A portion having a large length value (for example, 1302 and 1304 in FIG. 13) and a portion having a large change in black and white (a small run-length value for one code data) (for example, a network in a portion 1303 in FIG. 13). Part). In general, a portion having a large change in black and white tends to have a small compression ratio, and a portion having a small change in black and white tends to have a large compression ratio. Therefore, in a one-page document, a portion having a small change in black and white and a portion having a large change in black and white are picked up, and the compression ratio and processing performance of the portion are obtained.

The control unit 7 outputs an operation instruction signal q for causing the processing time operation circuit 11 to execute an operation. The processing time operation circuit 11 outputs a processing performance table, a compression ratio register, and a code data amount thereof (the compression ratio). Is calculated as the difference between the values of the two index registers A used when the calculation is performed.) The processing time of the code data is calculated and output each time the calculation instruction signal q is received, and is set in the processing time register 12. I do.

The case of calculating the processing time of D ₀ will be described below.

First, the compression ratio register is obtained from the processing performance table.
D_0cSearch for processing performance corresponding to the value closest to the value of
You. If the processing performance value is t₁ And if
Note D ₀ Processing time D_otIs D_0t= T₁ × ((i₁ −i₀ ) X number of bits in one word +
(J₁ −j₀ )) The same applies to the above D_m Processing time D_mtIs D_m Corresponding to
Processing performance is t_m Then D_mt= T_m × ((i_{m + 1} −i_m ) X number of bits per word
+ (J_{m + 1} −j_m )) Is given as

The processing time register 12 stores the result.

The control unit 7 stores the data in the processing time register 12
Of processing time of divided area of one page
s, and causes the division point operation circuit 13 to execute the operation.
And outputs a calculation instruction signal r. The division point calculation circuit 13
One page from the value stored in the processing time register 12
Minute code data processing time (stored in processing time register 12)
(Sum of processing time s values). next,
A code for processing the code data processing time for one page in parallel
Divided by the number of signal decoding circuits (hereinafter the average value T_A : One note
(The average value of the processing time required by the signal decoding circuit). Next
In addition, each of the codec circuits has the D₀ To D_m Continuous throat
Is determined to be processed. Processing time register 12
D stored in_0t, D_1t, D_2t...
First D_0t+ D_1t+ D_2t+ ... + D_lt≧ T_AWhen it becomes
D_0t+ D_1t+ D_2t+ ... + D_ltAnd D_0t+ D_1t+ D_2t+ ... +
D_{(l-1) t}And T_A One code decoding up to
No. circuit. That is, D_0t+ D_1t+ D_2t+ ... +
D_{(l-1) t}Is T_A , The above D₀ To D
_l-1 Are assigned to one code decoding circuit.

At this time, address information i and bit position information j corresponding to D ₁ stored in the index register A are set in the index register B.

Next, D _lt + D _{(l + 1) t} + D _{(l + 2) t} +... + D
when it becomes _{kt ≧ T A, D lt +} D (l + 1) t + D (l + 2) t + ...
Compare + D _kt with D _lt + D _{(l + 1) t} + D _{(l + 2) t} +... + D _{(k-1) t} and compare D _lt + D _{(l + 1) t} + D _{(l + 2) t} +. + D _kt is T _A
Allocate space to D _K to a different one code decoding circuit from when D _l was close to.

At this time, address information i and bit position information j corresponding to D _{k + 1} stored in the index register A are set in the index register B.

In the same manner, the areas from D ₀ to D _m are allocated to each code decoding circuit.

However, at the time when the assignment to the immediately preceding code decoding circuit from the end is completed, the remaining area is assigned to the last code decoding circuit. The bit position information j is stored.

The index register B stores the result.

The code decoding circuit 15 performs a code decoding process of the MH code or the MR code by the control signal w from the control unit 7 in accordance with the storage address of the first bit of the scanning line stored in the index register B and the bit position in the word. Start and write the result to the image memory 16.

FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG.
This is shown in FIG. 10, FIG. 11, and FIG.

When processing the MR code data, the storage address of the first bit of the scan line stored in the index register A and the bit position in the word are determined by the K parameter (in the two-dimensional encoding, one scan is used). After the line is encoded by the one-dimensional encoding code, the following K-
Each of the one scan line is encoded by referring to the previous scan line. ) Is stored for each predetermined line which is a multiple of a positive integer.

Next, the operation of this embodiment will be described with reference to a specific example.

FIG. 13 shows a specific example of image data. Reference numeral 1301 denotes a print range on paper, in which a character string 1302, a graph and its description 1303, and a circuit diagram 1304 are expressed. Which indicates that.

Further, D ₀ -D shown on the left side of FIG.
D ₁₅ indicates the region D ₀ to D _15, → represents the division point.

An encoded version of this is sent from the higher-level device.

Hereinafter, the case of the MH code will be described.

In this example, the code decoding circuit A, the code decoding circuit B, the code decoding circuit C, and the code decoding circuit D
The case where the parallel processing is performed by the four code decoding circuits will be described.

Now, as for the total number of scanning lines of an image, the run length value after the expansion of the code data of 1600 lines and one scanning line is assumed to be 1000. when storing the word in the bit positions in the index register a, it is divided from the street D ₀ which is shown outside the frame of FIG. 13 to 16 of the region of the D _15.

The original image data amount (the number of bits) of each area is 1000 × 100 = 100000 bits. The storage address information i and the bit position information j in the word stored in the index register A are as shown in Table 1. (1 word is 16 bits).

[0102]

[Table 1] Table 2 shows the amount of code data (the number of bits) in each area.

[0103]

[Table 2] Table 3 shows the compression rate of the code data of each area in units of 0.5.

[0104]

[Table 3] It is also assumed that the values in the processing performance table are the values in Table 4.

[0105]

[Table 4] Table 5 shows the result of calculating the processing time from the above values.

[0106]

[Table 5] Next, the regions D ₀ to D ₁₅ are divided into four.

The total processing time is 627.92 m
s. The result of dividing this by 4 is 156.98m
s.

[0108] As you added sequentially the processing time in the above table from the region D _0, the addition result from the region D ₀ to D ₃ is 1
44.36 ms, the addition result in the areas D ₀ to D ₄ is
182.55 ms, and the sum of the addition results in the areas D ₀ to D ₃ is closer to 156.98 ms.

The following results are obtained by successively adding in the same manner.

The addition result from the areas D ₄ to D ₆ is 16
8.54 ms, the addition result in the areas D ₇ to D ₁₀ is 1
55.39 ms, the addition result in the areas D ₁₁ to D ₁₅ is
159.82Ms, therefore, region D ₄ to a code data for processing from the region D ₀ to D ₃ first code decoding circuit
The up D ₆ from area D ₇ to the code data that the next code decoding circuit to process up to D ₁₀ from the region D ₁₁ to the code data that the next code decoding circuit to process up to D ₁₅ the next code decoding from It is divided into code data to be processed by the circuit. That is, as shown in Table 6, the storage address information i and the bit position j in the word are stored in the index register B.

[0111]

[Table 6] Next, the four code decoding circuits start the code decoding process according to the information stored in the index register B.

That is, the code decoding circuit A outputs the information i ₀ , j
Code data from ₀ to information i ₄ and j ₄ is decoded and written to the image memory.

The code decoding circuit B decodes the code data from the information i ₄ , j ₄ to the information i ₇ , j ₇ and writes the decoded data in the image memory.

The code decoding circuit C decodes the code data from the information i ₇ , j ₇ to the information i ₁₁ , j ₁₁ and writes it to the image memory.

The code decoding circuit D decodes the code data from the information i ₁₁ , j ₁₁ to the information i ₁₆ , j ₁₆ and writes the decoded data in the image memory.

The following effects can be obtained by performing the above operation.

The area processed by the code decoding circuit A is from D ₀ to
Since a D _3, the processing time is 31.97 + 41.25
+ 32.19 + 38.76 = 144.17 ms The processing area of the code decoding circuit B is D _{4 to} D ₆ , so the processing time is 38.19 + 69.60 + 60.75 =
Processing region of 168.54ms code decoding circuit C, the processing time because it is _{D 7 ~D 10, 50.53 + 38.38} + 32.77 +
33.71 = 155.39 ms Since the area processed by the code decoding circuit D is D _{11 to} D ₁₅ , the processing time is 32.18 + 31.98 + 31.61.
+ 32.37 + 31.68 = 159.82 ms,
The processing time is the longest at 168.
Since this is 54 ms, the processing time of the entire image is 168.
54 ms.

On the other hand, in the case of the conventional method, since the data is divided by the number of lines, the area to be processed by the first code decoding circuit is D _{0 to} D ₃ , and the processing time is 31.97+
41.25 + 32.19 + 38.76 = 144.17m
s Since the area processed by the second code decoding circuit is D _{4 to} D ₇ , the processing time is 38.19 + 69.60 + 60.
75 + 50.53 = 219.07ms processing region of the third code decoding circuit, since a D ₈ to D _11, the processing time is 38.38 + 32.77 + 33.
71 + 32.18 = 137.04 ms Since the area to be processed by the fourth code decoding circuit is D _{12 to} D ₁₅ , the processing time is 31.98 + 31.61 + 32.
37 + 31.68 = 127.64 ms, and the longest processing time is caused by 219.07 of the second code decoding circuit.
ms, the processing time of the entire image is 219.07
ms.

Therefore, compared to the conventional method, 219.07
ms-168.54 ms = 50.53 ms.

[0120]

A first effect is that one page of code data (MH code, MR code) is divided into a plurality of blocks in scan line units, and each code data is divided into a plurality of code decoding circuits equal to the number of divided blocks. In the data decompression processing device that performs the code decoding process in parallel in the above, when the code data of one page is divided, the decoding processing time required by each code decoding circuit can be substantially equalized.

As a result, one code decoding circuit does not require more processing time than another code decoding circuit, and the processing time of one page can be optimized.

The reason is that the number of divided scanning lines of the code data of each block is changed based on the compression ratio and the amount of code data so as to average the decoding processing time of each code decoding circuit. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data decompression processing device as one embodiment of the present invention.

FIG. 2 is a detailed block diagram of an example of a decoding unit in FIG. 1;

FIG. 3 is a detailed block diagram of an example of a dividing unit of FIG.
2).

FIG. 4 is a detailed block diagram of an example of a dividing unit shown in FIG.
2).

FIG. 5 is a diagram illustrating an example of a processing performance table according to the present invention.

FIG. 6 is a flowchart illustrating an example of a process of an EOL detection circuit in FIG. 3;

FIG. 7 is a flowchart illustrating an example of processing of the data address arithmetic circuit of FIG. 3;

FIG. 8 is a flowchart illustrating an example of a process of the index register A of FIG. 3;

FIG. 9 is a flowchart illustrating an example of processing of a compression ratio calculation circuit in FIG. 3;

FIG. 10 is a flowchart illustrating an example of processing of the processing time calculation circuit of FIG. 4;

FIG. 11 is a flowchart (1/2) illustrating an example of processing of the control unit in FIG. 3;

FIG. 12 is a flowchart (2/2) illustrating an example of a process of the control unit in FIG. 3;

FIG. 13 is an image showing a specific example.

FIG. 14 is a block diagram illustrating an example of a general MH code decoder.

FIG. 15 is a block diagram illustrating an example of a general MR code decoder.

FIG. 16 is a block diagram illustrating an example of a conventional MH code decoder.

FIG. 17 is a block diagram of an MH code decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High-order apparatus 2 Code data storage circuit 3 MH code decoding circuit 4 EOL detection circuit 5 Data address operation circuit 6 Index register 7 Control unit 8 Compression ratio operation circuit 9 Compression ratio register 10 Processing performance table storage circuit 11 Processing time operation circuit 12 Processing Time register 13 Division point operation circuit 14 Index register B 15 Code decoding circuit 16 Image memory 17 Index register A 101 Parallel / conversion register 102 Code table storage circuit 103 Video data generation circuit 104 Timing control circuit 1401 Code memory 1402 MH decoding circuit 1403 Pixel Generation circuit 1404 Image memory 1501 Code memory 1502 MR decoding circuit 1503 Change point detection circuit 1504 Pixel generation circuit 1505 Image memory

Claims (4)

(57) [Claims] 1. A plurality of code decoding means for decoding code data from a higher-level device, and a data division means for dividing at least one page of the code data into a plurality of codes and respectively supplying the plurality of code data to the plurality of code decoding circuits. And a data decompression processing device for converting the code data from the higher-level device into image data, wherein the data dividing means includes a total processing amount for decoding the at least one page of the code data. According to the compression ratio and the amount of code data for each of the divided areas in the code data , the processing time of each of the divided areas is divided into allocations that are the sum total of the respective processing amounts. Means,
A data decompression processing device, wherein the image data is obtained by supplying the divided code data to the plurality of code decoding circuits. 2. The at least one page to be decoded
A code data storing circuit for storing the code data, and a image memory for storing image data decoded by the code decoding means, said data dividing means, end-of-line for the synchronization line (hereinafter EOL)
An EOL detection circuit for detecting the presence / absence of an EOL; a data address operation circuit for calculating a storage address of the next bit of the EOL last bit in the code data storage circuit and a bit position in a word from an output result of the EOL detection circuit; a pointer register a for storing the storage address and the word <br/> over de in the bit position of the scan line leading bit predetermined for each scan line, each scan line head stored in the index register a a compression ratio arithmetic circuit for outputting calculates the compression rate of encoded data between the storage locations and said word in a bit position of the bit, and the compression ratio register which stores the result of the compression rate, the code decoding means provided in advance storage performance that stores processing performance table giving the processing performance and the relationship between the compression ratio of the code data to be the process And Buru memory circuit, the value of the compression ratio register and the processing time calculation circuit for the the code data to calculate the processing time when the code decoding circuit has processed output corresponding to the value, the operation result the processing time a processing time register for storing the processing time of each code decoding circuits from the value stored in the processing time register is stored in such as a uniform value the <br/> index register a before the storage address and the word in the bit positions of the scanning lines leading bit
2. The data decompression processing device according to claim 1, further comprising: a division point operation circuit that selects and outputs as many as the number of encoding / decoding circuits; and an index register B that stores the output result. The encoded data wherein to be decoded is the MH code data, the compression ratio arithmetic circuit, storage location and a word in a bit position of a single scan line leading bit stored in the index register A and its storage location and a word in the bit positions of the scan lines first bit following the stored (predetermined storage addresses and word in the bit positions of the scanning lines leading bit after scanning line (value 1 of the index register a) the value 1 and the index register in the following the index register value 2) and the scanning line number defined therebetween in advance of a, and previously given 1 run-length value from the index register a after encoding data decompression scan line Code data between value 2 of A (code data 1)
The compression ratio (compression ratio 1) calculates the and outputting of the processing time calculation circuit, numeral data (the encoded data 1 corresponding value of the compression ratio register and (compression ratio 1) to the value ) Has a function of calculating and outputting a processing time when the code decoding circuit processes the code data. The division point calculation circuit calculates the code data processing time (for one page) from the value stored in the processing time register. the <br/> process calculates the total) of the values stored in the time register, the code division value by the number of decoding circuits (one of the marks for parallel processing of code data processing time for the one page < The average value of the processing time required by the decoding circuit is below average value A)
Look, then scan line stored in the index register A corresponding thereto whenever made to the nearest sequentially added to continue the average value A of the value stored in the processing time register from the head having storage addresses and word in the bit position of the first bit number only the selected function of the output of the code decoding circuit, a data decompression processing apparatus according to claim 2, wherein a. 4. The code data to be decoded is MR code data, and the storage address and the bit position in the word of the first bit of the scan line stored in the index register A are set to a positive integer multiple of a predetermined K parameter. and each scan line, the compression ratio arithmetic circuit, storage location and a word in a bit position of a single scan line leading bit stored in the index register a (hereinafter the value of the index register a 1) to the next positive the index following a predetermined storage location and a word in the bit positions of the scanning lines leading bit after scan line is an integer multiple of storage locations and word in the bit positions of the scanning lines leading bit stored (the K parameter The value 2) of the register A, the predetermined number of scanning lines between them, and one given scanning line The compression ratio of the encoded data between the run-length value after encoding data decompression down the value 2 value 1 and the index register A of the index register A (code data 1) (compression ratio 1) calculates the output The processing time calculation circuit has a function of performing a processing time when the code decoding circuit processes a value (compression rate 1) of the compression rate register and code data (code data 1) corresponding to the value. calculates a and outputting the division point arithmetic circuit is stored the processing time from the value stored in the register 1 page of code data processing time (the <br/> processing time register It calculates the total) value, the code division value by the number of decoding circuits (one before parallel processing of the code data processing time for the one page
Serial asked the following average A) by the average value of the processing time required by the code decoding circuit, then continue sequentially adds the value stored in the processing time register from the head closest to the average value A has a function of selecting a storage address and a word in the bit positions of the scanning lines leading bit stored in the index register a corresponding thereto every time a value for the number of code decoding circuit output, it is characterized in claim Item 3. A data decompression processor according to item 2.