JPH06291991A - Picture communications equipment - Google Patents

Abstract

PURPOSE:To realize a simplified facsimile mail equipment and the reduction in the cost, to facilitate line extension and to reduce the cost thereof. CONSTITUTION:A compander 1 whose speed is ultra-high is employed and shares code conversion processing by the portion of N lines. A unit 32 for line extension is defined as the combination of one compander 1 with the N pieces of communications units 34. Data are sent simultaneously to N pieces of G3 facsimile reception terminal equipments. Reception capability is recognized in the facsimile procedure and the code conversion accordingly is executed by the compander 1 at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention executes a communication procedure for transmitting image code data to a plurality of image receiving terminals simultaneously by using a plurality of lines, and the receiving capability of each image receiving terminal during the communication procedure. The present invention relates to an image communication device which recognizes a code and performs code conversion of image code data according to each receiving ability.

[0002]

2. Description of the Related Art Conventionally, there is a so-called facsimile mail device as an image communication device of this type, which has a structure shown in FIG. In the example shown here, facsimile data (image code data) is received from a G4 facsimile transmission terminal via an ISDN line, and this data is simultaneously sent to a maximum of N G3 facsimile reception terminals using the G3 line (# 1 to #N). For transmission, the ISDN interface circuit 50, the memory 51, the control unit 52, and the G3 line corresponding blocks 53 of the same number as the number of accommodated G3 lines are connected by the system bus 54.

Each G3 line corresponding block 53 is a modem 5
4 and an NCU (network control circuit) 55, a compression / expansion device 56, and an enlargement / reduction device 57, and the compression / expansion device 56, the enlargement / reduction device 57, and the memory 58 are connected by an image bus 59. The control unit 52 performs facsimile procedure control, operation control of each unit, data transfer control, and the like, and includes a microprocessor / DMA controller unit 60, a memory (ROM / RAM) 61, and the like.

Received data from the G4 facsimile transmission terminal is stored in the memory 51 via the ISDN interface circuit 50. After this reception is completed, the control unit 52 makes a call to N G3 facsimile receiving terminals via the G3 line corresponding block 53 corresponding to the G3 lines (# 1 to #N) in a one-to-one correspondence, and during the facsimile procedure. A process of recognizing the receiving ability (encoding system, receiving paper size) of each facsimile receiving terminal and converting the data stored in the memory 51 into data according to the receiving ability of the facsimile receiving terminal (paper size conversion / image (Including conversion) is performed by the corresponding G3 line corresponding block 53, and the converted data is transmitted to the facsimile receiving terminal.

FIG. 37 shows an example of a communication sequence in this case. In this example, the receiving capability of the G3 facsimile receiving terminal connected to each G3 line is recognized from the DIS signal received in phase B of the facsimile procedure, and from that point on, code conversion processing (decoding of received data-enlargement / reduction- Coding)
And ends the code conversion process before entering the phase C of the facsimile procedure. However, the code conversion process may be executed during the phase C.

[0006]

However, according to such a configuration, since it is necessary to provide the same number of expensive G3 line corresponding blocks 53 as the number N of G3 lines that need to be processed at the same time, the number of accommodated lines is large. There is a problem that the device configuration becomes extremely complicated and expensive.

The background of such a problem is that the code conversion speed by the G3 line corresponding block 53 is slow. That is, in the G3 line corresponding block 53, the received data is sent to the compression / expansion device 56 for decoding, the restored image data is temporarily stored in the external memory 58, and the scaling device 57 is added to the image data in this memory 58. Enlargement / reduction (image conversion) is performed, and the image data after enlargement / reduction is sent from the memory 58 to the compression / expansion device 56 for encoding, and the encoded data is returned to the memory 51, whereby code conversion is performed. Further, the image data of the reference line at the time of the encoding or decoding processing by the compression / expansion device 56 is placed in the line memory on the external memory 58. Therefore, the number of accesses to the image bus 59 associated with the code conversion processing is very large, and the access time is long, so that there is a limit to the speeding up of the processing.

The present invention has been made in view of the above problems, and provides a facsimile mail apparatus or the like having a simple structure and a low cost even when the number of lines that must be processed simultaneously is large. It is an object of the present invention to provide a facsimile mail device or the like which can easily cope with expansion and whose cost increase is small.

[0009]

In order to solve the above problems, the present invention uses a plurality of lines and executes a communication procedure for transmitting image code data to a plurality of image receiving terminals at the same time. In an image communication device for executing code conversion processing of image code data according to the receiving capability of each image receiving terminal, a high-speed code conversion device is used, and a line-compatible communication unit for line interface and a code conversion device are provided. , And one code conversion device is commonly used for code conversion processing for a plurality of image receiving terminals in which communication procedures are simultaneously executed.

Further, according to the present invention, in the configuration of such an image communication device, a combination of N line units and one code conversion device is a unit unit for line extension.

According to the present invention, in the configuration of the image communication apparatus, a plurality of processing blocks for code conversion processing of image code data, a plurality of line memories necessary for executing the processing of the plurality of processing blocks, and an external device. An improved code converter comprising a block for interfacing with the bus, an internal bus for transferring data to the line memory and each block, and a block for controlling each block.

[0012]

According to the present invention, the number of code conversion devices can be made smaller than the number of accommodated lines and the same number of communication units as the number of accommodated lines are required in the conventional device. Even in many cases, the overall configuration of the image communication device can be greatly simplified. Further, since the code conversion device has to be considerably more expensive than the communication unit, the cost of the image communication device can be significantly reduced by the reduction of the code conversion device.

Further, it is possible to easily add a line in units of N lines only by adding a unit unit consisting of one code conversion device and N communication units. Further, since there is no particular factor of cost increase other than the cost increase of the added unit unit, the line extension cost can be reduced.

Further, according to the configuration of the improved code conversion apparatus used in the image communication apparatus of the present invention, an external bus is provided for external input of image code data before conversion and external output of image code data after conversion. Code access processing can be executed without accessing the external bus, and the line memory necessary for executing the processing is also internal, so access to it can be performed at high speed. High-speed code conversion processing is possible. As a result, the number of expensive code conversion devices can be significantly reduced by having one code conversion device perform the code conversion processing for many lines.

[0015]

1 is a schematic block diagram of a facsimile mail apparatus according to an embodiment of the present invention. In the example shown here, the facsimile data from the G4 facsimile transmitting terminal is received from the ISDN line, the data is code-converted and simultaneously transmitted to a maximum of N G3 facsimile receiving terminals.

In FIG. 1, reference numeral 1 is an improved compression / decompression device capable of extremely high-speed code conversion processing. As will be described later in detail, the compression / expansion device 1 can be used not only as a code conversion device but also as a compression device, a decompression device or an image conversion device. Reference numeral 16 is a memory for temporarily storing image code data (reception data, transmission data, etc.). Reference numeral 31 is an ISDN interface circuit for interfacing with the ISDN line.

Reference numeral 34 is a line-corresponding communication unit for interfacing with G3 lines (# 1 to #N), and in this example, there are N communication units. Each communication unit 34 comprises a modem 35 and an NCU 35.

Reference numeral 30 denotes a control unit for performing facsimile procedure control, operation control of each unit, data transfer control and the like. The control unit 30 is of a program control type and includes a microprocessor unit (MPU) 13 including a DMA controller, a memory (ROM / RAM) 15 for storing programs and data, and other MPU peripheral circuits (not shown). . Reference numeral 10 is a system bus as a transmission path for data and control information between the respective parts.

The compression / decompression device 1 is responsible for code conversion processing for N lines. A set of one compression / expansion device 1 and N communication units 34 (for N lines) constitutes one unit unit 32 for line extension, and only by adding this unit unit 32, line extension is made in N line units. Can handle.

FIG. 2 shows an example of such an extension. In this example, since two unit units 32 are provided,
2N G3 lines (# 1 to #N, # N + 1 to # 2N) enable simultaneous transmission to 2N G3 facsimile receiving terminals. Other configurations do not require any changes. It should be noted that reducing the number of lines actually connected to one unit unit 32 to less than N may cause another step difference.

The overall operation of this facsimile mail device is as follows. It should be noted that although the description is given here assuming that the configuration is shown in FIG. 1, the same consideration can be applied to the case where the unit unit 32 is added as shown in FIG.

The image code data received from the G4 facsimile transmission terminal via the ISDN line is stored in the memory 16 via the ISDN interface circuit 31. The control of the facsimile procedure at this time is performed by the control unit 30. Since this procedure control is the same as the conventional one, detailed description thereof will be omitted.

After the reception from the G4 facsimile transmission terminal is completed, the control unit 30 starts the transmission processing to the G3 facsimile reception terminal. A schematic flow of the transmission processing for one line is as shown in FIG.

The control unit 30 has N G3 lines via the communication unit 34, which is in one-to-one correspondence with the G3 lines (# 1 to #N).
A call is made to the facsimile receiving terminal (S1), a facsimile procedure with the G3 facsimile receiving terminal for which the call setting has been made is executed (S2), and then the line is opened (S3).

In the facsimile procedure with each G3 facsimile receiving terminal, the control unit 30 recognizes the receiving capability of each G3 facsimile receiving terminal from the DIS signal received in phase B. This recognition content is G3 line (# 1 to #
The DIS reception flag corresponding to the G3 line on the memory 15 is set at the same time, while being stored in the memory 15 in association with N).

The control unit 30 also controls the compression / expansion device 1 to execute a code conversion process on the received image code data in the memory 16 according to the receiving capability of each G3 facsimile receiving terminal. FIG. 3B is a schematic flow of this control. The DIS reception flag on the memory 15 is referred to check whether there is a line for which the flag is set (S10). If the DIS reception flag for one or more lines is set, one of the lines is selected and a code conversion process is executed according to the reception capability of the G3 facsimile receiving terminal of the same line (S11). The converted image code data is managed for each line and stored in the memory 11. When the code conversion processing for one line is completed, the DIS reception flag corresponding to the same line is reset and the code conversion end flag corresponding to the line in the memory 15 is set (S12). The same control is repeated until the code conversion processing for all lines is completed (S13).

Such a code conversion process is completed before entering the phase C of the facsimile procedure (S2). Conversely, even in the worst case, that is, even if the DIS signals are simultaneously received from the G3 facsimile receiving terminals of all the lines, one compression is performed so that the code conversion for all the lines can be completed before entering the phase C. The number N of lines that the processing device 1 is responsible for is determined.

Thereafter, the control unit 30 instructs the respective G3 facsimile receiving terminals in the memory 1 in the phase C thereof.
The corresponding conversion code data in 6 corresponds to the corresponding communication unit 3
4 to send.

Note that the G3 lines (# 1 to #) N have their priorities determined in advance, and in step S11, 2
If the DIS reception flags for more than one line are set, the one line with the highest priority is selected. For example, the priority order of G3 lines (# 1 to #N) is # 1>#2>
# 3>. ． ． >#N-1>#N(# 1 is the highest rank), when the DIS reception flags of all the lines are set, selection is made in order from # 1.

The control using the flag and the priority control described here are merely examples, and it goes without saying that another suitable control method may be adopted.

FIG. 4 shows an example of the communication sequence. Here, it is assumed that the DIS signals are simultaneously received from all the G3 lines (# 1 to #N). In this case, the code conversion process is executed according to the predetermined priority order as described above. Generally, the reception time of the DIS signal varies from line to line.

The procedure time of the G3 facsimile is long, and the DI
It usually takes about 5 seconds from the reception of the S signal until entering the phase C. The speed of the code conversion process (including the paper size conversion) of the compression / expansion device 1 used in the present embodiment is so fast that the code conversion process for 16 lines can be executed in 5 seconds, as will be specifically described later. is there. That is, the maximum N = 16
Is. However, this number assumes the worst case, that is, the case where DIS signals are simultaneously received from all lines. Actually, as described above, the reception time of the DIS signal varies from line to line, so that one compression / expansion device 1 can practically carry out the code conversion processing for more lines.

Although the facsimile data received from the ISDN line is code-converted and transmitted to the G3 facsimile receiving terminal so far, the facsimile data received from the G3 line can be similarly transmitted. .

Overall Structure of Compression / Expansion Device FIG. 5 is a block diagram showing the internal structure of the improved compression / expansion device 1 used in this embodiment. In this example, encoding processing, decoding processing, image conversion (enlargement / reduction for paper size conversion) processing, and combination processing thereof can be performed at high speed, and one of the combination processing is code conversion processing.

Further, in this example, not only the interface with the system bus 10 is possible, but also the interface with the external image bus 11 is possible as shown by a broken line in FIG. And this image bus 1
Control of data input from the image data input unit 21, data output to the image recording unit 22, and the like can be performed via the RAM 28 on the first unit or directly.

In FIG. 5, reference numeral 100 is an image bus control unit which realizes an interface function with the image bus 11. A RAM 200 is used as a line memory and parameter register for internal processing. This R
The AM 200 can also be accessed from the MPU 13 (FIG. 1) of the control unit 30. Reference numeral 300 is an internal bus DMA control unit for controlling DMA transfer to the RAM 200 by the internal data bus (BE data bus) 1700, and 400 is a system bus control unit for interfacing with the MPU (FIG. 1).

Reference numeral 500 is a working register used as various registers, and RAM is actually used. Reference numerals 600 to 800 denote change pixel detection units for detecting change pixel addresses of 16-bit width data, and 900 to 1
100 is a FI for temporarily storing the changed pixel address information
FO buffer, 1200 is an arithmetic and logic unit used in connection with execution of internal processing, 1300 is MH / MR / MM
An R decoder, 1400 is an image conversion unit that performs image conversion (enlargement / reduction) in the main scanning direction of the image, and 1500 is MH / M.
An R / MMR encoder 1600 is a microprogram controller for controlling device operation.

The changed pixel detection units 600 to 800 and F
The IFO buffers 900-1100 can also be included in the corresponding processing blocks 1300-1100. However, in this case, since the changed pixel detection unit 600 and the FIFO buffer 900 are shared by the two processing blocks 1300 and 1500, it is necessary to add the same one.

Reference numeral 1700 denotes a DMA control bus, which comprises a DMA transfer request signal line from each section and a DMA transfer permission signal line to each section. Internal data bus (BE data bus) 18
00 is a 16-bit bus mainly used for transferring image data. 1900 is also a 16-bit internal data bus (BC data bus), which is mainly used for transfer of code data. Although not shown in FIG. 5, a micro program control bus exists between the micro program control unit 1600 and each unit in the apparatus (see FIG. 9 and the like).

Configuration of Encoder FIG. 6 is a block diagram of encoder 1500. In FIG. 6, the changed pixel address control unit 1502 outputs the changed pixel address of the reference line from the FIFO buffer 900 to the FI.
The change pixel addresses of the encoded lines are fetched from the FO buffer 1100, ordered, and input to the encoding mode determination unit 1504.

The coding mode determination unit 1504 determines the coding mode (pass, vertical, horizontal mode) from the input changed pixel address information. The code table search unit 1506 searches the internal code table based on the result of the determination of the coding mode and assigns the code.

The packing processing unit 1508 converts the variable length code output from the code table search unit 1506 into 16-bit / word code data (word packing).
And output to the internal data bus 1900 or 1800 in word units. Reference numeral 1510 is a main sequencer for overall control of the encoder 1500. Internal RAM
A request for DMA transfer with 200 is issued from the main sequencer 1510. 1512 to 1518 are the corresponding processing units 1502 under the control of the main sequencer 1510.
It is a sub sequencer that controls 1508.

The encoder 1500 also has a register 1520 in which one line width (the number of words of image data of one line) is set through an internal data bus (BE data bus) 1800, and the number of codes of one line (the code data of one line). It has a counter 1522 for counting the number of words). The value of this counter 1522 is the internal data bus 180.
Can be output to 0.

Reference numeral 1524 is a comparator provided in connection with MG3 encoding (described later), and compares the value of the register 1520 with the value of the counter 1800. This comparison output is reflected in the status signal of the microprogram control bus 1602. The micro program control unit 1600 can perform control such as designation of a coding mode and activation of the encoder 1500 via the micro program control bus 1602.
Moreover, the state of the encoder 1500 can be acquired.

Decoder Configuration FIG. 7 is a block diagram of the decoder 1300. In FIG. 7, the code shift unit 1302 shifts the code data fetched from the internal data bus (BC data bus) 1900 by the code length for which decoding has been completed, and always provides the code analysis unit 1304 with undecoded code data. Code analysis unit 1304
Searches the internal decoding ROM according to the code data and sends the decoded code to the drawing unit 1308. However, MG3
When an extension code for encoding is detected, the input image data is transferred from the code shift unit 1302 to image data to the drawing unit analysis unit 1308.

Here, the MG3 coding means that one line of image data is coded into facsimile standard code data (MH, MR or MMR code), and the length of one line of code data is the length of the original image data ( Alternatively, when the total length of the image data and the extension code) is exceeded, it is an encoding method in which data obtained by adding the extension code (tens of bits) to the original image data is encoded and output. This MG3 encoding system is based on Japanese Patent Application No.
It is specifically described in the specification and drawings of No. 2669.

The a0 address operation unit 1306 is a FIFO
From the changed pixel address information of the reference line input from the buffer 900 and the decoded code input from the code analysis unit 1304, the start point of the encoded line or the address of the reference changed pixel a0 (see CCITT Recommendation T.4) is calculated. The drawing unit generates image data from the a0 address and white / black information, and outputs the generated image data to the internal data bus (BE data bus) 1800 in units of words (16 bits).

Reference numeral 1310 is a main sequencer for performing overall control of the decoder 1300, and 1312 to 1318 are corresponding functional blocks 1 under the control of the main sequencer 1310.
It is a sub-sequencer that controls 302 to 1318.
The DMA transfer request is issued from the main sequencer 1310.

The decoder 1300 also includes a comparator 1320 for detecting white data (words in which all bits are white bits) from the restored image data, and a continuous EOL number and one line width (code number) as internal data. Bus (BE data bus) 1
It has registers 1322 and 1324 which are set from 800. Based on the comparison result by the comparator 1320, the main sequencer displays a white line (a line in which all bits are white pixels).
The determination result is output to the microprogram control bus 1602 as a status signal.

Further, the main sequencer 1310 checks the decoding error for each line. The check result is output as a status signal. The micro program control unit 1600 has a micro program control bus 1
Through 602, control such as designation and activation of a decoding mode and status monitoring can be performed for the decoder 1300.

Structure of Image Conversion Unit FIG. 8 is a block diagram of the image conversion unit 1400. In FIG. 8, the register 1402 is a FIFO buffer 1000.
The change pixel address (14 bits) to be further input and color information (B / W) are held, and the register 1404 has an enlargement / reduction rate set through an internal data bus (BE data bus) 1800. The multiplier 1406 obtains the changed pixel address after the enlargement / reduction by multiplying the changed pixel address by the enlargement / reduction ratio.
Give to 408.

The drawing unit 1408 generates image data after scaling based on the given change pixel address and the color information given by the register 1402. This image data is output to the internal data bus (BE data bus) 1800 in word units via the register 1410. Reference numeral 1412 is a register in which the one-line width (word number) before conversion is set via the internal data bus 1800, and 1414 is a register for counting the one-line width (word number) after conversion. Reference numeral 1416 is a sequencer that controls each unit in the image conversion unit 1400, and also issues a DMA transfer request.

Arrangement of Arithmetic and Logical Operation Unit, Working Register, etc. FIG. 9 shows an arithmetic and logic operation unit 1200, a working register (RAM) 500 and its peripheral configuration, and a connection configuration with other functional blocks. In FIG. 9, 12
Reference numeral 02 is a 16-bit ALU (including a shifter) that forms the center of the arithmetic logic operation unit 1200.

As is apparent from the figure, it is possible to load the data from the RAM 200 or the like into the ALU 1202, perform the necessary calculation, and write the calculation result in the RAM 200 or the like. Also, a working register (RAM) 500
Operations and checks on the above registers can be performed via the ALU 1202.

In FIG. 9, 1204 and 1206 are ALs.
U1202 input registers, 1207 and 1207 are AL
A selector for selecting an input of U1202, 1210 is a local bus of the arithmetic logic operation unit 1200, and 1211 is an output buffer to the local bus 1210. 1212 and 1213 are a local bus 1210 and an internal data bus (B
E data bus) 1800 is a buffer for data transfer with the 1800.

1214 is a microprogram control bus 1
A decoder that decodes the peripheral address on 602 and outputs a control signal for the ALU 1202 peripheral, 1216 is an R / W control circuit (decoder) that controls the read / write of the working register 500, and 1218 is an address controlled by the microprogram controller 1600. A pointer (counter) 1220 is a selector which selects the value of the address pointer 1218 or the address given from the microprogram control bus 1602 and outputs it to the address bus 1220.

Structures of Micro Program Control Unit and System Bus Control Unit FIG. 10 is an explanatory diagram of structures of the micro program control unit 1600 and the system bus control unit 400.

The compression / decompression device 1 has two processing channels for encoding and decoding, and can perform processing by switching the channel for each line. In order to facilitate such processing execution, the system bus control unit 4
Register set 40 for channel 0 (CH0) at 00
2 and register set 404 for channel 1 (CH1)
There is. The system bus controller 400 includes a system bus timing controller 406, a data buffer 408, and a DMA controller 41 as shown in FIG.
0, clock generator 412, etc. are also included.

The microprogram control unit 1600 has a general structure. In addition to a microROM 1601 storing a microprogram for processing various commands, a program counter 1603 for controlling the execution of the microprogram, a stack 1604, and a stack. Pointer 1605, instruction register 1606, instruction decoder 160
Including 7.

The microprogram control unit 1600 further inputs the macro command set in the command register in the macro ROM 1608 and register sets 402 and 404, which stores the start address of the microprogram for each macro command, to the macro ROM 1608. Selector 1609, micro ROM 1602
A multiplexer 1610 for switching the input of, a multiplexer 1611 for inputting a status signal on the microprogram control bus 1602 and an activation signal from the system bus control unit 400 to the multiplexer 1610 as a control signal.

Method of Using Internal RAM FIG. 11 is an explanatory diagram of a method of using the RAM 200. RA
The linear address space of M200 is channel 0 (C
(H0) parameter register set area 201, channel 1 (CH1) parameter register set area 204, and image memory area 206 are used by being divided. Parameter register set area 20 for each channel
2, 204 are divided into coding command, decoding command, other commands, and parameter register areas 208 to 214 for DMA.

The image memory area 206 is divided into a plurality of line memory areas, and the divided areas are used as various line memories according to processing contents, as described later with reference to FIGS. 13 to 15.

Configuration of Image Bus Control Unit FIG. 12 is a block diagram of the image bus control unit 100. The image bus control unit 100 is a DMA for image data.
It includes a DMA controller 102 for transfer, an address counter 104 and a data buffer 106. Under the control of the image bus control unit 100, the following four types of image data can be DMA-transferred. a) I / O device on the image bus (image input unit 2
1) Transfer from memory (RAM28) to memory (b) I / O from memory (RAM28) on the image bus
Transfer to device (image recording unit 22) c) Transfer from memory (RAM 28) on image bus to compression / expansion device 1 d) Memory on image bus (RA) from compression / expansion device 1
M28) transfer The address counter 104 corresponds to 4 for each DMA transfer.
It is composed of a set of address registers 110 and an incrementer 112. Similarly, the DMA controller 102
Includes four sets of transfer number registers 116 and decrementer 11
6 is included. The DMA controller 102 also has a D
A priority control 118 and a timing control unit 120 for priority control of the MA request are included.

Configuration Related to Line Memory FIGS. 13, 14 and 15 show the internal bus DMA control unit 3.
00, the address register 50 defined on the working register 500 by the microprogram.
2 is a diagram for explaining the breakdown of the line memory 216 defined in the image memory area 206 of the RAM 2 and the RAM 200 and the corresponding relationship between them.

FIG. 13 shows the case of encoded command processing, FIG. 14 shows the case of decoded command processing, and FIG.
Indicates the case of code conversion command processing. In the following description, if necessary to distinguish the address register 502 and the line memory 216 from each other, FIG.
Names INPUT to D1R shown in FIG. 14 or FIG.
To use.

The internal bus DMA control unit 300 has the same number of address counters (A to J) 30 as the line memories 216.
2. DMA for controlling DMA transfer between the RAM 200 and processing blocks such as the encoder 1500 and the decoder 1300
A control unit 304, a selector 306 for selecting the address counter 302, and the like are included.

The area of the line memory 216 on the RAM 200, the address counter 302 and the address register 50.
2 corresponds one-to-one. Since the reference line line memories for the encoding process and the decoding process are for two channels, the external MPU is the encoder 150 in the image processing apparatus 1.
0, it is easy to operate as if there were two decoders 1300.

FIG. 16 shows the structure of the address register 502 defined on the working register 500. IN
Although the PUT address register is shown as an example, the structure of other address registers 502 is similar.

As shown, the lower 11 bits of the address register 502 are the start address of the line memory.
The upper 4 bits (A to E) are flag bits, and their meanings are as follows. A: "1" indicates that the corresponding line memory has valid data. B: "1" indicates that the content of the corresponding line memory is reduction target data. When C: "1", the content of the corresponding line memory is the final line data. D: The meaning differs depending on the register. E: "1" indicates that the content of the corresponding line memory is the enlargement target data.

The microprogram can operate or check these flag bits by using the arithmetic and logic unit 1200.

Operation of Compression / Expansion Apparatus The operation of each processing of the compression / expansion apparatus 1 configured as described above will be described with reference to the system configuration shown in FIG.

The input / output path of the image data of the compression / expansion device 1 is as follows. a) image input unit 21 → compression / expansion device 1 b) image input unit 21 → RAM 28 → compression / expansion device 1 c) compression / expansion device 1 → image recording unit 22 d) compression / expansion device 1 → RAM 28 → image recording unit 22 compression / expansion The image bus control unit 100 of the apparatus 1 supports the DMA transfer of such image data, but the transfer from the image input unit 1 to the RAM 28 is the DMA channel 0, and the transfer from the RAM 28 to the image recording unit 22. Is the DMA channel 1.

Description of Compressing Operation (Outline) The MPU 13 (FIG. 1) of the control unit 30 gives an operation instruction by issuing a macro command to the compressing / expanding apparatus 1. The MPU 13 first sets various registers in the system bus control unit 400. This also includes designation of coded channels CH0 and CH1.

After this register setting is completed, the command register 4 of the designated channel in the system bus control unit 400.
Write the encoded command to 02A or 404B (FIG. 10). This command is decoded by the macro ROM 1608 through the selector 1609, and the start address of the encoding program is output. The encoding program in the micro ROM 1601 is executed from this address. Each processing block in the compression / expansion device 1 has a micro ROM 1
It is controlled by the program written in 601.

As described above, the line memory 216 and the address register 502 defined in the case of the encoded command processing are as shown in FIG. The contents or roles of each line memory are as follows. INPUT: Image data of input line (input buffer) CONVR: Image data of line before main scanning conversion CONVW: Image data of line after main scanning conversion CODING: Image data of encoded line BC1: Code data (output buffer) BC: Code Data (output buffer) C0R: reference line image data for coding channel 0 C1R: reference line image data for coding channel 1 D0R: reference line image data for decoding channel 0 D1R: decoding channel 1 Image data of reference line for use (description along FIG. 19) FIG. 19 shows a simplified example of the flow of the encoding program. The compression operation will be described in detail along this flow.

When the encoded command is issued, the process 20
The parameter required by 01 is set in the parameter register set area 202 (CH0) or 204 (CH) of the RAM 200.
Load the working register 500 from 1). The start address of the area of the line memory 216 having the same name is set in the address register 502.

In steps 2002 and 2003, a DMA transfer request on the image bus 11 (from the image input section 21 to RA
When there is a transfer request to M28 or a transfer request from the RAM 28 to the image recording unit 22, DMA transfer processing is performed.
If there is DMA transfer, the microprogram sets the start address in the start address register 110 and the transfer word number in the transfer count register 114 of the image bus control unit 100, activates them, and sets the activation flag to "
1 "(FIG. 12). After that, the image bus control unit 100 executes the DMA transfer.

In the next step 2004, the compression / decompression device 1 is read from the RAM (line buffer) 28 on the image bus 11.
Is a process of inputting one line of image data to the INPUT line memory on the RAM 200.

(Description with reference to FIG. 20: Input of image data)
The flow of this image data input processing is shown in FIG. Figure 2
At 0, the microprogram has processes 2101, 21.
In 02, it is confirmed that the image bus control unit 100 is not in operation and the activation flag of the image bus control unit 100 is in the reset state. If this is confirmed, in process 2103, the start address of the INPUT line memory is set from the INPUT address register to the address counter A (FIG. 13) in the internal bus DMA control unit 300 via the internal data bus 1800. In step 2104, the address register 104 of the image bus control unit 100 (see FIG.
The address of the external RAM 28 is set to one of 2).

Here, the image input section 21 → RAM 28 →
It is assumed that image data is input through the path of the compression / expansion device 1.

In process 2105, the image bus controller 10 is executed.
The number of words in one line is set in one of the transfer count registers 114 (FIG. 12) in 0. In processing 1706, the image bus control unit 100 is set to the memory read mode, and processing 2
It is activated in 107, and the activation flag is set to "1" in process 2108.

After the start-up, every time the image bus control unit 100 reads 1-word data, the incrementer 112 is
Increments the memory read address, and the decrementer 116 decrements the number of transfer words.

The image data read by the image bus control unit 100 is transferred to the INPUT line memory on the RAM 200 via the internal data bus (BE bus) 1800. This transfer is performed by the image bus control unit 100 in the RAM.
The DMA control unit 304 in the internal bus DMA control unit 300 issues a DMA transfer request to the internal data bus 18
This is executed by giving the control right of 00 to the image bus control unit 100. When the image data of 1 word is transferred to the INPUT line memory, the address counter A in the internal bus DMA control unit 300 is also incremented.

The above operation is repeated until the number of transfer words set in the image bus control unit 100 becomes zero. During the transfer, the process 2101 immediately returns.

When the transfer of one line is completed, INPUT
Image data for one line is stored in the line memory. Process 2
The processing after 109 is processing after one line is input.

In process 2109, the activation flag set in process 2108 is reset. In process 2110, the start address of the external RAM 28 containing the next line is calculated. In process 2111, the number of lines to be continuously processed by the encoded command is decremented, and the remaining number of processed lines is calculated. In process 2112, it is determined whether the line input immediately before the result of process 2111 is the final line. In the case of the final line, the C flag of the INPUT address register is set to "1" in process 2113. In processing 2114, the A flag of the INPUT address register is set to "
Set to 1 ". The state of these A and C flags is
As will be described later, in the process of exchanging the contents of the address register, it is delivered to the subsequent processing.

FIG. 17 shows a state when one line of data is stored in the INPUT line memory.
Here, it is assumed that the INPUT line memory is the memory area 216A starting from the address XXX. When the image data is completely input, the A flag of the INPUT address register is set to "1", and it can be seen that there is valid data in the INPUT line memory. Since the CONVR address register indicates YYY and its A flag is "0", it can be seen that the CONVR line memory is vacant in the memory area 216B starting from the address YYY. (Continuing the description along with FIG. 19) Returning to the flow of FIG.
The microprogram checks A = 1 of the INPUT address register in process 2005, and if A = 1, checks A = 0 of the CONVR address register in process 2006.

INPUT A = 1 and CONVR A =
If it is 0, that is, if there is valid data in the INPUT line memory and the CONTVR line memory is empty, in step 2007, the INPUT address register and CO
Swap the contents of the NVR address register.

(Data Transfer Between Line Memories) The data transfer between the line memories will be described with reference to FIGS. 17 and 18. FIG. 17 shows a state before execution of the process 2007. FIG. 18 shows the address registers INPUT and CO.
This is the state after the contents of the NVR have been exchanged. In FIG. 18, the CONVR address register is the memory area 216A.
Of the memory area 216B, and the INPUT address register points to the start address YYY of the memory area 216B. In effect, the data input to the INPUT line memory is passed to the CONVR line memory,
This means that an empty area has been passed to the T-line memory.

As described above, since the method does not involve the actual movement of data on the RAM 200, the data transfer between the line memories is instantaneously performed.

(Continuing from the description according to FIG. 19) Next processing 2
Reference numeral 008 denotes an enlargement / reduction (image conversion) process in the main scanning direction. In this process, the data in the CONVR line memory is converted and written in the CONVW line memory.

In this process 2008, the microprogram makes the following settings before activating the image converter 1400. The address counters CONVR and CONV are provided to the address counters B and C in the internal bus DMA control unit 300.
Load the start address set in W (Fig. 1
3). RAM by the MPU 13 (FIG. 1) of the control unit 30
The enlargement / reduction ratio set in the parameter register 208 in the image conversion unit 200 is stored in the register 1404 in the image conversion unit 1400.
(Fig. 8). The number of words of the CONVR line is set in the register 1412. After such initial settings, the microprogram activates the image conversion unit 1400,
The process 2008 is exited.

The image data in the CONVR line memory is DMA-transferred to the changed pixel detection unit 700 and converted into changed pixel data, and its address information is input to the register 1402. Registers 1402, 1 by multiplier 1406
The contents of 404 are multiplied to obtain the changed pixel address data after conversion. Based on this data and the color information in the register 1402, the drawing unit 1408 creates converted image data. The obtained converted image data is DMA-transferred to the CONVW line memory. In this case, the method of the DMA transfer from the CONVR line memory and the DMA transfer to the CONVW line memory is performed by the image bus control unit 100.
Is the same as the DMA transfer from the RAM to the RAM 200. When the conversion of one line is completed, the A flag of the CONVW address register is set to "1".

When reduction in the sub-scanning direction is required, determination is made as to whether or not the line data on the CONVW line memory is a thinning line and flag control is performed following the one-line main scanning conversion. The contents of this processing will be described later. When it is determined that the line is the thinning line, the A flag of the CONVW address register is not set.

In processes 2009 and 2010, it is determined whether or not there is valid data after conversion and whether or not the coding CODING line memory is empty. CONVW address register A = 1 and CODING address register A =
When it is 0, the address register C is processed in the next processing 2011.
By exchanging the contents of ONVW and CODING and loading the head address after the exchange into the corresponding address counter 302, the line memories CONVW and CODIN are exchanged.
Transfer data between G. In the case of thinning lines, this exchange is not done.

Process 2012 is a code process of data in the CODING line memory. If the encoder 1500 is not in operation, the microprogram sets the encoding mode (MH, MR, MMR, MG3) for the encoder 1500, sets one line width in the register 1520, and activates the encoder. However, in the case of the thinning line, since the A flag of the CONVW address register is "0", the encoder 1
Do not start 500.

The activated encoder 1500 is
The image data in the G line memory is encoded by referring to either data in the encoded reference line memories C0R (CH0) and C1R (CH1), and the result is written in the encoded data memory BC1. Data reading from the CODING line memory and data writing to the BC1 line memory are performed through the internal bus DMA control unit 300. The operation of the internal bus DMA control unit 300 is the same as the case of data transfer from the image bus control unit 100 to the RAM 200.

The changed pixel address of the encoded line is detected by the changed pixel detecting section 800, and the changed pixel address of the reference line is detected by the changed pixel detecting section 600.

When the encoding of one line is completed, the A flag of the BC1 address register is set to "1". C
ODING address register and address counter C0R
The reference line is updated by exchanging the contents of (CH0) or C1R (CH1).

The microprogram executes processing 2013, 2
When the end of encoding and the vacancy of the BC line memory are confirmed in 014, the address registers BC1, BC are processed in processing 2015.
By exchanging the contents of the line memory BC1,
Transfers BC data.

In process 2016, the code data is output from the BC line memory to the system bus 10 by DMA transfer. At this time, it is necessary to know the code amount to be output, but at the end of encoding, the counter 152 in the encoder 1500
The code amount can be known by referring to the contents of 2 (FIG. 6).

In processing 2017, it is judged whether or not the encoding of the set number of lines is completed, and if it is not completed, the processing 2
Return to 002. If the encoding is completed, the process 2018
Then, the processing of the encoded command is ended after waiting for all the code data to go out.

At the end of the encoded command, the C flag is "
Judgment is made based on whether or not the encoding of the final line set to 1 "has been completed. The state of the C flag is propagated through the address register as follows: INPUT, C = 1 → CONVR, C = 1 C = 1 of CONVR Then, after the image conversion is completed, CONV
W, C = 1 → CODING, C = 1 (Summary of compression operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, the image data input process (process 2004), the image conversion process (process 2008), the encoding process (process 2012), and the code data output process (process 2016) are performed in parallel. Operate. Further, in parallel with this, DMA transfer (process 2002, process 2003) on the image bus side can be performed.

Therefore, the compression processing time of the main compression / expansion device 1 can be approximately expressed by the following equation. Processing time = max {image input time, image conversion time, coding time, code output time} FIG. 21 shows how to use the line memory in the coding command processing. As can be seen from this figure, the line memories INPUT, CONVR are used for toggle, the line memories CONVW, CODING, C0R / C1R are used for circulation, and the line memories BC1, BC are used for toggle.

If the main scanning conversion is not performed, FIG.
As noted at 1, the data in the CONVW line memory is passed directly to the CODING line memory.

Although the image data is input from the image bus 11 side in the above description, the compression / expansion device 1 can also input the data to be encoded from the system bus 10 as shown in FIG. Similarly, in the above description, the encoded data is transmitted via the RAM 200 to the system bus 10
However, it is also possible to output directly to the system bus 10 from the encoder 1500.

Description of Decompression Operation (Outline) The MPU 13 of the control unit 30 first sets various registers relating to the decoding command processing. This includes designation of decoding channels 0 and 1 (CH0, CH1).

After this register setting is completed, the MPU 13 sets the command register 402 in the system bus control unit 400.
Write the decryption command in A or 404A. This command is decoded by the macro ROM 1608 and the start address of the decoding program is output. The decoding program in the micro ROM 1601 is executed from this address.

As already described, the line memory 216 and the address register 502 defined in the case of the encoded command processing are as shown in FIG. The contents or roles of each line memory are as follows. DECODE: Image data of restored line D0R: Image data of reference line for decoding channel 0 D1R: Image data of reference line for decoding channel 1 CONVR: Image data of line before conversion CONVW: Image data of line after conversion OUT2: Output Line buffer OUT1: Output line buffer OUT: Output line buffer Code data is line memory D0R (CH0) or D1
The data restored by decoding with reference to the data of R (CH1) is expanded in the DECODE line memory. When the decoding of one line is completed, the contents of the DECODE line memory are transferred to the line memory D0R or D1R and are referred to when decoding the next line. At the same time, the contents of the line memory D0R or D1R are stored in the line memory CONV.
It is passed to R for image conversion. Image conversion is CO
This is performed for the data in the NVR line memory, and the converted image data is written in the CONVW line memory.

The converted data in the CONVW line memory immediately reaches OU if the OUT2 line memory is empty.
Passed to T2 line memory. The data in the OUT2 line memory is immediately transferred to the OUT1 line memory if the OUT1 line memory is empty. If the OUT line memory is empty, the data in the OUT1 line memory is
Immediately, this data is output to the OUT line memory and output to the outside.

In this way, CONVW, OUT2, OU
Each T1 and OUT line memory is a line-by-line FIFO
Acts as a buffer.

(Description along FIG. 22) FIG. 22 shows an example of the flow of the decoding program. Following this flow,
The decryption command processing will be described.

In process 3001, parameters necessary for the decryption command process are set as parameter registers set 202 (CH0) or 204 in the RAM 200 as initial setting.
The working register 500 is loaded from (CH1).

One line is decoded in the process 3002, which will be described later in detail with reference to FIG.

In process 3003, the A flag of the DECODE address register is checked to determine whether the restoration of one line is completed. In process 3004, it is determined whether the CONVR line memory is empty. DECODE
If A = 1 of the E address register and A = 0 of the CONVR address register, the address register CONVR and the address register D0R or D1R are processed in processing 3005.
Of the address register D0R or D1R and the address register DECODE in step 3006.
The contents of are exchanged and data is exchanged between line memories.

As a result, the line memory D0R or D
The restored data is passed to 1R, and the next line is ready to be restored. The data that has been used as a reference line is passed to the CONVR line memory, and the memory area of the data that has been converted is passed to the DECODE line memory.
Now you are ready to restore the next line and the next image conversion.

In steps 3007 and 3008, the presence or absence of data to be converted and the availability of the CONVW line memory are checked.

In process 3009, the image conversion unit 1400 performs image conversion in the main scanning direction. The content of this process is the same as the process 2008 of FIG. When sub-scanning direction conversion is necessary, thinning line determination and flag control are performed subsequent to main scanning conversion, the details of which will be described later.

Process 3010 is control of the line buffer. The details will be described later with reference to FIG.

It is checked in step 3011 whether there is data to be output. In process 3012, the data in the OUT line memory is externally output. In processing 3013.3014, when there is a request for DMA transfer on the image bus side,
The transfer process is performed. This is the process 2 shown in FIG.
The same as 002 and 2003.

In processing 3015, it is judged whether or not the decryption command has ended, and if the end condition is not satisfied, processing 3002
Return to. When the end condition is satisfied, in process 3016,
The data transferred to the CONVR line memory is returned to the line memory D0R or D1R in preparation for the next decoding command.

(Description with reference to FIG. 23: 1-line encoding)
FIG. 23 is a flow of the 1-line decoding process 3002 of FIG. In process 3101, the status signal indicating that the decoder 1300 is in operation is checked. If it is not in operation, in step 3102, the decoder 13
Check the start flag of 00. If it is confirmed that the startup flag is set (started), the process proceeds to step 3103, and if the startup flag is reset, the process proceeds to step 3115. When the decoder 1300 is in operation, it immediately returns.

The processing flow when the decoder 1300 is not in operation is as follows. In process 3115, the decoder 1
The internal bus DMA control unit 3 prepares to start the 300.
Address counter A and address counter I or J in 00, address register DECODE and address register D0R or D1R on the working register 500.
Load the contents of each.

Thereafter, each time one word is accessed in response to the DMA transfer request from the decoder 1300, these address counters are automatically incremented to specify the write address of the restored data and the read address of the reference line data.

In process 3116, the number of words in one line is set in the register 1324 of the decoder 1300 and the internal register (not shown) of the reference line change pixel detection unit 600. After such preparation, the decoder 1300 is started in the process 3117, the start flag of the decoder 1300 is set to "1" in the process 3118, and the process returns. The above is the line head processing.

After the process 3103, the decoder 1300 is set to 1
The data for the line is decrypted and the restored data is DECODE
It is a processing part after being obtained in the line memory.

In processing 3103, the activation flag set in processing 3118 is reset. In the process 3104, the status signal of the decoder 1300 indicating whether there is a decoding error is checked.

If there is a decoding error, a decoding error process is performed in process 3119. For example, a process of replacing the line having an error with the immediately preceding line or the white line is performed.
If there is no decoding error, the error-free data has been restored in the DECODE line memory.
Set the flag to "1".

In process 3106, the status signal of the decoder 1300 indicating that the restored line is a white line (all pixels are white) is checked. Each time the decoder 1300 restores one word, the comparator 1320 (FIG. 7) checks whether or not the data is white data, and when one line has been decoded, it is determined from the status signal that the line is a white line by a microprogram. You can check on the side. If it is a white line, process 31
At 07, increment a counter for counting the continuous white lines at the top of one page or a counter for counting the continuous white lines at the bottom of the page (both counters are prepared on working register 500) To do.

In step 3108, the status signal of the decoder 1300 indicating whether the RTC code is detected is checked. In process 3109, it is determined whether to output the restored data to the outside. This judgment is made by register set 402 (CH0) or 40 in the system bus control unit 400.
4 (CH1) by referring to a specific register. The bit contents of this register are set by the MPU of the processor block 13.

If the line is not output, the process 31
At 10, set the B flag of the DECODE address register to "
1 ". Lines with the B flag set are
When outputting data, the data is ignored and not output to the outside. By such control, it is possible to perform control such that the MPU side cuts the white line at the upper end or the lower end of the page.

In process 3112, the number of lines to be continuously processed set by the MPU is decremented to obtain the number of remaining lines. Then, in processing 3113, the number of remaining lines is checked. If this is 0, processing 3114 determines DECOD.
Set the C flag indicating the last line of the E address register to "
Set to 1 ". If the number of remaining lines is not 0, return immediately.

In process 3120, a counter for the number of restored lines (prepared on the working register 500) is incremented. With this counter value, the number of lines on one page can be obtained. The number of lines is stored in the decoding command parameter register area 210 for the corresponding channel of the RAM 200 by the microprogram when the processing of one page is completed. This area can be directly accessed from the MPU.

(Description According to FIG. 24: Line Buffer Control) FIG. 24 is a flow of the process 3010 (line buffer control) of FIG. In processing 3201 and 3202, CO
After confirming that A = 1 of the NVW address register and A = 0 of the OUT2 address register, the contents of the address registers CONVW and OUT2 are exchanged in process 3203.

As a result, the data in the CONVW line memory enters the OUT2 line memory, and the empty area extends to the CONVW line memory. The flag states of the address register are A = 1 for OUT2 and A = 0 for CONVW.

Data exchange between the line memories OUT2 and OUT1 is performed in processes 3208, 3204 and 3205, and data exchange between the line memories OUT1 and OUT is performed in processes 3209, 3206 and 3207. Process 32
At 07, the A flag of the OUT address register is set to "1". With the above processing, CONVW, OUT2, OU
Each T1 and OUT line memory is a line unit FIFO
It will be used as a buffer.

(Description with reference to FIG. 25: image data output)
FIG. 25 is a flow of the image data output process 3012 of FIG. In process 3301, the image bus control unit 3301
Check whether or not is in operation, and if it is in operation, return. If it is not operating, it is checked in process 3302 whether the activation flag of the image bus control unit 100 is set. If the activation flag is "1", it means that the image bus control unit 100 has been activated and is not in operation. Therefore, the process proceeds to the process 3311 and subsequent line end processes.

If it is not activated, the line head process is started. In processing 2303, the B flag of the OUT address register is checked to determine whether to output the data of the OUT line memory.

If the B flag is not "1", the data is the data to be output, and therefore the output for the DMA transfer is prepared. First, in process 3304, the start address is loaded from the OUT address register into the address counter 302 corresponding to the OUT line memory in the internal bus DMA control unit 300. In process 3305, the address of the external RAM 28 is set in one of the address registers 104 in the image bus control unit 100. In process 3306, the number of words in the output line is set in one of the transfer word number registers 114 in the image bus controller 100. In process 3307, the operation mode of the image bus control unit 100 is set. Here, the memory write mode is set. Then, in process 3308, the image bus control unit 100 is activated. In process 3309, the start flag in the memory write mode of the image bus control unit 100 is set to "1", and the process returns.

If the B flag is "1" in processing 3303, data output is not performed, and the contents of the OUT line memory are ignored by resetting the A flag of the OUT address register to "0" in processing 3310. . This process achieves line thinning.

The process 3311 and subsequent processes are line end processes. In process 3311, the activation flag of the image bus control unit 100 set in process 3309 is reset. In process 3312, the E flag of the OUT address register is checked to determine whether the output line is the enlargement target line in the sub-scanning direction.

If it is not the enlargement target (E = 0), the second output of the data in the OUT line memory is unnecessary.
In processing 3313, the A flag of the OUT address register is set to "
It is reset to 0 "and the OUT line memory is released. If the line is an enlargement target line (E = 1), OU is reached in processing 2314.
Reset the E flag in the T address register. That A
Since the flag is "1", this data is output again, and as a result, enlargement in the sub-scanning direction (line interpolation) is achieved. In process 3315, the address of the external RAM 28 is updated to output the next line, and the process returns.

The end of the decoding command is judged by whether or not the data in which the C flag is set to "1" is output. The C flag (final line flag) is propagated as follows by exchanging the address register. DECODE, C = 1 → CONVR, C = 1 If CONVR, C = 1, after image conversion is completed CONV
W, C = 1 → OUT, C = 1 (Summary of expansion operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, a decoding process (process 3002) and an image conversion process (process 300) are performed.
9), the image data output process (process 3012) operates in parallel. Further, DMA transfer processing on the image bus side (processing 3
013, process 3014) can also operate in parallel with these.

Therefore, the expansion processing time of the compression / expansion device 1 can be approximately expressed by the following equation. Processing time = max {decoding time, image conversion time, image data output time} FIG. 26 shows how to use the line memory in the decoding command processing. As you can see from this figure, DECOD
Each line memory of E, D0R / D1R, and CONVR is cyclically used, and CONVW, OUT2, OUT1, O
Each line memory of the UT is also used cyclically.

Description of Code Conversion Operation Next, the code conversion operation will be described. This code conversion is to input a certain code data and convert it to another code data. For example, conversion from MR code to MMR code.

In the case of the code conversion operation, the code data to be converted is input from the system bus 10, decoded by the decoder 1300, and the restored data is written in the DECODE line memory. By the decoding operation already described, C
The data in the ONVR line memory is converted into an image. Up to this point, the decompression operation is exactly the same.

After that, the data in the CONVW line memory is the object of encoding. After that, the compression operation is exactly the same.

The above decoding, image conversion, and coding processes can be repeated in order for each line to convert the code data for one page into another code.

In the case of this code conversion processing, as already described, the address register 502 and line memory 216 shown in FIG. 15 are defined. FIG. 28 is an explanatory diagram of how to use the line memory.

FIG. 27 is a flow of the code conversion program. Since the processes having the same numbers as those in the flow of FIG. 19 or FIG. 22 have the same contents, the description thereof will be omitted.

From the flow of FIG. 27, the following can be easily understood. a) Decoding process, image conversion process, encoding process, and two DMA transfer processes on the image bus side operate in parallel. b) Even if a decoding error occurs, since the decoding error check and the decoding error processing (processing 3119 in FIG. 23) are performed in the 1-line decoding processing (processing 3002), the image data after the error processing is coded. The conversion is performed. Therefore, the coded data after conversion does not include a decoding error.

In the code conversion operation or decompression operation, the number of lines in one page and the number of continuous white lines at the upper and lower edges of the page are obtained in the decoding process (process 3002) (processes 3120 and 3107 in FIG. 23). When the operation is completed, it is stored in the decryption command parameter register area 210 on the RAM 200. The MPU 13 can read out these parameters and use them for determining the enlargement / reduction ratio and the cut lines at the upper and lower ends of the page.

Description of image conversion (reduction) in the sub-scanning direction Reduction in the sub-scanning direction is realized by thinning out one line for every constant number of lines, and enlargement in the sub-scanning direction is copying one line for every certain number of lines ( It is realized by performing (interpolation). Here, the reduction operation in the sub-scanning direction will be described in detail centering on a method of determining thinning lines.

FIG. 29 is a conceptual diagram of the processing of the sub-scanning direction conversion operation. Related parameters (working register 5
00 are provided in the registers 551 to 557 prepared as follows) (however, for channel 0). C0-VCONV (sub-scan conversion ratio): register 551 C0-ZLINE (constant line number, which will be described later): register 552 C0-VCWRK (work register): register 553 C0-ZLWRK (work register): register 554 register X ( Register indicating address of RAM 200): Register 555 Non-white word counter: Register 556 N (constant): Register 557 (Description of algorithm that does not give priority to white line) CONV
Every time one line of valid data is obtained in the W line memory, C0-VCONV is integrated by the 16-bit ALU 1202. This integrated value is C0-VCWRK. The line in which the carry occurs when the ALU 1202 overflows when integrated is the target of thinning.

The carry of the 16-bit ALU 1202 comes out once every 65536 / (C0-VCONV) lines. If M = 65536 / (C0-VCONV), one line is thinned out to M lines, and the reduction ratio R is R = (M-1) / M = 1- (1 / M).

From this relationship, the MPU 13 determines C0-VCONV from the reduction ratio R and sets it to the compression / expansion device 1.

FIG. 30 (a) is an explanatory view of the integration process of CO-VCONV. It is a line of the image and the integrated value CO of each line.
-VCWRK is shown side by side. In the example shown here, since carry occurs on the fifth line, this line is set as a thinning line.

Such an algorithm is conventionally known. It should be noted that the determination of the copy line in the case of enlargement in the sub-scanning direction can be performed by the same algorithm, and the integration process is shown in FIG. 30 (b). In this example, since carry occurs on the 5th line, the 5th line is the enlargement target line, and this is encoded twice.

In the compression / expansion device 1, both the above algorithm and the improved algorithm described below can be selected.

(Explanation of Improved Algorithm) FIG. 31
FIG. 6 is an explanatory diagram of this improved sub-scanning direction reduction algorithm. The arrow indicates the position of the carry line. According to the above-mentioned conventional algorithm, the lines with carry are unconditionally thinned, so that there is a drawback that thin ruled lines are lost and the image quality is deteriorated.

This improved algorithm prevents such image quality deterioration by preferentially thinning out white lines. That is, C0-ZLINE is set to be smaller than the line thinning interval, a white line is searched in the range of C0-ZLINE from the line where the carry occurs, and the white line is thinned. CO-ZILI
If there is no white line in the NE range, the last (C0-ZLINE) line in this range is thinned out.

The white line referred to here is the number of non-white words ≦
A line that satisfies N. N is a value set by the MPU. If N = 0, all words are searched for a white word line as a white line.

(Explanation with reference to FIGS. 32 and 33) FIG. 32 is a flow of processing for determining thinning lines and setting flags. This processing is realized by a micro program written in the micro ROM 1601.
It is executed every time one line of data is generated in the VW line memory (immediately after the main scanning conversion process is completed in the process 3009 of FIG. 22 or 27 or the process 2008 of FIG. 19). According to the flag information set here, lines are actually thinned in the subsequent restored data output process (process 3012 in FIG. 22 in the case of a decoding operation).

In FIG. 32, in processing 4001, C0-Z
Decrement the LINE. Process 4002, 4003
To add to C0-VCONV and C0-VCWRK (update integrated value). In process 4004, it is checked whether a carry of the ALU 1202 (included in the status signal of the ALU 1202) has occurred.

Processing 4005A when carry is out
Then, when the carry is not output, the process is 4005B, and M
It is checked whether the PU sets the specific registers (402, 404) in the system bus control unit 400 to the white line priority thinning (the above-mentioned improved algorithm). When it is determined in the process 4005B that the white line priority thinning is not performed (when the above-described conventional algorithm is selected), the process returns, and when it is determined that the white line priority thinning is performed, the process proceeds to a process 4007.

If it is determined in the process 4005A that the white line is to be thinned out, the CO-ZLWRK is processed in the process 4006.
Is set to the initial value C0-ZLINE, and the processing 4007 is performed. If it is determined in the processing 4005 that the white line is prioritized thinning, the processing immediately proceeds to the processing 4007.

This processing 4007 is to check the data in the CONVW line memory and determine whether or not the condition for the thinning line is satisfied, the content of which is shown in FIG. This determination result is used as the next processing 4008.
Check with. If it is determined to be a white line, process 4
At 010, it is judged whether or not the range of C0-ZLINE has been checked, and if not checked, the process returns.

If it is determined that the inspection within the range of CO-ZLINE has been completed, or if it is determined in step 4008 that the line is a white line, the B flag of the CONVW address register is set to "1" in step 4009 and the process returns. Now, in the subsequent process (process 3013 in FIG. 22), CONVW
The data in the line memory is treated as a thinned (reduction target) line.

FIG. 33 is a flow chart of the process 4007. In process 4101, the start address of the CONVW line memory is set in the register X. In process 4102, ALU1
The content of the address pointed to by register X is loaded into the accumulator (ACCA) of 202. This is a process of reading one word (16 bits) of data from the RAM 200 through the internal data bus 1800 (FIG. 5).

In processing 4103, it is determined whether the data is white data in which all 16 bits are white pixels or non-white data including black pixels even with 1 bit. If it is non-white data, the non-white word counter (register 55
6) is incremented. In process 4106, it is determined whether or not the check for one line is completed. If it is not completed, the register X is incremented in process 4105 and the process 41
The process is repeated from 02.

When the check of one line is completed, the process 4
At 107, it is determined whether the count value of the non-white word counter is less than or equal to the set value N. If N or less, a flag indicating a white line is set in process 4108. Process 4
In 008 (FIG. 32), this flag is checked.

As is clear from the above description,
The compression / expansion device 1 can also perform only image conversion. It is also possible to perform the decompression operation without outputting the data at all, and to check the code data for an error or to detect the number of lines and the number of white lines at the upper and lower ends of the page at high speed.

The measured values of the processing time of the compression / expansion device 1 are shown in FIGS. 34 and 35. FIG. 34 shows a compression operation (encoding process +
FIG. 35 shows the processing time for one line of the decompression operation (decoding processing + image conversion processing).

The measurement condition is that the conversion rate of the image conversion processing is 10
It is set to 0% and the load inside the compression / expansion device is set to the maximum, and the length of 1 line is set to 204 of B4 size.
8 pixels, machine cycle 100nsec (10M
Hz). The measured values are MH, MR, MMR of the standard facsimile encoding method, the MG3 encoding method in which the encoded data amount does not exceed the image data amount, and the reference line is all white and the encoding line is 1-bit alternating image data. H
It is shown for (W1, B1).

The numbers on the horizontal axis mean the number of changed pixels in one word (16 bits). In the case of an average document image, the number of changed pixels in one word is in the range of 0-4. Therefore, for an average document image, one line is 100μ.
It can be compressed or expanded in about sec.

The processing time of the code conversion processing is not more than the total time of the compression processing time and the expansion processing time. That is, even if the time for the size conversion (image conversion) from the B4 size to the B4 size is included, the code conversion process of the average document image is 200 μm.
It can be executed at high speed in a time of about sec / line.

Practically, since the image conversion from B4 size to A4 size is usually performed, the code conversion processing time is much faster. In addition, here 10MHz
It was measured as (machine cycle 100 nsec),
Since it has been confirmed that the compression / expansion device 1 can be easily operated at 16 MHz, the code conversion processing time can be shortened to about 100 μsec / line, and if one page is 2400 lines, 0.2 to 0. It is possible to convert the code of one page in 3 seconds. Therefore, as described above, one compression / expansion processing device 1 can handle the encoding processing for 16 lines.

Although the embodiment of the facsimile mail apparatus has been described so far, the present invention can be applied to an image communication apparatus which performs similar image code data transmission processing by a specific communication procedure other than the facsimile procedure.

[0179]

As is apparent from the above description, the present invention has the following effects.

1) A high-speed code conversion device is used, and a line-corresponding communication unit for a line interface and a code conversion device are made independent, and one code conversion device is used for a plurality of lines in which a communication procedure is simultaneously executed. Since it is commonly used for the code conversion processing for the image receiving terminal, it is possible to reduce the number of expensive code conversion apparatuses, simplify the configuration of the image communication apparatus, and achieve cost reduction.

2) Only by adding a unit unit in which N line units and one code conversion device are combined,
It is possible to easily add a line in units of N lines at a minimum cost.

3) A plurality of processing blocks for code conversion processing of image code data, a plurality of line memories necessary for executing the processing of the plurality of processing blocks, and a block for interfacing with the external bus. By using an improved transcoding device comprising an internal bus for data transfer to the line memory and each block, and a block controlling each block,
Since a single code conversion device is responsible for code conversion processing for a large number of lines, and the cost of the code conversion device, which makes up a considerable proportion of the cost of the image communication device, can be significantly reduced, an image with a large number of accommodated lines can be obtained. The communication device can also be provided at low cost.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a facsimile mail apparatus according to the present invention.

FIG. 2 is a schematic block diagram showing a line extension example of the facsimile mail device of the present invention.

FIG. 3A is a schematic flowchart showing processing for one line. FIG. 3B is a schematic flowchart showing control of code conversion.

FIG. 4 is a diagram showing an example of a communication sequence of the facsimile mail apparatus of the present invention.

FIG. 5 is a block diagram of a compression / decompression device.

FIG. 6 is a block diagram of an encoder in the compression / decompression device.

FIG. 7 is a block diagram of a decoder in the compression / decompression device.

FIG. 8 is a block diagram of an image conversion unit in the compression / decompression device.

FIG. 9 is a block diagram of an arithmetic logic operation unit in the compression / expansion device and its peripherals.

FIG. 10 is a block diagram of a micro program control unit and a system bus control unit in the compression / decompression device.

FIG. 11 is an explanatory diagram of how to use the internal RAM of the compression / decompression device.

FIG. 12 is a block diagram of an image bus control unit in the compression / decompression device.

FIG. 13 is a line memory for processing encoded commands,
Illustration of address counter and address register

FIG. 14 is a line memory for decoding command processing,
Illustration of address counter and address register

FIG. 15 is an explanatory diagram of a line memory, an address counter, and an address register for code conversion processing.

FIG. 16 is a block diagram of an address register

FIG. 17 is a diagram showing a state before data is transferred between line memories.

FIG. 18 is a diagram showing a state after data is transferred between line memories by exchanging contents of address registers.

FIG. 19 is a flowchart of compression operation.

FIG. 20 is a flowchart for inputting image data.

FIG. 21 is a diagram showing how the line memory is used and data flow during compression operation.

FIG. 22 is a flowchart of a decompression operation.

FIG. 23 is a flowchart of 1-line decoding.

FIG. 24 is a flowchart of line buffer control.

FIG. 25 is a flowchart of image output.

FIG. 26 is a diagram showing how the line memory is used and the data flow during a decompression operation.

FIG. 27 is a flowchart of a code conversion operation.

FIG. 28 is a diagram showing usage and data flow of a line memory during code conversion operation.

FIG. 29 is an explanatory diagram of parameters for image conversion in the sub-scanning direction.

30A is an explanatory diagram of a thinning line determination method for reducing in the sub-scanning direction, and FIG. 30B is an explanatory diagram of a copy line determination method for expanding in the sub-scanning direction.

FIG. 31 is an explanatory diagram of a thinning line determination method using an improved algorithm.

FIG. 32 is a flowchart of sub-scanning reduction.

FIG. 33 is a flowchart for checking data in the CONVW line memory.

FIG. 34 is a relationship diagram showing the relationship between each encoding format of the compression / expansion device and one-line processing time during compression operation.

FIG. 35 is a relationship diagram showing the relationship between each encoding format of the compression / expansion device and the one-line processing time during expansion operation.

FIG. 36 is a schematic block diagram of a conventional facsimile mail device.

FIG. 37 is a diagram showing an example of a communication sequence of a conventional facsimile mail device.

[Explanation of symbols]

 1 Compression / Expansion Device 10 System Bus 16 Memory 30 Control Unit 31 ISDN Interface Circuit 32 Line Expansion Unit Unit 34 Communication Unit 35 Modem 36 NCU 100 Image Bus Control Unit 200 Internal RAM 216 Line Memory 300 Internal Bus DMA Control Unit 400 System Bus Control Unit 500 Working Register 600 Changed Pixel Detection Unit 700 Changed Pixel Detection Unit 800 Changed Pixel Detection Unit 1200 Arithmetic Logic Operation Unit 1300 Decoder 1400 Image Conversion Unit 1500 Encoder 1600 Micro Program Control Unit 1700 DMA Control Bus 1800 Internal Data Bus 1900 Internal Data Bus

Claims (3)

[Claims] 1. A communication procedure for transmitting image code data to a plurality of image receiving terminals at the same time using a plurality of lines, and image code data according to the receiving capability of each image receiving terminal during the communication procedure. An image communication apparatus for executing code conversion processing of a plurality of lines, a plurality of line-corresponding communication units for a line interface, a code conversion apparatus commonly used for code conversion processing for image receiving terminals for a plurality of lines, For temporarily storing the image code data before and after the code conversion process by the code conversion device, and a control unit for controlling the call procedure and the communication procedure for the image reception terminal and the code conversion process by the code conversion device. Image communication device that is connected to the memory of the bus. 2. The image communication device according to claim 1, wherein a combination of N communication units and one code conversion device constitutes a unit unit for line extension. 3. A communication procedure for transmitting image code data to a plurality of image receiving terminals at the same time using a plurality of lines, and image code data according to the receiving capability of each image receiving terminal during the communication procedure. An image communication apparatus for executing code conversion processing of a plurality of lines, a plurality of line-corresponding communication units for a line interface, a code conversion apparatus commonly used for code conversion processing for image receiving terminals for a plurality of lines, For temporarily storing the image code data before and after the code conversion process by the code conversion device, and a control unit for controlling the call procedure and the communication procedure for the image reception terminal and the code conversion process by the code conversion device. And a plurality of processing blocks for performing code conversion processing of image code data, and the plurality of processing blocks. A plurality of line memories necessary for executing lock processing, a block for interfacing with the external bus, an internal bus for transferring data to the line memory and each block, and a block for controlling each block An image communication apparatus comprising: