JPH06291189A - Gate array - Google Patents

Abstract

PURPOSE:To provide a gate array which prevents signal leakage which is called stroke noise between adjacent signal lines extended between ECL basic cells which perform high-speed operation. CONSTITUTION:A grounding cable 50 is arranged in a wiring area between the ECL basic cells 40 of an gate array whereupon CMOS basic cells and ECL basic cells 40 are arranged in array, and signal lines 44 and 45 are formed by sandwiching the grounding cable 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption CMO.
The CMOS logic cell area forming the S logic circuit and the ECL logic cell area forming the high-speed ECL logic circuit are set to 1
The present invention relates to a gate array provided in a chip.

[0002]

2. Description of the Related Art With the miniaturization of LSI manufacturing technology, the number of elements integrated in one chip of integrated circuits has dramatically increased from several hundred thousand to several million transistors. With higher integration, the parasitic capacitance of transistors in integrated circuits is becoming smaller. For this reason, it has become possible to operate at a frequency of several tens of MHz to several hundreds of MHz even with CMOS, which has conventionally been considered to have low power consumption but slow operation.

Also in the gate array, it has been proposed to realize high speed and low power consumption with one chip.
For example, the structure of a conventional gate array is shown in FIG. The gate array shown in the figure has a structure in which an ECL basic cell region that operates at high speed using ECL logic gates and a CMOS basic cell region that operates with low power consumption using CMOS logic gates are arranged in one chip. Have.

In FIG. 6, reference numeral 1 denotes one chip composed of a single crystal silicon substrate having a rectangular planar shape,
A plurality of external terminals 2 (bonding pads) are arranged in the peripheral region of the element formation surface along each rectangular side of the chip 1. An input / output buffer circuit 3 is arranged on the element formation surface of the chip 1 inside the external terminal 2 and in a region close to the external terminal 2.

Input / output buffer circuits 3 are arranged corresponding to the arrangement of external terminals 2. Although the input / output buffer circuit 3 does not show a detailed configuration, input buffer circuit cells and output buffer circuit cells are arranged.

In the input buffer circuit cell, for example, a complementary MISFET forming an input first stage circuit, a resistance element forming an electrostatic breakdown preventing circuit, a clamp MISFET, and the like are arranged. In the output buffer circuit cell, for example, a complementary MISFET, a bipolar transistor, or the like that constitutes the final output stage circuit is arranged. The input / output buffer circuit 3 can selectively connect either of the semiconductor elements forming the input buffer circuit or between the semiconductor elements of the output buffer circuit to form an input buffer circuit or an output buffer circuit.

In the area surrounded by the input / output buffer circuit 3, the CM is formed in the element formation area of the chip.
A CMOS basic cell region 11 in which CMOS basic cells 10 forming an OS logic gate are arranged in an array in m rows and n columns
And an ECL basic cell region 13 in which ECL basic cells 12 forming an ECL logic gate are arranged in an array form in k columns and i rows.
And a level signal conversion region 14 for converting the input / output signal level between ECL-CMOS is arranged in the boundary region between the CMOS basic cell region 11 and the ECL basic cell region. In the level signal conversion region 14, CMOS to EC
Bidirectional level converters to L and ECL to CMOS are included, and the connection between the CMOS region and the bipolar region described above is performed through each level converter.

FIG. 7 is a CMO of the gate array shown in FIG.
An example of the master portion of the CMOS basic cell 10 that constitutes the S logic gate is shown. In FIG. 7, 20 is a source or drain region of an NMOS transistor, and 21 is a PMOS.
Source or drain region of transistor, 22 is NM
The gate region of the OS transistor, 23 is the gate region of the PMOS transistor, 24 is the P-type substrate electrode region for taking the substrate potential of the NMOS transistor, and 25 is the PMOS.
Each of the N-type substrate electrode regions for taking the substrate potential of the transistor is shown.

A metal wiring is formed on a master of a basic cell constituting the CMOS logic circuit in a process called a slice to form the CMOS logic circuit.

FIG. 8 shows an example of the metal wiring of the slice formed by using FIG.

In FIG. 8, reference numeral 26 is a contact hole for connecting the source / drain region or gate region of the master portion, the substrate electrode region and the wiring 27 of the first layer formed thereon, and 28 is a first hole. Through holes for connecting the wiring 27 of the second layer and the wiring 29 of the second layer are respectively shown. The wiring 29 of the second layer is provided in the CMOS basic cell region 11 shown in FIG. It serves as a connection point for automatically wiring between the cells of the arranged slices.

As shown in FIG. 9, the wiring between the slice cells is automatically arranged and set in the wiring area 41 between the pair of master ECL basic cells 40 arranged in the ECL basic cell area 13 of FIG. Is performed along the wiring grid 43 for. The basic cell has a lead-out terminal 42 along a wiring grid 43.
Therefore, the wiring between the slice cells is the wiring grid 43.
Along the lead terminals 42 of the basic cell.

FIG. 10 shows an example of wiring between the basic cells in FIG. In FIG. 10, 44 is a second-layer signal line, 45 is a first-layer signal line, and 46 is a through hole. The connection between the signal line 45 of the first layer and the signal line 44 of the second layer is made by providing a through hole 46 on any of the wiring grids 43 shown in FIG.

Next, the structure of the bipolar transistor of the ECL basic cell will be described.

The npn-type bipolar transistor of the ECL logic cell is composed of an n-type collector region, a p-type base region and an n-type emitter region in a region surrounded by the element isolation region. The n-type collector region is composed of an n-type well region used as an intrinsic collector region, a buried n-type semiconductor region used as a graft collector region, and an n-type semiconductor region for raising collector potential.
The p-type base region is composed of a p-type semiconductor region. The n-type emitter region is composed of an n-type semiconductor region.

Next, the operation will be described. Bipolar C
In the MOS mixed gate array, a high speed operation is processed by a bipolar linear circuit and a low power consumption operation is processed by a CMOS circuit. Such a bipolar CMOS mixed gate array is
CMO even in ECL basic cell area operated at high speed
Since the wiring structure is the same as that of the S basic cell region, a signal having a high frequency passes through a signal passing through the ECL basic cell region and the wiring region. Therefore, as shown in FIG. 11, when the distances between the wirings A, B, and C become closer, the line capacitances C1 and C2 of the wirings A and B and B and C cannot be ignored. When the wirings A, B, and C are all signal lines, the signal is transmitted from the line A to the line B through C1 and from the line B to C2 as a signal corresponding to the changing frequency of each signal line.

[0017]

Since the conventional gate array is constructed as described above, when the integration of the ECL basic cell area composed of bipolar linear and the high speed operation circuit are advanced. As the number of signal lines arranged per unit area increases, the distance between signal lines becomes shorter and shorter. When a signal of several 100 MHz is transmitted there by wiring between cells, signal leakage due to AC coupling of wiring capacitance called crosstalk noise occurs between adjacent signal lines, which causes the functional LSI to function. However, there is a problem that the reliability of the circuit operation is reduced, and the high-speed logic gate and the low-speed logic gate cannot be efficiently integrated.

The invention of claim 1 has been made to solve the above problems, and a signal line is provided in the wiring region between ECL basic cells with a ground line extending in the X and Y directions interposed therebetween. The purpose of this is to prevent crosstalk noise between adjacent signal lines.

It is an object of the present invention to provide a wiring grid for arranging signal lines with the ground wire interposed therebetween, whereby wiring can be arranged with a high wiring density.

According to a third aspect of the present invention, a third grounded line different from the signal line for connecting the entire wiring region to the basic cells is further provided on the first and second ground lines extending in the X and Y directions. By covering with a ground line layer, the purpose is to improve the noise shielding effect and prevent crosstalk noise between adjacent signal lines.

The invention of claim 4 is the first, second and third aspects.
It is an object of the present invention to reduce the wiring load and prevent the crosstalk noise by forming the ground wire of (1) in the first layer, the second layer and the third layer.

It is an object of the present invention to provide a wiring grid for arranging the signal lines with the ground line interposed therebetween, thereby increasing the wiring density and arranging the wiring.

According to a sixth aspect of the present invention, the first and second ground lines are extended in the X and Y directions, and signal lines are provided with the ground lines sandwiched therebetween, and the signal lines are provided on the ground lines and in the X and Y directions. First,
The wiring load can be reduced and the noise shielding effect can be obtained by providing the entire wiring region between the second ground lines so as to be covered with the third and fourth ground line layers that are different from the signal lines connecting the basic cells. And to prevent vertical crosstalk noise.

It is an object of the present invention to provide a wiring grid for arranging signal lines with a ground wire interposed therebetween so as to increase the wiring density and arrange the wiring.

[0025]

According to another aspect of the present invention, there is provided a gate array in which a ground line extending in the X and Y directions is arranged in a wiring region provided between ECL basic cells, and the ground line is connected to the ground line. A signal line is provided between them.

The gate array according to the invention of claim 2 is E
A wiring grid for arranging signal lines is provided with a ground line in a wiring region between CL basic cells interposed therebetween.

A gate array according to the invention of claim 3 is
On the first and second ground lines extending in the X and Y directions, a third ground line in a layer different from the signal line that covers the entire wiring region and connects between the basic cells is provided.

In the gate array according to the invention of claim 4, the first, second and third ground lines are provided in the first layer, the second layer and the third layer.
They are formed in layers and are layered.

A gate array according to the invention of claim 5 is E
A wiring grid for arranging signal lines is provided with a ground line in a wiring region between CL basic cells interposed therebetween.

The gate array according to the invention of claim 6 is X
And a fourth ground line between the first and second ground lines extending in the Y direction and a third ground line on the first and second ground lines, and these layers are connected between the basic cells. It is provided by covering the entire wiring region with a layer different from the signal line.

The gate array according to the invention of claim 7 is E
A wiring grid for arranging signal lines is provided with a ground line in a wiring region between CL basic cells interposed therebetween.

[0032]

According to the first aspect of the invention, in the gate array, a ground line extending in the X and Y directions is provided in the wiring region of the ECL basic cell region in which a high frequency signal is input, and the ground lines are adjacent to each other. The noise generated between the signal lines due to the provision of the signal to be absorbed is absorbed by the ground line, so that the generation of crosstalk noise between the adjacent signal lines can be prevented.

The gate array according to the invention of claim 2 is
Among the wirings formed through the wiring grid in the wiring region, the wiring between adjacent signal lines is formed as a ground line,
The wiring can be arranged with a high wiring density.

The gate array according to the invention of claim 3 is
First and second ground lines extending in the X and Y directions are provided in the wiring region, signals adjacent to each other are provided with the ground lines interposed therebetween, and noise generated between the adjacent signal lines is the ground. The third ground line that is absorbed by the line and covers the entire wiring region on the second ground line is provided at a different layer level from the signal line that connects the basic cells. By sandwiching some of the signal lines with the first and second ground lines, it is possible to enhance the noise shielding effect and prevent crosstalk noise between adjacent signal lines.

The gate array according to the invention of claim 4 is
First and second ground lines extending in the X and Y directions are formed in the first and second layers, and the third ground line is provided on the ground lines and covers the entire wiring region to form the third ground line in the third layer. Since it is formed as described above, the wiring load can be reduced and crosstalk noise can be prevented.

The gate array according to the invention of claim 5 is
Among the wirings formed through the wiring grid in the wiring region, the wiring between adjacent signal lines is formed as a ground line,
The wiring can be arranged with an increased wiring density.

The gate array according to the invention of claim 6 is
First and second ground lines extending in the X and Y directions are provided in the wiring region, signals adjacent to each other are provided with the ground lines interposed therebetween, and noise generated between the adjacent signal lines is the ground. A third ground line which is absorbed by the line and covers the entire wiring region on the second ground line, and a fourth ground line which covers the entire wiring region is provided between the first and second ground lines. Since the third and fourth ground lines are provided as separate lines in the signal line connecting the basic cells, the wiring load can be reduced, the noise shielding effect can be improved, and the vertical crosstalk can be further improved. Noise can be prevented.

A gate array according to the invention of claim 7 is
Among the wirings formed through the wiring grid in the wiring region, the wiring between adjacent signal lines is formed as a ground line,
The wiring can be arranged with a high wiring density.

[0039]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view showing an ECL basic cell region composed of an ECL basic cell and a wiring region according to an embodiment of the invention of claim 1, and FIG. 2 is a plan view showing a state in which wiring is applied in the slicing process in FIG. And FIG. 1 and FIG.
The same or corresponding parts as those in FIGS. 9 and 10 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, the wiring region 4 is provided between the master cells 40 and 40 of the ECL basic cells which form the ECL logic circuit.
1 is provided. The wiring region 41 has a wiring grid 43 for automatically wiring the signal lines. The wiring grid 43 is usually provided as information in the design tool. The spacing between the wiring grids is predetermined by the design rule of the design.

For example, in the design rule: 0.8 μm, the distance between the wiring grids of the first layer is 2.4 μm and the distance of the second layer is 3.2 μm.

Reference numeral 42 is a lead-out terminal from the in-cell wiring formed on the master cell 40 of the ECL basic cell. Fifty
Is a plurality of wirings provided between wiring grids and extending in the X direction. Reference numeral 51 is a plurality of wirings provided between the wiring grids and extending in the Y direction. These wirings 50 and 51 are connected to the power supply line at the ends in the column direction of the ECL basic cell 40 and serve as a ground line.
The ground line 50 (first ground line) is formed using the first wiring layer, and the ground line 51 (second ground line) is formed using the second wiring layer.

That is, the ground line 50 is the ECL basic cell 4
After forming an npn-type bipolar transistor forming 0 in the substrate, it is formed between the wiring grid 43 and the wiring grid 43 (corresponding to the invention of claim 2). After this step, the signal line 44 connecting the transistors of the ECL basic cells 40, 40 is formed using the second wiring layer. The ground line 51 is formed simultaneously with the formation of the signal line 44.
The first and second wiring layers are formed by depositing Al.

FIG. 2 shows the above-mentioned connected state.
In FIG. 2, 45 is a predetermined wiring grid 4 for the first layer wiring.
3 is a signal line extending in the X direction passing above the wiring 3, and is formed as the first wiring layer. Therefore, at the level of the first layer, the ground line 50 is connected to the signal line 4 adjacent to each other in the X direction.
It is arranged between 5 and 45. The arrangement of the first layer is the same in the basic cell.

Further, the signal line 44 is the ECL basic cell 40,
The signal line 44 is a second-layer signal line that connects between the 40 bipolar transistors, and the signal line 44 extends in the Y direction passing over a predetermined wiring grid 43 for the second-layer wiring. Therefore, 2
Also in the layer, the ground line 51 is arranged between the signal lines 44 and 44 which are adjacent to each other in the Y direction, similarly to the arrangement state of the wiring of the first layer.

The first-layer signal line 45 and the second-layer signal line 44
And are connected to each other using a through hole 46.

Although the first ground line extending in the X direction is formed in the first layer and the second ground line extending in the Y direction is formed in the second layer in the above, the first and second layers are formed. The ground line may be formed in the first layer, and the point where both lines intersect may be formed via the insulating layer. Further, although the ground line is formed by one line, it may be divided into a plurality of lines and arranged between the adjacent signal lines.

Further, comparing the number of wiring grids of FIG. 1 of one embodiment of the present invention with that of FIG. 9 of the prior art, in FIG.
Since 0 and 51 are provided, the number of wiring grids for forming signal lines is about 1/4 of the conventional one. The ground wire 50, 51
A wiring grid 43 for arranging the signal lines is provided with the signal line interposed therebetween. Note that the spacing between wiring grids is determined by the minimum criteria of the manufacturing process used.

In the wiring design of the bipolar CMOS gate array, most of the wiring is automatically designed by the automatic wiring system, but the ECL basic cell area in which high speed operation is performed can be designed manually or semi-manually. Is.

Next, the operation will be described. Bipolar CM in which CMOS and ECL logic gates are mixed on one chip
The digital signal of the CMOS basic cell 10 of the OS gate array enters the level signal conversion region 14. The CMOS level signal that has entered the level signal conversion region 14 is level-converted so that only a high-frequency signal passes through the signal line and EC.
Enter the L basic cell 40. The signal line that has entered the ECL basic cell 40 has the first and second ground lines 5 extending in the X and Y directions in the wiring region 41 between the basic cells 40 and 40 shown in FIG.
Since the signal lines 44 and 45 are arranged so as to sandwich 0 and 51, noise generated between the signal lines is absorbed by the ground lines 50 and 51.

According to the configuration of the first embodiment, the wiring region 41 of the ECL basic cell 40 in which the high speed signal line is arranged is provided.
By disposing the ground lines 50 and 51 extending in the X and Y directions with the signal lines 44 and 45 interposed therebetween, it is possible to prevent generation of crosstalk noise between adjacent signal lines. .

Example 2. 3 is a plan view showing an ECL basic cell region consisting of an ECL basic cell and a wiring region according to an embodiment of the invention of claim 3, and FIG. 4 is a sectional view taken along the line AA of FIG. 3 in which signal lines are arranged. It is a figure, and in FIG.3 and FIG.4, the same code | symbol is attached | subjected to FIG.9 and FIG.10 and an equivalent part, and description is abbreviate | omitted.

In FIG. 3, the wiring region 41 passes over the ground line (first ground line) 50 extending in the X direction of the first layer and the ECL basic cell 40 extending in the Y direction of the second layer. A ground line (second ground line) 51 and a third-layer ground line (third ground line) 60 that covers the entire wiring region 41 including the first-layer and second-layer ground lines 50, 51 are provided. ing. This 3
The ground line 60 of the layer is shown surrounded by a dotted line. Reference numeral 61 is a through hole for connecting the ground lines 50 and 60 of the first and third layers inside the basic cell as shown in FIG. Further, similarly to FIG. 1, a wiring grid 43 for arranging the signal lines is provided with the ground lines 50 and 51 interposed therebetween (claim 5).

In FIG. 4, a ground line 50 extends in the X direction between adjacent signal lines 45, 45 in the first wiring layer of the ECL basic cell 40 and the wiring region 41 between them. ing. A signal line 44 is arranged in the second wiring layer so as to extend in the Y direction. In the third wiring layer, the ground line 60 is provided only in the wiring region 41 so as to cover the entire region (claim 4). The ground line 60 is formed in a layer different from the signal line connecting the basic cells. The ground wire 60 of the third layer and the ground wire 7 of the first layer inside the ECL basic cell 40
A through hole 61 is provided to connect the first and second electrodes. Reference numeral 70 is a substrate. In the above description, the first ground line extending in the X direction is formed in the first layer and the second ground line extending in the Y direction is formed in the second layer. It may be formed as a layer and a point where both lines intersect may be formed via an insulating layer.

According to the configuration of the second embodiment, the entire wiring region between the ECL basic cells 40 on the ground line is covered with the ground line 60 different from the signal line connecting the ECL basic cells 40. , The shield effect more than that of disposing the ground line between the adjacent signal lines can be obtained, crosstalk noise can be prevented, and the wiring load can be reduced because the wiring is hierarchized.

Example 3. FIG. 5 is a cross-sectional view of an ECL basic cell 40 and a wiring region 41 according to an embodiment of the invention of claim 6, and in FIG. 5, the same or corresponding parts as those in FIG. 9 and FIG. The description is omitted.

In FIG. 5, in the wiring region 41, a ground line (first ground line) 50 extending in the X direction is provided between the signal lines 45 and 45 adjacent to the first layer, and ECL
A ground line 71 is also formed between the signal lines 45 inside the basic cell 40. The second layer wiring is the ground wire (fourth ground wire)
It is formed of only 80 and covers the entire wiring region 41.
Reference numeral 81 is a third-layer signal line, and a ground line (second ground line) extending in the Y direction is formed between the signal lines 81. Four
The wiring of the layer is formed only by the ground line (third ground line) 82 and covers the entire wiring region 41 (claim 7). The third and fourth ground lines are formed in a layer different from the signal line connecting the basic cells. Reference numeral 83 is a through hole that connects the ground wires of the second and fourth layers. Although not shown in the drawing, wiring grids for arranging the signal lines are provided in the wiring regions 41 of the first and third layers in the drawing with the ground line interposed therebetween as in FIG. (Claim 7).

According to the structure of the third embodiment, the second layer and the fourth layer are
Since the layers 80 and 82 dedicated to the ground lines are provided in the layer and the layer dedicated to the ground lines 80 and 82 is provided to cover the entire wiring region, the signal line is shielded by the upper and lower ground lines. . Therefore, crosstalk noise in the vertical direction can be prevented, and the wiring load can be reduced because the wiring is hierarchical.

[0059]

As described above, according to the invention of claim 1, the signal lines extending in the X and Y directions are adjacent to each other in the wiring region between the ECL basic cells in which the high-speed signal lines are arranged. Since the first and second ground lines are provided, the crosstalk noise between the adjacent signal lines can be prevented.

According to the second aspect of the present invention, since the wiring grid for arranging the signal lines is provided with the ground line interposed therebetween,
This has the effect of increasing the wiring density and arranging the wiring.

According to the third aspect of the present invention, the whole wiring region is further covered with the ground line layer other than the signal line connecting between the basic cells on the first and second ground lines. Therefore, there is an effect that the noise shield effect is increased and crosstalk noise between adjacent signal lines can be prevented.

According to the invention of claim 4, since the ground line is provided in the third layer and the wiring is layered, the wiring load can be reduced and the crosstalk noise can be prevented.

According to the invention of claim 5, since the wiring grid for arranging the signal line is provided with the ground wire interposed therebetween,
This has the effect of increasing the wiring density and arranging the wiring.

According to the sixth aspect of the invention, the ground wire is connected to X, Y.
In addition, the wiring load can be reduced because it is configured to extend in the direction and further to cover the entire wiring region between the ground lines and on the ground line with a grounded layer different from the signal line connecting the basic cells. In addition, it has the effect of increasing the noise shielding effect and preventing vertical crosstalk noise.

According to the invention of claim 7, since the wiring grid for arranging the signal line is provided with the ground wire interposed therebetween,
This has the effect of increasing the wiring density and arranging the wiring.

[Brief description of drawings]

FIG. 1 is a plan view showing an ECL basic cell region including an ECL basic cell and a wiring region of a gate array according to an embodiment of the present invention.

FIG. 2 is a plan view showing a state where the master of FIG. 1 is connected in a slicing process.

FIG. 3 is a plan view showing an ECL basic cell region including an ECL basic cell and a wiring region of a gate array according to an embodiment of the invention of claim 3;

FIG. 4 is a cross-sectional view taken along the line AA of FIG. 3 showing a state in which signal lines are arranged.

FIG. 5 is a sectional view showing an ECL basic cell and a wiring region of a gate array according to an embodiment of the invention of claim 6;

FIG. 6 is a plan view showing a conventional gate array chip.

FIG. 7 is a plan view showing a master portion of the CMOS basic cell of FIG.

FIG. 8 is a plan view showing a state in which wiring is provided on the CMOS basic cell of FIG.

FIG. 9 is a plan view showing a basic cell and a wiring region of a conventional gate array.

FIG. 10 is a plan view showing a state in which wiring is provided in FIG.

FIG. 11 is an explanatory diagram showing the principle of noise generation between signal lines.

[Explanation of symbols]

 10 CMOS Basic Cell 11 CMOS Basic Cell Area 12, 40 ECL Basic Cell 13 ECL Basic Cell Area 41 Wiring Area 43 Wiring Grid 44, 45 Signal Line 50 Ground Line (First Ground Line) 51 Ground Line (Second Ground Line) ) 60,82 Ground wire (third ground wire) 80 Ground wire (fourth ground wire)

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[Procedure amendment]

[Submission date] August 9, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

As shown in FIG. 11, the npn-type bipolar transistor of the ECL logic cell is composed of an n-type collector region, a p-type base region and an n-type emitter region in a region surrounded by the element isolation region. It The n-type collector region includes an n-type well region used as an intrinsic collector region, a buried n-type semiconductor region used as a graft collector region, and a collector potential raising n-type semiconductor region. The p-type base region is composed of a p-type semiconductor region. The n-type emitter region is composed of an n-type semiconductor region.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

Next, the operation will be described. Bipolar C
In the MOS mixed gate array, a high speed operation is processed by a bipolar linear circuit and a low power consumption operation is processed by a CMOS circuit. Such a bipolar CMOS mixed gate array is
CMO even in ECL basic cell area operated at high speed
Since the wiring structure is the same as that of the S basic cell region, a signal having a high frequency passes through a signal passing through the ECL basic cell region and the wiring region. Therefore, as shown in FIG. 12, when the distances between the wirings A, B, and C become closer, the line capacitances C1 and C2 of the wirings A and B and B and C cannot be ignored. When the wirings A, B, and C are all signal lines, the signal is transmitted from the line A to the line B through C1 and from the line B to C2 as a signal corresponding to the changing frequency of each signal line.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0058

[Correction method] Change

[Correction content]

According to the structure of the third embodiment, the second layer and the fourth layer are
Since the layers 80 and 82 dedicated to the ground lines are provided in the layer and the layers dedicated to the ground lines 80 and 82 are provided to cover the entire wiring region, the signal lines are shielded by the upper and lower ground lines. . Therefore, crosstalk noise in the vertical direction can be prevented, and the wiring load can be reduced because the wiring is hierarchical. Also, the ECL basic cell part performs high-speed processing.
Although it has been described as a specific example for
For high speed and basic cells that compose BiCMOS gate
The same applies when using an optimally designed CMOS basic cell
effective.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11 is a layout diagram of an ECL basic cell.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 12

[Correction method] Added

[Correction content]

FIG. 12 is an explanatory diagram showing the principle of noise generation between signal lines.
is there.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 12

[Correction method] Added

[Correction content]

[Fig. 12]

Claims (7)

[Claims] 1. A CMOS forming a CMOS logic gate.
A CMOS basic cell region in which basic cells are arranged in an array,
In a gate array provided with an ECL basic cell region in which ECL basic cells forming an ECL logic gate are arranged in an array in one chip, the ECL basic cell region is EC
A wiring region is provided between the L basic cells, and the wiring region includes X, Y
A gate array comprising: first and second ground lines extending in a direction; and signal lines sandwiching the ground lines. 2. The gate array according to claim 1, wherein a wiring grid for arranging signal lines is provided with the ground line interposed therebetween. 3. CMOS forming a CMOS logic gate
A CMOS basic cell region in which basic cells are arranged in an array,
In a gate array provided with an ECL basic cell region in which ECL basic cells forming an ECL logic gate are arranged in an array in one chip, the ECL basic cell region is EC
A wiring region is provided between the L basic cells, and the wiring region includes X, Y
The first and second ground lines extending in the direction, the signal lines arranged so as to sandwich the ground line, and the first and second ground lines provided on the first and second ground lines to cover the entire wiring region. A gate array comprising a signal line connecting between the basic cells and a third ground line on a different layer. 4. The first ground line is formed on the first layer, the second ground line is formed on the second layer, and the third ground line is formed on the third layer, respectively. Item 3. A gate array according to item 3. 5. The gate array according to claim 3, wherein a wiring grid for arranging signal lines is provided with the ground line interposed therebetween. 6. A CMOS forming a CMOS logic gate.
A CMOS basic cell region in which basic cells are arranged in an array,
In a gate array provided with an ECL basic cell region in which ECL basic cells forming an ECL logic gate are arranged in an array in one chip, the ECL basic cell region is EC
A wiring region is provided between the L basic cells, and the wiring region includes X, Y
A first and a second ground line extending in the direction, a signal line arranged with the ground line interposed therebetween, a third ground line provided on the first and second ground lines, and X. , A fourth ground line provided to cover the entire wiring region between the first and second ground lines extending in the Y direction, and the third and fourth ground lines are provided between the basic cells. A gate array, wherein the gate array is formed in a layer different from that of the signal line for connecting. 7. A gate array, wherein a wiring grid for arranging signal lines is provided with the ground line interposed therebetween.