JPH06291076A - Junction structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the aluminum spike resistance of a junction between a diffusion layer and a wiring, and prevent the increase in diffusion layer capacitance. CONSTITUTION:A first diffusion layer 12 with phosphorus lightly diffused is formed in a semiconductor substrate 11, and a second diffusion layer 13 with arsenic or antimony heavily diffused is formed in a part of the uppermost area thereof. A third diffusion layer 14 with phosphorus heavily diffused is formed. The third diffusion layer 14 is deeper than the first diffusion layer 12 and positioned within the range of the second diffusion layer 13 on the surface of the semiconductor substrate 11. The resultant diffusion layer 15 of the junction structure mentioned above is applicable as the source/drain region in MOS transistors, the source/drain region in output transistors included in the output circuits in solid-state imaging devices, floating diffusion layers and so on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction structure in which a diffusion layer of a semiconductor device is connected to a wiring, and more particularly, the diffusion layer of a MOS transistor is connected to a wiring or the diffusion of a voltage conversion transistor of a solid-state imaging device. The present invention relates to a joint structure relating to connection between layers and wiring, and a method for manufacturing the same.

[0002]

2. Description of the Related Art An example of a conventional joint structure will be described with reference to an explanatory view of an output circuit section of a CCD image pickup device shown in FIG.
In the figure, a layout diagram is shown in (1) and BB is shown in (2).
A line outline sectional view is shown.

As shown in the figure, a gate electrode 103 is formed on the surface of a semiconductor substrate 101 via a gate insulating film 102. The source / drain regions 1 are formed on the semiconductor substrate 101 on both sides of the gate electrode 103.
04 and 105 are formed.

Further, the reset transistor 111 and the horizontal output transistor 1 provided on the upper layer of the semiconductor substrate 101.
The high-concentration diffusion layer 1 is formed in the upper layer of the source / drain region 113 such as 12 and the portion to which the wiring 127 described later is connected.
06 is formed. The high concentration diffusion layer 106 is in a floating state with respect to the source / drain region 113.

Further, an interlayer insulating film 121 is formed on the semiconductor substrate 101. Contact holes 122, 123, and 124 are formed in the interlayer insulating film 121 on the source / drain regions 104 and 105 and on the high-concentration diffusion layer 106. The wiring 125 is a source through the contact hole 122. Contact hole 1 connected to drain region 104
The wiring 126 extends through the source / drain region 105
It is connected to the. Further, the wiring 127 is connected to the high concentration diffusion layer 106 through the contact hole 124.

The source / drain regions 104 and 105
The high-concentration diffusion layer 106 is formed by diffusing arsenic, phosphorus, etc. in a relatively high concentration. For example, in the case where the source / drain regions 104 and 105 and the high-concentration diffusion layer 106 are formed by diffusing arsenic in a high concentration, since the diffusion coefficient value of arsenic is small, the junction depth is shallow.

[0007]

However, since the arsenic diffused at a high concentration, such as the source / drain regions and the high concentration diffusion layer (hereinafter referred to as the diffusion layer), has a shallow junction depth. When an aluminum spike occurs at the junction with the wiring, the aluminum spike penetrates the diffusion layer and causes a junction leak. As a result, the reliability of the device is significantly reduced.

In a CCD element having a so-called aluminum shunt structure in which the wiring also serves as a light-shielding film, when an aluminum-silicon alloy is used as the wiring material in order to suppress the generation of aluminum spikes, silicon is deposited inside the aluminum-silicon alloy. Then, the wiring easily transmits light. Therefore, the light that has passed through the wiring leaks into the transfer electrode, and the smear characteristic deteriorates. This means that
It becomes a fatal defect for the CD element. Therefore, CCD
The reliability of the device is greatly reduced.

Further, when phosphorus is diffused to a high concentration to form a diffusion layer, the diffusion layer is formed deeply because phosphorus is introduced to a deep position of the semiconductor substrate. Therefore, the problem of junction leakage due to the aluminum spike is solved, but since phosphorus has a larger diffusion coefficient than arsenic, the diffusion layer is formed to spread widely in the peripheral direction of the semiconductor substrate. For this reason, in the case of a MOS transistor, there is a large amount of overlap with the gate electrode. As a result, the gate electrode exists on the high-concentration n-type diffusion layer, so that the depletion layer does not extend to the semiconductor substrate side. For this reason, the capacity per unit area of this portion is increased, and the efficiency of converting charges into voltage is significantly reduced.

As described above, when the depth of the diffusion layer is made shallow, the problem of aluminum spike occurs, and when the depth of the diffusion layer is made deep, the capacity increases.

Further, if the concentration of the diffusion layer is lowered, the contact resistance between the wiring and the diffusion layer increases, and the driving capability of the output circuit is lowered.

An object of the present invention is to provide a highly reliable joint structure which eliminates junction leakage and a method for manufacturing the same.

[0013]

DISCLOSURE OF THE INVENTION The present invention is a joint structure and a method of manufacturing the same, which has been made to achieve the above object. That is, the junction structure is a junction structure formed by connecting the diffusion layer formed in the semiconductor substrate and the wiring, and the first diffusion layer in which low concentration phosphorus is diffused is formed in the semiconductor substrate. There is. Further, a second diffusion layer in which a high concentration of arsenic or antimony is diffused is formed in a part of the upper layer of the first diffusion layer. Further, a third diffusion layer in which a high concentration of phosphorus is diffused is formed in a state deeper than the first diffusion layer and within the range of the second diffusion layer on the surface of the semiconductor substrate. The diffusion layer in the junction structure is a MOS
These are the source / drain regions of the transistor. Alternatively, it is the source / drain region of the output transistor in the output circuit of the solid-state imaging device. Alternatively, it is a floating diffusion layer in the output circuit.

In the method for manufacturing the junction structure, in the first step, low concentration phosphorus is diffused in the semiconductor substrate to form the first diffusion layer. Then, in a second step, a high concentration of arsenic or antimony is diffused in a part of the upper layer of the first diffusion layer,
A second diffusion layer having a concentration higher than that of the first diffusion layer is formed, and the semiconductor substrate is deeper than the first diffusion layer and is within the range of the second diffusion layer on the surface of the semiconductor substrate. High-concentration phosphorus is diffused to form a third diffusion layer having a higher concentration than the first diffusion layer.

[0015]

In the above junction structure, the semiconductor substrate has the first diffusion layer in which low-concentration phosphorus is diffused, so that the depth of the diffusion layer does not become unnecessarily large. Further, by depleting the first diffusion layer, the capacitance of the diffusion layer is prevented from increasing. Further, since the second diffusion layer in which high-concentration arsenic or antimony is diffused is formed on the upper layer of the first diffusion layer, the contact resistance in connection with the wiring is reduced. Further, since the third diffusion layer in which a high concentration of phosphorus is diffused is formed in a state deeper than the first diffusion layer, a junction leak is generated against an aluminum spike when the wiring is made of an aluminum-based metal. It will not occur.

Further, the above junction structure is applied to the source / drain region of a MOS transistor, the source / drain region of a transistor, or the source / drain region of an output transistor in an output circuit of a solid-state image pickup device. Or the one applied to the floating diffusion layer or the like in the output circuit, the same effect as described above can be obtained.

In the method of manufacturing the above-mentioned junction structure, a low-concentration first diffusion layer is formed by utilizing the difference in diffusion coefficient of impurities and the difference in depth of introduction of impurities by, for example, an ion implantation method. A second diffusion layer having a higher concentration than that and a first diffusion layer
And a high-concentration third diffusion layer, which is deeper than the second diffusion layer. That is, the second diffusion layer is formed shallow by using arsenic or antimony having a small diffusion coefficient, and the third diffusion layer is formed deep by using phosphorus that can be introduced deeply.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the figure, the semiconductor substrate 11 has a first diffusion layer 12 formed by diffusing low-concentration phosphorus.
Are formed. The first diffusion layer 12 has a dose amount of about 1 × 10 ¹² cm ⁻² , for example. First above
In a part of the upper layer of the diffusion layer 12 of, for example, the dose amount is 1
A second diffusion layer 13 in which arsenic or antimony with a high concentration of approximately 10 ¹⁶ cm ^-2 is diffused is formed. Further, phosphorus having a high concentration, for example, a dose amount of about 1 × 10 ¹⁶ cm ⁻² was diffused in a state deeper than the first diffusion layer 12 and within the range of the second diffusion layer 13 on the surface of the semiconductor substrate 11. The third diffusion layer 14 is formed. Thus, the diffusion layer 15 is composed of the first, second, and third diffusion layers 12, 13, and 14.

An insulating film 16 is formed on the semiconductor substrate 11.
Are formed. A contact hole 17 is formed in the insulating film 16 on the diffusion layer 15. A wiring 18 connected to the diffusion layer 15 is formed through the contact hole 17.

In the above junction structure, the semiconductor substrate 11 is
Since the first diffusion layer 12 in which low-concentration phosphorus is diffused is formed, the depth of the diffusion layer 15 does not become unnecessarily deep. Further, since the second diffusion layer 13 in which high-concentration arsenic or antimony is diffused is formed on the upper layer of the first diffusion layer 12, the contact resistance in the connection with the wiring 18 is reduced. Furthermore, since the third diffusion layer 14 in which high-concentration phosphorus is diffused is formed in a state deeper than the first diffusion layer 12, it is possible to prevent the aluminum spike when the wiring 18 is formed of an aluminum-based metal. The resistance is improved and the junction leak does not occur.

Next, the second embodiment will be described with reference to the schematic sectional view of FIG. In the figure, the same components as those described in the first embodiment are designated by the same reference numerals.

As shown in the figure, a gate electrode 22 is formed on the semiconductor substrate 11 via a gate insulating film 21. Further, on the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 22, first diffusion layers 23 and 24 formed by diffusing low concentration phosphorus are formed. This first diffusion layer 2
3, 24 have a dose amount of about 1 × 10 ¹² cm ⁻² , for example. Second diffusion layers 25, 26 formed by diffusing high-concentration arsenic or antimony with a dose amount of about 1 × 10 ¹⁶ cm ⁻² are formed in a part of the upper layers of the first diffusion layers 23, 24. Has been done. Furthermore, the first diffusion layer 2
In a state deeper than 3, 24 and in the respective regions of the second diffusion layers 25, 26 on the surface of the semiconductor substrate 11, high-concentration phosphorus with a dose amount of about 1 × 10 ¹⁶ cm ⁻² is diffused, for example. The third diffusion layers 27 and 28 are formed. Thus, the diffusion layer 29 is composed of the first, second and third diffusion layers 23, 25 and 27, and the diffusion layer 30 is composed of the first, second and third diffusion layers 24, 26 and 28. To be done.
Each diffusion layer 29, 30 functions as a source / drain region of the MOS transistor 20. As above, MO
The S transistor 20 is configured.

An insulating film 31 is formed on the semiconductor substrate 11 so as to cover the gate electrode 22. Contact holes 32 and 33 are formed in the insulating film 31 on the diffusion layers 29 and 30. Further, wirings 34 and 35 are formed to connect to the diffusion layers 29 and 30 through the contact holes 32 and 33, respectively.

In the junction structure of the MOS transistor 20 described above, the semiconductor substrate 11 is formed with the first low-concentration phosphorus diffused therein.
Since the diffusion layers 23 and 24 are formed, the depth of the diffusion layers 29 and 30 does not become unnecessarily deep. Further, by depleting the first diffusion layers 23 and 24, it is possible to prevent the capacitance of the diffusion layers 29 and 30 from increasing. Also the first
By forming the second diffusion layers 25 and 26 in which high-concentration arsenic or antimony is diffused on the diffusion layers 23 and 24, the contact resistance in the connection with the wirings 34 and 35 is reduced. Furthermore, the first diffusion layers 23, 2
Since the third diffusion layers 27 and 28 in which high-concentration phosphorus is diffused are formed in a state deeper than 4, the wiring 34,
Even if an aluminum spike occurs when 35 is made of an aluminum-based metal, a junction leak is less likely to occur.

The junction structure as described in the first and second embodiments can be applied to, for example, the diffusion layer of the output circuit of the solid-state image pickup device. Therefore, as a third embodiment,
The diffusion layer of the output circuit of the solid-state imaging device will be described with reference to FIG. In the drawing, an example of a layout diagram is shown in (1) on the upper side, and a schematic cross-sectional view taken along the line AA is shown in (2) on the lower side.

As shown in the figure, the semiconductor substrate 41 has a reset transistor 61 and a horizontal output transistor 6.
2 and are provided. This reset transistor 6
1 and the horizontal output transistor 62 are connected to the semiconductor substrate 41.
The source / drain diffusion layer 63 formed in the upper layer is shared.

On the upper layer of the source / drain diffusion layer 63, the first diffusion layer 42 formed by diffusing low concentration phosphorus is formed. The first diffusion layer 42 has a dose amount of about 1 × 10 ¹² cm ⁻² , for example. In a portion of the upper layer of the first diffusion layer 42, for example, a dose amount of 1 ×
A second diffusion layer 43 in which arsenic or antimony with a high concentration of about 10 ¹⁶ cm ⁻² is diffused is formed. Furthermore the first
Of the high-concentration phosphorus having a dose amount of about 1 × 10 ¹⁶ cm ⁻² , for example, in a state deeper than the diffusion layer 42 and within the range of the second diffusion layer 43 on the surface of the semiconductor substrate 41. 3 diffusion layers 44 are formed. In this way, the diffusion layer 45 is constituted by the first, second, and third diffusion layers 42, 43, 44. Therefore, the diffusion layer 45 is formed in a floating state with respect to the source / drain diffusion layer 63.

The gate insulating film 5 is formed on the semiconductor substrate 41.
The gate electrode 52 is formed through the line 1. Further, on the upper layer of the semiconductor substrate 41 on both sides of the gate electrode 52, a first diffusion layer 53 formed by diffusing low concentration phosphorus,
54 is formed. The first diffusion layers 53 and 54
Has a dose amount of about 1 × 10 ¹² cm ⁻² , for example. A second diffusion layer 55, 5 in which a high concentration of arsenic or antimony having a dose amount of about 1 × 10 ¹⁶ cm ^-2 is diffused is formed in a part of each upper layer of the first diffusion layers 53, 54.
6 is formed. Further, in a state deeper than the first diffusion layers 53, 54 and at the second surface on the surface of the semiconductor substrate 41.
Within each range of the diffusion layers 55 and 56, for example, the dose amount is 1
3rd, which is formed by diffusing phosphorus with a high concentration of about 10 ¹⁶ cm ^-2
Diffusion layers 57 and 58 are formed. In this way, the first, second, and third diffusion layers 53, 55, and 57 form the diffusion layer 59, and the first, second, and third diffusion layers 54 and 5 are formed.
A diffusion layer 60 is composed of 6, 58. As described above, the output transistor 50 in which the diffusion layers 59 and 60 function as the source / drain regions is configured.

A diffusion layer 45 is formed on the semiconductor substrate 41.
The insulating film 71 is formed so as to cover the output transistor 50 and the like. Further, the insulating film 71 on the diffusion layer 45 and the diffusion layers 59 and 60 of the output transistor 50.
Contact holes 72, 73, and 74 are formed in the. Wirings 75 connected to the diffusion layers 45, 59, 60 through the contact holes 72, 73, 74,
76 and 77 are formed.

In the solid-state image pickup device using the above-mentioned junction structure, the wirings 75, 76 and 77 are made of aluminum,
It can be applied as a light-shielding film on the transfer electrode.
Further, the same effect as that described in the first and second embodiments can be obtained.

Next, a method of manufacturing the joint structure described in the first embodiment will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described in the first embodiment are designated by the same reference numerals.

As shown in FIG. 4A, in the first step, an ion implantation mask 81 is formed on the semiconductor substrate 11 by the usual photolithography technique. An opening 82 for introducing impurities is formed in the ion implantation mask 81.

Then, a low concentration of phosphorus 91 is introduced into the semiconductor substrate 11 by the ion implantation method. The dose amount at this time is set to, for example, 1 × 10 ¹² cm ⁻² . After that, the ion implantation mask 81 is removed by, for example, asher processing or wet etching.

Then, the second step shown in FIG. 4B is performed. In this step, the ion implantation mask 83 is formed by the usual photolithography technique. In the ion implantation mask 83, an opening 84 is formed in a region narrower than the set position of the opening 82.

Then, a high concentration of arsenic (or antimony) 92 is introduced at a shallow position in the upper layer of the semiconductor substrate 11 by the ion implantation method. The dose amount at this time is, for example, 1
It is set to × 10 ¹⁶ m ^-2 . Further, using the same ion implantation mask 83, high-concentration phosphorus 93 is introduced into the semiconductor substrate 11 in a state deeper than the low-concentration phosphorus 91 introduced previously. The dose amount at this time is set to, for example, 1 × 10 ¹⁶ m ^-2 . In this ion implantation method, the same ion implantation mask 83 is used for ion implantation, but it is also possible to newly form an ion implantation mask for each ion implantation and perform the ion implantation. After that, the ion implantation mask 83 is removed by, for example, asher processing or wet etching.

Thereafter, as shown in FIG. 4C, an annealing process is performed to diffuse and activate the introduced impurities in the semiconductor substrate 11. Then, the first diffusion layer 12 formed by diffusing the low concentration phosphorus 91 is formed in the semiconductor substrate 11. Further, a second diffusion layer 13 formed by diffusing arsenic (or antimony) 92 having a higher concentration than that of the first diffusion layer 12 is formed on the first diffusion layer 12. Furthermore, the first
The third diffusion layer 14 formed by diffusing phosphorus 93 having a higher concentration than that of the second diffusion layer 12 is deeper than the first diffusion layer 12 and within the range of the second diffusion layer 13 on the surface of the semiconductor substrate 11. To form. In this way, the diffusion layer 15 including the first, second and third diffusion layers 12, 13 and 14 is formed.

After that, as shown in FIG. 4D, the insulating film 16 is formed on the upper surface of the semiconductor substrate 11 by, for example, the CVD method as a normal film forming technique. Next, a contact hole 17 is formed in the insulating film 16 on the third diffusion layer 14 of the diffusion layer 15 by the usual photolithography technique and etching. Then, after forming a wiring forming film (not shown) by a normal wiring forming technique, a wiring 18 connected to the diffusion layer 15 through the contact hole 17 is formed by a photolithography technique and etching.

In the method of manufacturing the junction structure, for example, the difference in the depth of introduction of the impurities introduced into the semiconductor substrate 11 by the ion implantation method and the difference in the diffusion coefficient are utilized. That is, the low-concentration phosphorus 91 forming the first diffusion layer 12 is formed.
After the introduction of arsenic, arsenic (or antimony) 92 having a higher concentration than that for forming the second diffusion layer 13 is formed.
And a third deeper than the first diffusion layer 12 is introduced.
Then, a high concentration of phosphorus 93 that forms the diffusion layer 14 is introduced.
Thus, by introducing arsenic or antimony having a small diffusion coefficient shallowly, the second diffusion layer 13 is formed shallowly, and by introducing phosphorus having a large diffusion coefficient deeply, the third diffusion layer 14 is formed deeply. .

The method of manufacturing the joint structure described above is based on M
It can also be applied when forming the source / drain regions of the OS transistor. This case will be described below. It is not shown in the figure. The symbols in the description are
The reference numerals shown in FIG. 2 are given.

First, the gate insulating film 21 is formed on the upper surface of the semiconductor substrate 11, and then the gate electrode 22 is formed on the upper surface of the gate insulating film 21. Thereafter, in the same manner as in the above manufacturing method, the diffusion layer 29 including the first, second, and third diffusion layers 23, 25, and 27 having different impurity concentrations and impurity introduction depths.
To form. At the same time, a diffusion layer 30 including the first, second and third diffusion layers 24, 26 and 28 is formed. At this time, an ion implantation mask (not shown) used when forming the first diffusion layers 23 and 24 is provided so as to cover the gate electrode 22. By forming the ion implantation mask in this manner, the range in which the first diffusion layers 23 and 24 which are the source / drain regions of the MOS transistor are located below the gate electrode 22 is reduced.

The method of manufacturing the junction structure described above can also be applied to the case of forming the diffusion layer of the output circuit of the solid-state imaging device described with reference to FIG. The manufacturing method in this case will be described with reference to the manufacturing process diagram of FIG.

As shown in FIG. 5A, first, the gate insulating film 51 of the output transistor 50 is formed on the upper surface of the semiconductor substrate 41, and then the gate electrode 52 is formed on the upper surface of the gate insulating film 51. At this time, as other transistors, for example, gate insulating films (not shown) and gate electrodes (not shown) of a reset transistor (not shown) and a horizontal output transistor (not shown) are also formed.

Next, an ion implantation mask 85 is formed at a predetermined position by the usual photolithography technique. Subsequently, the source / drain diffusion layers 63 of the reset transistor (not shown) and the horizontal output transistor (not shown) are formed by ion implantation. After that, the ion implantation mask 85 used in this ion implantation method is removed.

Then, as shown in FIG. 5B, the ion implantation mask 86 is formed at a predetermined position by the ordinary photolithography technique by the method for manufacturing the junction structure. The ion implantation mask 86 is used for the gate electrode 5
It is provided to cover 2. Then, by the ion implantation method,
Low-concentration phosphorus 91 is introduced into a predetermined position of the source / drain diffusion layer 63 which will be the formation region of the first diffusion layer (42). At the same time, low-concentration phosphorus 91 is introduced into a predetermined position of the semiconductor substrate 41, which will be the formation region of the first diffusion layers (53) and (54). At this time, the gate electrode 52 can be used as a part of the ion implantation mask 86. That is, by using the gate electrode 52 as an ion implantation mask, the semiconductor substrate 41 on both sides of the gate electrode 52 is formed.
In addition, low-concentration phosphorus 91 is formed in the formation regions of the first diffusion layers (53) and (54) which become the source / drain regions in a self-aligned manner.
Will be introduced. Then, the ion implantation mask 86 is removed.

Next, as shown in FIG. 5C, an ion implantation mask 87 is formed at a predetermined position by a normal photolithography technique. Then, a high concentration arsenic (arsenic Or antimony) 92 is introduced. At the same time, the source / drain diffusion layer 6 is formed at a predetermined position of the semiconductor substrate 41, which will be a formation region of the third diffusion layers (57), (58) and (44).
A high concentration of phosphorus 93 is introduced at a predetermined position of 3. afterwards,
The ion implantation mask 87 is removed.

Thereafter, as shown in (4) of FIG. 5, an annealing process is performed to form first diffusion layers 53 and 54 formed by diffusing low-concentration phosphorus 91 on the upper layer of the semiconductor substrate 41. In addition, the second layer formed by diffusing high-concentration arsenic (or antimony) 92 in a part of the upper layers of the first diffusion layers 54 and 55.
Diffusion layers 55 and 56 are formed. Furthermore, the first diffusion layer 5
Third diffusion layers 57 and 58 formed by diffusing high-concentration phosphorus 93 in a state deeper than 3, 54 are formed. Thus, the diffusion layer 59 including the first, second and third diffusion layers 53, 55 and 57 is formed and the diffusion layer 60 including the second, second and third diffusion layers 54, 56 and 58. To form. At the same time, the first diffusion layer 43 formed by diffusing low-concentration phosphorus 91 is formed in a part of the source / drain diffusion layer 63.
The second diffusion layer 43 in which a high concentration of arsenic (or antimony) 92 is diffused in a part of the upper layer of the first diffusion layer 42.
To form. Further, a third diffusion layer 44 formed by diffusing high-concentration phosphorus 93 is formed in a state deeper than the first diffusion layer 42. In this way, the first, second and third diffusion layers 4
A diffusion layer 45 composed of 2, 43 and 44 is formed.

The diffusion layers 59 and 60 function as source / drain regions of the output transistor 50. The diffusion layer 45 also functions as a floating diffusion layer that connects a wiring (not shown) that is formed later to the source / drain diffusion layer 63.

[0048]

As described above, according to the present invention,
Since the first diffusion layer in which low concentration phosphorus is diffused is formed,
The diffusion layer capacity can be suppressed, and the reliability against hot carriers can be improved. Further, since the second diffusion layer in which high-concentration arsenic or antimony is diffused is formed on the first diffusion layer, the contact resistance at the connection with the wiring can be reduced, and the driving capability of the output circuit can be improved. . Further, since the third diffusion layer in which a high concentration of phosphorus is diffused is formed in a state deeper than the first diffusion layer, the occurrence of a junction leak due to an aluminum spike when the wiring is formed of an aluminum-based metal is eliminated, and the junction The reliability of can be improved.

Further, the above junction structure is applied to the source / drain region of a MOS transistor, the source / drain region of a transistor, or the source / drain region of an output transistor in an output circuit of a solid-state imaging device. Alternatively, the same effect as described above can be obtained by applying it to the floating diffusion layer.

According to the invention of the method for manufacturing the junction structure, the first, second and third diffusion layers having different concentrations are formed by utilizing the difference in diffusion coefficient of impurities introduced into the semiconductor substrate. A diffusion layer can be formed under the gate electrode of the MOS transistor without a high-concentration diffusion layer. Therefore, the capacitance per unit area does not increase, and the efficiency of converting the signal charge of the MOS transistor into a voltage does not decrease.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a schematic configuration sectional view of a second embodiment.

FIG. 3 is an explanatory diagram of a third embodiment.

FIG. 4 is a manufacturing process diagram of the first embodiment.

FIG. 5 is a manufacturing process diagram of the third embodiment.

FIG. 6 is an explanatory diagram of a conventional example.

[Explanation of symbols]

11 semiconductor substrate 12 first diffusion layer 13 second diffusion layer 14 third diffusion layer 15 diffusion layer 18 wiring 20 MOS transistor 23 first diffusion layer 24 first diffusion layer 25 second diffusion layer 26 second Diffusion layer 27 third diffusion layer 28 third diffusion layer 29 diffusion layer 30 diffusion layer 34 wiring 35 wiring 41 semiconductor substrate 42 first diffusion layer 43 second diffusion layer 44 third diffusion layer 45 diffusion layer 50 Output unit transistor 53 First diffusion layer 54 First diffusion layer 55 Second diffusion layer 56 Second diffusion layer 57 Third diffusion layer 58 Third diffusion layer 59 Diffusion layer 60 Diffusion layer 75 Wiring 76 Wiring 77 Wiring 91 Low-concentration phosphorus 92 High-concentration arsenic (or antimony) 93 High-concentration phosphorus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 29/796 21/336 29/784 (72) Inventor Hiroaki Oki 6-chome Kitashinagawa, Shinagawa-ku, Tokyo 7th 35th Sony Corporation

Claims (4)

[Claims] 1. A junction structure formed by connecting a diffusion layer formed on a semiconductor substrate and a wiring, wherein the diffusion layer is a first diffusion layer formed by diffusing low concentration phosphorus into the semiconductor substrate. A second diffusion layer formed by diffusing high-concentration arsenic or antimony in a part of the upper layer of the first diffusion layer, and a second diffusion layer deeper than the first diffusion layer and on the semiconductor substrate surface. And a third diffusion layer formed by diffusing high-concentration phosphorus within the range of the second diffusion layer. 2. The junction structure according to claim 1, wherein the diffusion layer is a source / drain region of a MOS transistor. 3. The one or both of the junction structure of the source / drain regions of the output transistor in the output circuit of the solid-state imaging device or the junction structure of the floating diffusion layer in the output circuit. The joint structure is characterized in that it is formed with the joint structure. 4. A method of manufacturing a junction structure comprising connecting a diffusion layer formed on a semiconductor substrate and wiring, wherein a low concentration phosphorus is diffused into the semiconductor substrate to form a first diffusion layer. 1) and diffusing high-concentration arsenic or antimony in a part of the upper layer of the first diffusion layer to form a second diffusion layer having a higher concentration than the first diffusion layer, and the semiconductor A third phosphorus having a concentration higher than that of the first diffusion layer is formed by diffusing high-concentration phosphorus into the substrate in a state deeper than the first diffusion layer and within the range of the second diffusion layer on the surface of the semiconductor substrate. 2. A method for manufacturing a joint, which comprises performing the second step of forming the diffusion layer.