JPH06290105A - Digital data storage - Google Patents

Abstract

PURPOSE:To improve the availability of memory capacity and to minimize the omission of image information by storing successively the 1st variable length code data in the order of lower memory addresses and the 2nd variable length code data vice versa and securing the synchronizing between the variable length code data read out from a low address through the center address and the variable length data read out from the highest address through the center address respectively in a reading mode. CONSTITUTION:A memory 31 of capacity equivalent to two blocks is provided together with a write address generating circuit 36 which outputs the address acquired by a positive or negative count-up operation, a read address generating circuit 40, a register 37 which stores the final address of one of both blocks, and a comparator 38 which compares the data on the other block with the write address stored in the memory 31, the address stored in the register 37, and the center address of the memory 31 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is suitable for digital data storage, for example, applied to a digital VTR having a conversion circuit for converting a variable length code block into a synchronous code block or a synchronous code block into a variable length code block. Regarding the device.

[0002]

2. Description of the Related Art FIG. 11 shows the structure of a digital VTR recording system. In the digital VTR recording system shown in FIG. 11, a digital video signal to be supplied to an input terminal 1 is recorded by a field shuffling circuit 2. The shuffled and field shuffled digital video signal is converted from a DC component into coefficient data of a high-order AC component by a DCT (discrete cosine transform) circuit 3.

The coefficient data is quantized by a quantization circuit 4, that is, divided by a predetermined quantized coefficient, and the resulting quantized data is encoded by an encoder 5 by a run length or Huffman coding method, for example. The encoded data is coded, and the outer code circuit 6 adds outer parity to the outer code format, and the inner code circuit 7 adds inner parity to the inner code format for synchronization / ID.
After the synchronizing signal and the ID (identification) data are added by the adding circuit 8 to form the product code, the product code is supplied to the recording head 10 through the amplifying circuit 9, and the recording head 10 forms inclined tracks on the magnetic tape. Will be recorded as

Here, the form of the data output from the synchronization / ID addition circuit 8 is, for example, a product code form as shown in FIG. That is, the data of this product code structure is
As shown in FIG. 14, data having a plurality of data strings each including a synchronous SYNC 2 bit, ID data ID 2 bit, data DATA (VLC: variable length code) 162 bits, and parity PARITY (however, inner parity: inner code) 14 bits. , Outer parity OUT (outer code).

Two pieces of data having this product code form data for one track. For example, in the above-mentioned digital VTR, one field has six tracks. The sync code block described later refers to the entire data having the product code configuration shown in FIG.

FIG. 12 shows the digital VTR shown in FIG.
12 shows the structure of a reproducing system for reproducing the data recorded by the recording system of FIG. 12. In the reproducing system of the digital VTR shown in FIG. 12, the recording signal recorded on the magnetic tape 11 is reproduced by the reproducing head 12. The reproduced signal is supplied to the equalizer 14 through the amplifier circuit 13, is equalized in waveform by the equalizer 14 and then converted by the 8/10 conversion circuit 15, and then the synchronous signal is reproduced by the synchronous reproduction circuit 16. It

The signal output from the synchronous reproduction circuit 16 is error-corrected in the inner code error correction circuit 17,
The inner code error correction circuit 17 outputs data and an error flag. The data and the error flag are supplied to the outer code error correction circuit 18, further subjected to error correction processing by the outer code, and then supplied to the decoder 19 where they are decoded. After that, after being inversely quantized by the inverse quantization circuit 20, it is supplied to an IDCT (inverse discrete cosine transform) circuit 21 and is inversely discrete cosine transformed by this IDCT circuit 21.

The output of this IDCT 21 is the field
The data supplied to the shuffling circuit 22 is arranged into the original data array, and further, in the error correction circuit 23, data that cannot be corrected based on the error flag is interpolated with the data of the previous line and not shown via the output terminal 24. It is supplied to other circuits of the digital VTR.

The present applicant arranges coefficient data generated by transform coding such as DCT in order from a low order to a high order, performs variable length coding, and temporally calculates coefficient data of each block. A digital video signal recording apparatus has been proposed in which the length of the sync block is controlled to be constant by moving the end portion (see Japanese Patent Application No. 03-225014).

[0010]

As described above, the digital VTR can compress and record the recording data. In the digital VTR shown in FIG. 11, the DCT circuit 3 is used to convert the image data. Data on the frequency axis is converted, the data on the frequency axis is quantized by the quantization circuit 4, and the encoder 5 performs variable length coding by a method such as run length or Huffman to compress the amount of information. ing.

That is, the image data is converted into variable-length code data of indefinite size based on the amount of information held. In a digital VTR that adopts, for example, a two-dimensional DCT as transform coding, coefficient data is variable-length coded, so the amount of data per block changes depending on the amount of high frequency components in the image. At the time of recording, it is general to form a sync code block (sync block) of a fixed length, but since the sync code block which is a basic unit of data recorded in the VTR has a fixed length, the variable length code data is If the fixed-length data is stored in a memory having a capacity matched, for example, the capacity of the memory of the encoder 5 shown in FIG. 11 has a surplus, or all the data cannot be stored in the memory.

This will be described with reference to FIG.
In FIG. 13, for convenience of explanation, the capacity of the sync code block is 1296 bits. In FIG. 13, Fb is the first bit, Lb is the last bit, V
d indicates a variable length code block. As shown in FIG. 13A, when the variable-length code block Vd is 1296 bits or less, if the data of this variable-length code block Vd is stored in the memory as it is, it corresponds to the data capacity of the synchronous code block as shown in FIG. 13B. Vd in the memory
A surplus portion indicated by 1 is generated.

Further, as shown in FIG. 13C, when the variable length code block Vd is 1296 bits or more, if the data of this variable length code block is stored in the memory as it is, as shown in FIG. In the memory corresponding to the capacity, the data cannot be stored by the capacity indicated by Vd2, and the data is partially lost.

In the digital VTR adopting the information amount compression, it is necessary to control the information amount so that the recorded image is maximized within the recording capacity of the VTR in order to minimize the deterioration of the image quality due to the compression. For that purpose, it is necessary to increase the utilization efficiency of the recording capacity and reduce the amount of information loss, but for the reasons described above, there is a disadvantage that the performance of the digital VTR cannot be fully exhibited. It was

In addition, due to the nature of the variable length code, if there is an error in the data, it is not possible to decode from there. The variable length code block is generally composed of DCT coefficient data of a plurality of image blocks. Figure 1
3E shows an example in which the DCT coefficients of each block are arranged in the variable length code block in the order of blocks.

That is, in FIG. 13E, the variable length code data VLC is converted into variable length code blocks VLC1, VLC2,
It shows a case of being composed of VLC3, VLC4, .... Here, the coefficient in the low frequency band of the DCT coefficient determines the brightness and color of the image, and the coefficient in the high frequency band determines the fine portion of the image. Therefore, when the coefficients in the low frequency band are lost, the influence on the image quality of the image is far greater than when the coefficients in the low frequency band are lost.

Therefore, in the case of the arrangement as shown in FIG. 13E, if a residual data error of the VTR reproduction signal occurs in the variable-length code block VLC4, FIG. 13F.
12, the VLC block VLC4 is provided with the decoder 19, the inverse quantization circuit 20, and the IDCT circuit 21 shown in FIG.
However, there is an inconvenience that the original image cannot be obtained and the reproduced image is deteriorated remarkably because the decoding becomes impossible (indicated by "x" in FIG. 13F).

The present invention has been made in consideration of the above points, and improves the utilization efficiency of the storage capacity of the memory, reduces the amount of loss of image information, and minimizes the image quality deterioration caused by the residual error of the VTR. An attempt is made to propose a digital data storage device which can be suppressed to the limit.

[0019]

The present invention includes first and second aspects.
Storage means 31 for storing the input digital data, and when storing the first input data in the storage means 31, a write address signal that sequentially advances from the minimum write address signal is supplied, and the storage means 31 receives the second input data. When storing the input digital data, contrary to the case where the first input digital data is stored in the storage means 31, a write address generating means for supplying to the storage means 31 a write address signal which sequentially advances from the maximum write address signal. 36, a read address generating means 40 for supplying a read address signal to the storage means 31, and a write for storing the write address signal from the write address generation means 36 at the time when the first input digital data is stored in the storage means 31. Address storage means 37 and a second input digital data Is stored in the storage means 31, it has a comparison means 38 for comparing the write address signal from the write address generation means 36 and the write address signal stored in the write address storage means 37. When the first input digital data is stored and then the second input digital data is stored, the comparison unit 38 causes the write address signal stored in the write address storage unit 37 and the current write address generation unit 36 to operate. The second input digital data is stored in the storage means 31 until the generated write address signals coincide with each other.

The present invention further includes the above first and second aspects.
The respective digital data are variable length code block data, and two synchronous code blocks are generated by storing the first and second digital data in the storage means 31.

Further, according to the present invention, in the above description, the data arrangement in the variable length block is arranged in descending order of importance.

Further, according to the present invention, a storage means 51 for storing the first and second input digital data and the storage means 5 are provided.
When the first input data is stored in 1, the write address signal is sequentially incremented from the minimum write address signal is supplied, and when the second input digital data is stored in the storage unit 51, the first input digital data is stored. Contrary to the case of storing in the storage means 51, a write address generation means 56 for supplying to the storage means 51 a write address signal which sequentially advances from the maximum write address signal,
When reading the first input digital data stored in the storage means 51, a read address signal that sequentially advances from the minimum read address signal is supplied, and the storage means 51 is supplied.
In the case of reading the second input digital data stored in the storage means 51, a read address signal that sequentially advances from the maximum read address signal is supplied to the storage means 51, contrary to the case of reading the first input digital data from the storage means 51. The read address generating means 58 is provided.

Further, the present invention is based on the above description.
The respective digital data are data of the synchronous code block. By storing these first and second digital data in the storage means 51, two variable length code blocks are generated.

[0024]

According to the configuration of the present invention described above, the storage means 31
When the first input digital data is stored in the second input digital data and the second input digital data is stored next, the comparison means 3
At 8, the second input digital data is stored in the storage means 31 until the write address signal stored in the write address storage means 37 and the write address signal currently generated by the write address generation means 36 match.

Further in the above, according to the configuration of the present invention,
When the first and second digital data are data of variable-length code blocks, respectively, the first and second digital data are stored in the storage means 31, thereby generating two synchronous code blocks.

Further in the above, according to the configuration of the present invention,
Arrange the data arrangement in the variable-length block in descending order of importance.

Further, according to the above-described configuration of the present invention, when the first input data is stored in the storage means 51, the write address signal which sequentially advances from the minimum write address signal is supplied, and the second storage means 51 is supplied with the write address signal. In contrast to the case of storing the first input digital data in the storage means 51, the write address signal which sequentially advances from the maximum write address signal is supplied to the storage means 51 when storing the input digital data of First stored in 51
When reading the input digital data of, the read address signal which is sequentially stepped from the minimum read address signal is supplied, and when the second input digital data stored in the storage means 51 is read, the first input digital data is read. Contrary to the reading from the storage means 51, a read address signal that sequentially advances from the maximum read address signal is supplied to the storage means 51.

Further in the above, according to the configuration of the present invention,
When the first and second digital data are data of the synchronous code block, respectively, the first and second digital data are stored in the storage means 51 to generate two variable length code blocks.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the digital data storage device of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 30 denotes variable-length code data Va and V from a variable-length coding circuit or the like (not shown) of the encoder 5 of the digital VTR shown in FIG. 11, for example.
The variable-length code data Va and Vb supplied via the input terminal 30 are stored in the memory 31 by a write address signal from a write address generation circuit 36, which will be described later, and read address, which will be described later. It is read from the memory 31 by the read address signal from the generation circuit 40.

Reference numeral 33 denotes an input terminal to which a switching signal is supplied from, for example, the system controller (or the variable length coding circuit of the encoder 5 or the like) of the digital VTR shown in FIGS. 11 and 12, and via the input terminal 33. Depending on the switching signal supplied, the movable contact 34c of the switch 34 may cause one or the other fixed contact 34a or 3
4b is selectively connected and controlled.

One fixed contact 34a of the switch 34
Is supplied with the write address signal from the write address generation circuit 36, and the other fixed contact 34b of the switch 34 is supplied with the read address signal from the read address generation circuit 40.

Reference numeral 35 denotes, for example, a digital VTR (not shown)
Is an input terminal to which a control signal from the system controller or the like is supplied. Here, this control signal is equal to the lengths of the variable length code data Va and Vb in the time axis direction, for example, it becomes a low level "0" during the period when the variable length code data Va is supplied, and the variable length code High level "1" while the data Vb is being supplied
Becomes

The write address generation circuit 36 is reset to "0" when the control signal is at the low level "0", the increment operation is started from this "0" to generate the write address, and the control signal is at the high level "0". When it is 1 ", the highest value is loaded, for example, and the decrement operation is started from this highest value to issue the write address.

Reference numeral 37 denotes a register which takes in the write address signal from the write address generating circuit 36 when the control signal supplied through the input terminal 35 is low level "0", and the control signal is high level "1", for example. ", The write address signal last fetched is held. The held write address signal is the memory 31 of the last data of the variable length code data Va shown in FIG. 2B.
Is the address in. The final write address of the variable length code data Va held in the register 37 is supplied to the comparator 38.

The comparator 38 supplies a write address signal supplied from the register 37, a write address signal supplied from the write address generation circuit 36, and a control signal supplied from the input terminal 35 when the control signal supplied is low level "0", for example. Compare the central address of the memory 31,
The comparison result is supplied to, for example, the write / read control terminal of the memory 31. The address indicated by the write address signal from the write address generation circuit 36 is ADx, the address indicated by the write address signal supplied from the register 37 is ADy, and the central address of the memory 31 is AD.
When z is set, writing to the memory 31 is controlled as follows according to the comparison result of the comparator 38.

That is, when ADx> ADz, writing of the variable length code data Va and Vb to the memory 31 is permitted, and ADx <ADz and ADx> ADy.
At this time, writing of the variable length code data Va and Vb to the memory 31 is permitted.

As a result, the variable length code data Va and V
Even if the data amount of b is different, the mutual data is stored in the memory 31.
You can remember without eroding in.

Reference numeral 39 is supplied from a system controller of a digital VTR (not shown) or the like, and corresponds to the length of the sync code block data (hereinafter simply referred to as sync code data) in the time axis direction, for example, low level "0", This is an input terminal for inputting a control signal of high level “1”.
While the control signal is at the low level “0”, the read address generation circuit 40 is reset to “0”,
After that, the increment operation is started to generate the read address. When the control signal is at the high level "1", the maximum value is loaded, and thereafter the decrement operation is started to generate the read address.

Next, the operation of the digital data storage device shown in FIG. 1 will be described with reference to the timing chart of FIG.

The input terminal 30 is supplied with the variable length code data Va and Vb shown in FIG. 2B, and the input terminal 33 is shown in FIG.
The switching signal shown in A is supplied. In the case of writing, the switching signal becomes low level "0", and at this time, the movable contact 34c of the switch 34 is connected to the fixed contact 34a. On the other hand, the control signal shown in FIG. 2C is supplied to the write address generation circuit 36, the register 37, and the comparator 38 via the input terminal 35.

The write address generation circuit 36 is reset to "0" when the control signal becomes low level "0", and then starts the increment operation as shown in FIG. 2D. The write address signal is supplied to one fixed contact 34a of the switch 34, the register 37, and the comparator 38, respectively.

The write address signal from the write address generating circuit 36 supplied to the fixed contact 34a of the switch 34 is supplied to the memory 31 via the movable contact 34c of the switch 34. As a result, the variable length code data Va shown in FIG. 2B is sequentially stored from the area corresponding to the lowest address of the memory 31 to the area of the higher address.

On the other hand, when the control signal shown in FIG. 2C is switched from the low level "0" to the high level "1", the register 37 holds the last supplied write address signal. Comparator 3
Continue to supply. In addition, the write address generation circuit 3
6 is loaded with the highest value, and thereafter, as shown in FIG. 2D,
The decrement operation is started, and the write address signals obtained thereby are supplied to the memory 31 via the comparator 38 and the switch 34, respectively.

Then, as shown in FIG. 2B, the variable length code data Vb is sequentially stored from the area corresponding to the highest address to the area corresponding to the lowest address of the memory 31. At the same time, the comparator 38 outputs the write address signal from the write address generation circuit 36 and the write address signal from the register 37 (variable length code data V
a signal indicating the address of the memory 31 in which the last data of a is stored) and the central address of the memory 31 are compared, and the variable length code data Va on the memory 31 is compared with the variable length code data Vb. Control to prevent erosion (or so-called overwriting). Thereby, the variable length code data Va and Vb of the two variable length code blocks having different data amounts can be satisfactorily stored in the memory 31 without eroding each other's data.

Now, in the case of reading, FIG.
As shown in, when the switching signal supplied to the switch 34 changes from low level “0” to high level “1”,
The movable contact 34c of the switch 34 is the other fixed contact 34b
The read address signal from the read address generating circuit 40 is connected to the memory 3 via the switch 34.
1 will be supplied.

Variable-length code data V from this memory 31
In the read period of a and Vb, first, as shown in FIG. 2E, the control signal supplied via the input terminal 39 becomes low level “0”, and in this case, the read address generation circuit 40 is reset to “0”. After that, the increment operation is started as shown in FIG. 2F, and the read address signal is supplied to the memory 31 via the switch 34.

The read address generation circuit 40 generates a read address signal and also detects whether or not the generated read address reaches the central address of the memory 31 by the control signal shown in FIG. 2E. When detecting that the read address has reached the central address of the memory 31, the read address generation circuit 40 starts the decrement operation after the highest value is loaded and supplies the read address signal to the memory 31 via the switch 34. .

Therefore, as shown in FIG. 2G, the memory 31
The variable length code data Va and Vb stored in the memory are read as the sync code data SYa and SYb of the sync code block. In this example, the case where the data amount of the variable length code data Va is larger than the data amount of the variable length code data Vb is described (the length on the time axis is different in FIG. 2B). The variable-length code data Va and Vb of two variable-length code blocks having different data amounts are the same as each other (the lengths on the time axis are the same in FIG. 2G). As is clear from the above description, it is possible to output as SYb by synchronizing a part of the variable length code data Va of the variable length code block having a large amount of data with a part of the variable length code data Vb of the variable length code block. This is because the synchronous code block data SYb of the code block is read.

Now, the above-mentioned processing will be further described with reference to FIGS.

FIG. 5 shows a case where the total data amount is 2592 bits or less and the data amount of the variable length code data Va is larger than that of the variable length code data Vb. In FIG. 5A, solid line arrows indicate the writing directions for writing the variable-length code data Va and Vb from the first bit Fb to the last bit Lb, respectively. Also,
In FIG. 5A, Va1 indicates the amount of data that exceeds half the capacity of the memory 31 (for example, 1296 bits) among all the data of the variable length code data Va. The number of 2592 bits means that one sync code block has 162 words, that is, two sync code blocks have 16 bits.
From 2 × 8 × 2, the total data amount is 2592 bits.

As shown in FIGS. 5A and 5B, when the data amount of the variable length code data Va exceeds 1/2 of the capacity of the memory 31, the variable length code data Va shown in FIG.
The first bit Fb to the last bit Lb are stored in the memory 31 shown in FIG. 3 in the direction indicated by the solid line arrow. Further, the last bit Lb of the variable length code data Va is followed by the variable length code data Vb shown in FIG. 5B. The first bit Fb to the last bit Lb are stored in the order indicated by the solid arrow.

After being stored in this way, FIGS.
, The sync code data SY of the sync code block
It is read with a fixed length as a and SYb. At the time of reading, since the variable-length code data SYa and SYb are set at the central address of the memory 31, a part Va1 of the variable-length code data Va is synchronized with the variable-length code data Vb as shown in FIG. 5D. The synchronous code data SYb of the code block is read in the direction indicated by the solid line arrow.
At this time, as shown in FIG. 5D, as the sync code data SYb of the sync code block, first, the variable length code data Vb is the first bit Fb as shown by the solid arrow.
From the last bit Lb to the last bit, and then a part Va1 of the variable-length code data Va is read from the last bit Lb to the end as indicated by the solid arrow.

The data amount of the variable length code data Vb is 1
This includes a case where the total data amount is 259 bits or more and the total data amount is within 2592 bits, and a case where the two variable length code data Va and Vb are both 1296 bits or less.

FIG. 6 shows that the total data amount is 2592 bits or more,
In addition, the case where the data amount of the variable length code data Vb is 1296 bits or less and the data amount of the variable length code data Va is larger than the data amount of the variable length code data Vb is shown. In FIG. 6A, the solid line arrows indicate the writing directions for writing the variable length code data Va and Vb from the first bit Fb to the last bit Lb, respectively. Further, in FIG. 6A, Va1 and Va2 represent data that exceeds half (for example, 1296 bits) of the capacity of the memory 31 among all the data of the variable length code data Va.

That is, as shown in FIGS. 6A and 6B, the data amount of the variable length code data Va is 1 / the capacity of the memory 31.
If it exceeds 2, the variable length code data V shown in FIG. 6A
In the memory 31 shown in FIG. 1A, the first bit Fb to the end of Va1 are stored as indicated by the solid arrow. That is, the variable length code data Va2 shown in FIG. 6A is not stored in the memory 31. Further, following the last bit Lb of the variable length code data Va, the variable length code data Vb shown in FIG. 6B is stored in order from the first bit Fb to the last bit Lb as shown by the solid arrow.

After being stored in this way, FIGS. 6C and 6D are shown.
, The sync code data SY of the sync code block
As a and SYb, they are read out in a fixed length as shown by solid arrows. At the time of reading, since the variable-length code data SYa and SYb are set with the central address of the memory 31 as a boundary, as shown in FIG.
A part Va1 of a is read together with the variable length code data Vb as the sync code data SYb of the sync code block in the direction indicated by the solid arrow. At this time, as shown in FIG. 6D, as the sync code data SYb of the sync code block, first, the variable-length code data Vb is read out in order from the first bit Fb to the last bit Lb as indicated by the solid line arrow. Then, a part Va of the variable-length code data Va
1 is read up to the last bit Lb as indicated by the solid arrow.

The case where the total data amount is 2592 bits or more and the data amount of the variable length code data Va is 1296 bits or less is also included. Further, the variable code data Va2 shown in FIG. 6A can be prevented from being stored in the memory 31 because, for example, the control signal from the variable code encoder circuit or the system controller at the next stage of the circuit shown in FIG. This is because writing is controlled by FIG. 2C).

FIG. 7 shows a case where each data amount of the variable length code data Va and Vb is 1296 bits or more. In FIG. 7A, solid line arrows indicate the writing directions when writing the variable length code data Va and Vb from the first bit Fb to the last bit Lb, respectively.
7A and 7B, Va1 and Vb1 are the memory 3 of the variable length code data Va and Vb, respectively.
Data that exceeds half the capacity of 1 (for example, 1296 bits) is shown.

That is, as shown in FIGS. 7A and 7B, when the data amount of the variable length code data Va and Vb exceeds 1/2 of the capacity of the memory 31, respectively, the variable length code data Va shown in FIG. In the memory 31 shown in FIG. 1, the first bit Fb to the front of Va1 are stored in the direction indicated by the solid arrow. That is, the variable length code data Va1 shown in FIG. 7A is not stored in the memory 31. Further, the variable-length code data Va is followed by the variable-length code data Vb shown in FIG. 7B as indicated by a solid line arrow Fb.
To Vb1 are stored. That is, the variable length code data Vb1 shown in FIG. 7B is not stored in the memory 31.

After being stored in this way, FIGS.
, The sync code data SY of the sync code block
It is read as a and SYb with a fixed length in the direction indicated by the solid arrow. At the time of reading, the variable-length code data SYa and SYb are set at the center address of the memory 31, but in this case, the variable-length code data Va and Vb are already equal at the center address of the memory 31. Since it is stored in the synchronous code block, the synchronous code data SYa and SYb of the synchronous code block are read as they are in the direction indicated by the solid arrow.

As described above, all the states caused by the magnitude relation of the two variable-length code blocks are roughly divided into three states, and by clearing them, all states can be dealt with. Further, the boundary position of the variable length code block can be known by decoding the variable length code until a predetermined number of data is obtained. Therefore, it is not necessary to include the information indicating the boundary position of the variable length code block in the sync code block, which is efficient.

Here, the operation of the digital data storage device shown in FIG. 1 will be further described with reference to FIG.

As shown in FIGS. 9A and 9B, the data length of the variable length code data Va is larger than 1296 bits (1/2 + Va1 of the capacity of the memory 31 of 2592 bits), and the data length of the variable length code data Vb is 1296 bits. 9C, the variable-length code data Va from the first bit Fb to the last bit Lb are stored in the memory 31 in the order from the low address Lad to the high address Had as indicated by the solid line arrow in FIG. 9C.
Are stored in this order. The variable-length code data Vb is transferred from the first bit Fb to the last bit L in the order of the highest value address Had to the lowest address Lad of the memory 31.
It is stored in the order of b. In FIG. 9C, Ac represents the central address of the memory 31.

At the time of reading, a part of the variable length code data Va is sequentially read from the first bit Fb to the position of the central address Ac shown in FIG. 9C, as shown by the solid line arrow in FIG. 9D. And is output as the synchronous code data SYa of the synchronous code block.

Then, as shown by a solid arrow in FIG. 9E, the variable length code data Vb is the first bit Fb.
To the last bit Lb, the part Va1 of the variable-length code data Va shown in FIG. 9A is read from the last bit Lb to the end. As a result, the two variable length code data Va and Vb are converted into the sync code data SYa and SYb of the two sync code blocks.

Before and after the description, the method of arranging the DCT count will be described with reference to FIG.

The image data is as shown in FIG.
The DCT circuit 3 shown in FIG.
Converted to coefficient data. In the example of FIG. 8, as shown in FIG. 8B, one DCT block DCT1, DCT2,
It is assumed that each of DCT3, DCT4, DCT5, ... Has been converted into five DCT coefficients. That is, the DCT block DCT1 is converted into DCT coefficients a0 to a4, and D
The CT block DCT2 is converted into DCT coefficients b0 to b4, the DCT block DCT3 is converted into DCT coefficients c0 to c4, and the DCT block DCT4 is converted into DCT coefficients d0 to d4.
It is converted into d4, and the DCT block DCT5 is converted into DCT coefficients e0 to e4. Further, the DCT coefficient “0” is DC data, and becomes high frequency data as the number increases.

Next, when performing variable length coding, as shown in FIG. 8C, each DCT block DCT1, DCT2, DCT3, DCT4, DCT is placed at the beginning of the variable length code block.
5, ... DC data (a0, b0, c0, d0,
e0 ... ・) are arranged below, and a1, b1, c1, d
1, e1, ..., a2, b2, c2, d2, e2,
..., a3, b3, c3, d3, e3, ...
Arranged as a4, b4, c4, d4, e4, ....

When the variable length code data having such a data array is recorded and reproduced, even if a residual data error of the reproduced signal occurs at the position of the DCT coefficient a2 in FIG. 8C, DCT coefficients a0, b0, c0, d0, e which are the basic components of the image
0, ..., a1, b1, c1, d1, e1, ...
・ Since the data of can be reproduced, the reproduced image can be avoided from being completely destroyed. This is because, as described above, the data having a lower frequency has a larger influence on the image quality, and the data having a higher frequency has a smaller influence on the image quality.

As shown in FIG. 11, an error correction code is used in the digital VTR. However, since an error remains from this, the use of the above-mentioned data array has a minimal effect on the image quality. Can be limited.

Next, referring to FIG. 3, a case where the digital data storage device is applied to the reproducing system decoder 19 of the digital VTR shown in FIG. 12, for example, will be described.

In the figure, reference numeral 50 indicates output data from the outer code error correction circuit 18 shown in FIG. 12, for example, the sync code data SYa and SY of the above-mentioned sync code block.
b is an input terminal, 53 is an input terminal to which a switching signal from a system controller or the like of a digital VTR (not shown) is supplied, and 55 is an input terminal to which a control signal from a system controller or the like is similarly supplied,
Reference numeral 52 is an output terminal from which data read from the memory 51, that is, variable length code data is output, and 57 is an input terminal to which a control signal from a system controller (not shown) or the like is supplied.

Reference numeral 54 is a switch, and its movable contact 54 is moved by a switching signal supplied through the input terminal 53.
c is controlled to be selectively connected to the fixed contact 54a or 54b. The write address generation circuit 56 is reset to "0" when the control signal supplied to the input terminal 55 is, for example, low level "0", and then starts the increment operation to obtain the write address signal and switches it. It is supplied to the memory 51 via 54, and the maximum value is loaded when the control signal becomes the high level “1”. After that, the decrement operation is started to obtain the write address signal, and this is sent to the memory 51 via the switch 54. Supply.

The read address generation circuit 58 is reset to "0" when the control signal supplied to the input terminal 57 is, for example, low level "0", and then starts the increment operation to obtain the read address signal. Is supplied to the memory 31 via the switch 54, and the maximum value is loaded when the control signal becomes the high level “1”. After that, the decrement operation is started to obtain the read address signal, and this is sent to the memory 31 via the switch 54. Supply to 51.

Next, the operation of the digital data storage device shown in FIG. 3 will be described with reference to the timing chart of FIG.

First, the synchronous code data SYa and SYb shown in FIG. 4B are supplied to the input terminal 50, and the input terminal 53.
Is supplied with the switching signal shown in FIG. 4A. In the case of writing, the switching signal becomes low level “0”, and at this time, the movable contact 54 of the switch 54
c is connected to the fixed contact 54a. On the other hand, the control signals shown in FIG. 4C are supplied to the write address generation circuit 56 via the input terminal 55.

The write address generation circuit 56 is reset to "0" when the control signal becomes the low level "0", and thereafter the increment operation is started as shown in FIG. The write address signal is supplied to one fixed contact 54a of the switch 54.

The write address signal from the write address generating circuit 56 supplied to the fixed contact 54a of the switch 54 is supplied to the memory 51 via the movable contact 54c of the switch 54. As a result, the synchronous code data SYa shown in FIG. 4B is sequentially stored from the area corresponding to the lowest address of the memory 51 to the area of the higher address.

On the other hand, when the control signal shown in FIG. 4C switches from the low level "0" to the high level "1", the highest value is loaded into the write address generation circuit 36, and the write address generation circuit 36 thereafter As shown in FIG. 4D, the decrement operation is started, and the write address signals obtained thereby are supplied to the memory 51 via the switch 54, respectively.

Then, as shown in FIG. 4B, the synchronous code data SYb is sequentially stored from the area corresponding to the highest address to the area corresponding to the lowest address of the memory 51.

Now, in the case of reading, FIG.
When the switching signal supplied to the switch 54 changes from low level “0” to high level “1” as shown in
The movable contact 54c of the switch 54 is the other fixed contact 54b.
The read address signal from the read address generating circuit 58 is connected to the memory 5 via the switch 54.
1 will be supplied.

Synchronous code data SY from this memory 51
In the read period of a and SYb, first, as shown in FIG. 4E, the control signal supplied through the input terminal 57 becomes low level “0”, and in this case, the read address generation circuit 58 is reset to “0”. After that, the increment operation is started as shown in FIG. 4F, and the read address signal is supplied to the memory 51 via the switch 54.

The read address generation circuit 58 generates a read address signal and also detects whether or not the read address generated has reached the central address of the memory 51 by the control signal shown in FIG. 4E. When detecting that the read address has reached the central address of the memory 51, the read address generation circuit 58 starts the decrement operation after the highest value is loaded and supplies the read address signal to the memory 51 via the switch 54. .

Therefore, as shown in FIG. 4G, the memory 51
The synchronous code data SYa and SYb stored in the above are read as the variable length code data Va and Vb of the variable length code block. In this example, the case where the data amount of the variable length code data Va is larger than the data amount of the variable length code data Vb is described (the length on the time axis is different in FIG. 4G).

The variable length code data Va and Vb having different data amounts can be obtained from the sync code data SYa and SYb of the sync code blocks having the same data amount.
This is because, although not shown, a variable length coding circuit or the like is connected to the next stage of the memory 51. The position of the last data of the variable length code data Va can be detected by counting the number of codes decoded by the variable length coding circuit. That is, it is possible to detect the address data at the delimiter between the variable length code data Va and Vb.
This is the source of the control signal supplied to the read address generation circuit 40 via the input terminal 39 described above.

The operation of the digital data storage device shown in FIG. 3 will be further described with reference to FIG.

As shown in FIGS. 10A and 10B, the sync code data SYa is the variable length code data Va and the sync code data S.
Yb is variable length code data Vb and variable length code data Va
10C, the variable-length code data Va and the partial Va1 of the variable-length code data Va, as shown in FIG. 10C.
Must be continuously output, and then the variable length code data Vb must be output. In FIG. 10C, Ac represents the central address of the memory 31.

When the above-mentioned processing is carried out, as shown by the solid line arrow in FIG. 10D, first, the synchronous code data SYa.
(The variable length code data Va1 is not included) is stored in the memory 51 in the order from the low address Lad to the high address Had, and in the order from the first bit Fb to the last bit Lb. Then, as indicated by the solid arrow, the address Had from the highest value of the memory 51 to the lower address Lad
Of the sync code data SYb, the data corresponding to the variable length code data Vb is stored in order from the first bit Fb to the last bit Lb, and the variable length code data Va1 is stored.
The data corresponding to is stored from the last bit Lb to the end.

At the time of reading, as shown by the solid line arrow in FIG. 10E, the variable-length code data Va is sequentially read from the first bit Fb, and is a part of the synchronous code data SYb. The long code data Va1 is also output, and these are output as variable-length code data Va.

Then, as shown by a solid arrow in FIG. 10F, the variable length code data Vb is the first bit F.
The bits from b to the last bit Lb are read. As a result, the two sync code data SYa and SYb are converted into two variable length code data Va and Vb.

As described above, in this example, the variable length code data Va and Vb are stored in the memory 31 on the encoder side.
When storing the variable length code data Va in the memory 51, the variable length code data Va is sequentially stored from the lower address of the memory 51 to the higher address, and the variable length code data Vb is sequentially stored from the higher address of the memory to the lower address. The address from the register 37, the write address from the write address generation circuit 36, and the central address are compared with each other. When the write address is larger than the central address, the write address is smaller than the central address, and the write address is the register. Only when it is larger than the address from 37, the variable-length code data Vb is written to the memory 31, and at the time of reading, the variable-length code data read from the lower address to the central address is set as the synchronization code data SYa. Read to the center address Synchronization code data S a-length encoded data
Since the data is output as Yb, the conversion from the variable length code data to the synchronous code data is simplified, the utilization efficiency of the storage capacity is improved, the configuration can be simplified, and the loss amount of image information is minimized. be able to.

Further, in this example, when storing the synchronous code data SYa and SYb on the decoder side in the memory 51, the synchronous code data SYa is stored in order from the lower address of the memory 51 to the higher address. Data S
Yb is sequentially stored from the higher address to the lower address of the memory, and at the time of reading, the data read from the low address to the end of the variable length code data Va is set as the variable length code data Va, and the variable of the highest value is changed to the variable length. Since the data read to the end of the code data Vb is output as the variable-length code data Vb, the variable-length code data can be obtained from the synchronous code data generated on the encoder side, and the utilization efficiency of the storage capacity is improved. Thus, the configuration can be simplified and the amount of missing image information can be minimized.

In the above example, the digital VTR
However, as long as the variable-length code is used, the same effect as described above can be obtained even if the present invention is applied to any device including a compression unit such as a high-efficiency coding device.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0096]

According to the present invention described above, when the first input digital data is stored in the storage means and then the second input digital data is stored in the storage means, the write address storage means is provided in the comparison means. Since the second input digital data is stored in the storage means until the write address signal stored in 1 and the write address signal currently generated by the write address generation means match.
It is possible to improve the utilization efficiency of the storage capacity of the memory and reduce the amount of missing information.

Further, according to the present invention described above, when the first and second digital data are data of the variable length code block, respectively, by storing these first and second digital data in the storage means, Since two sync code blocks are generated, it is possible to generate the sync code blocks with a simple configuration in addition to the above effects.

Further, according to the configuration of the present invention described above,
Since the data arrays in the variable-length block are arranged in descending order of importance, in addition to the above effects, for example, V
When applied to a TR or the like, it is possible to minimize the image quality deterioration caused by the residual error of the VTR.

Further, according to the present invention described above, when the first input data is stored in the storage means, the write address signal which is sequentially stepped from the minimum write address signal is supplied, and the second input digital data is supplied to the storage means. In contrast to the case where the first input digital data is stored in the storage means, a write address signal that sequentially advances from the maximum write address signal is supplied to the storage means, and the first stored in the storage means. When reading the input digital data, a read address signal that sequentially advances from the minimum read address signal is supplied, and when reading the second input digital data stored in the storage means,
On the contrary to the case of reading the first input digital data from the storage means, the read address signal which sequentially advances from the maximum read address signal is supplied to the storage means, so that the utilization efficiency of the storage capacity of the memory is improved. , It is possible to reduce the amount of missing information.

Further, according to the present invention described above, when the first and second digital data are data of the synchronous code block, respectively, by storing these first and second digital data in the storage means, two Since the variable-length code block is generated, the variable-length code block can be generated with a simple configuration in addition to the above effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital data storage device of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 3 is a block diagram showing an embodiment of a digital data storage device of the present invention.

FIG. 4 is a timing chart for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 5 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 6 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 7 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 8 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 9 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 10 is an explanatory diagram for explaining the operation of one embodiment of the digital data storage device of the present invention.

FIG. 11 is a configuration diagram showing an example of a recording system of a digital VTR.

FIG. 12 is a configuration diagram showing an example of a reproduction system of a digital VTR.

FIG. 13 is an explanatory diagram for explaining the operation of the conventional digital data storage device.

FIG. 14 is an explanatory diagram showing the structure of a product code.

[Explanation of symbols]

 31, 51 Memory 36, 56 Write address generation circuit 40, 58 Read address generation circuit 37 Register 38 Comparator

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[Procedure amendment]

[Submission date] September 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The comparator 38 is a write address signal supplied from the register 37, a write address signal supplied from the write address generation circuit 36 and a memory when the control signal supplied via the input terminal 35 is at the high level "1". The central address of 31 is compared, and the comparison result is supplied to, for example, the write / read control terminal of the memory 31. When the address indicated by the write address signal from the write address generation circuit 36 is ADx, the address indicated by the write address signal supplied from the register 37 is ADy, and the central address of the memory 31 is ADz, the comparison result of the comparator 38 indicates that Writing to the memory 31 is controlled as follows.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

[0037] That is, ADx> writing variable length code data V b to the memory 31 when the ADz is allowed, also the writing to the memory 31 of the variable length code data Vb when ADx <ADz and ADx> ADy Allowed Note that Va is controlled by the comparator 38.
All data is written in the memory 31 without any need.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

As a result, the variable length code data Va and V
Even if the data amount of b is different, the variable length code data Va and V
When the sum of the data amount of b is smaller than the capacity of the memory 31
In addition, mutual data can be stored in the memory 31 without being eroded.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

Then, as shown in FIG. 2B, the variable length code data Vb is sequentially stored from the area corresponding to the highest address to the area corresponding to the lowest address of the memory 31. At the same time, the comparator 38 outputs the write address signal from the write address generation circuit 36 and the write address signal from the register 37 (variable length code data V
a signal indicating the address of the memory 31 in which the last data of a is stored) and the central address of the memory 31 are compared, and the variable length code data Va on the memory 31 is compared with the variable length code data Vb. Control to prevent erosion (or so-called overwriting). As a result, the variable-length code data Va and Vb of the two variable-length code blocks having different data amounts are converted into the data of the variable-length code data Va and Vb.
If the sum of the data amounts is smaller than the capacity of the memory 31, the data can be satisfactorily stored in the memory 31 without eroding each other's data.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0058

[Correction method] Change

[Correction content]

The case where the total data amount is 2592 bits or more and the data amount of the variable length code data Va is 1296 bits or less is also included. Further, the variable length code data Va2 shown in FIG. 6A can be prevented from being stored in the memory 31.
Whether writing is controlled by the comparator 38 in FIG.
It is.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0067

[Correction method] Change

[Correction content]

[0067] Description may be around, but will now be described with reference to FIG. 8 the arrangement method of the DCT coefficients.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0080

[Correction method] Change

[Correction content]

[0080] On the other hand, when the control signal shown in FIG. 4C is switched from the low level "0" to high level "1", the maximum value is loaded in the write address generator circuit 5 6, the write address generating circuit 5 6 or later 4D, the decrement operation is started, and the write address signals obtained thereby are supplied to the memory 51 via the switch 54, respectively.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0084

[Correction method] Change

[Correction content]

The read address generation circuit 58 generates a read address signal, and also detects whether the generated read address reaches the address on the boundary between Va and Vb by the control signal shown in FIG. 4E. When detecting that the read address reaches the address on the boundary between Va and Vb , the read address generation circuit 58 starts the decrement operation after the maximum value is loaded and supplies the read address signal to the memory 51 via the switch 54. To do.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0086

[Correction method] Change

[Correction content]

The variable length code data Va and Vb having different data amounts can be obtained from the sync code data SYa and SYb of the sync code blocks having the same data amount.
This is because, although not shown, a variable length coding circuit or the like is connected to the next stage of the memory 51. The position of the last data of the variable length code data Va can be detected by counting the number of codes decoded by the variable length coding circuit. That is, it is possible to detect the address data at the delimiter between the variable length code data Va and Vb.
This is the control signal supplied to the read address generating circuit 58 through the input terminal 57 described above.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0089

[Correction method] Change

[Correction content]

In order to carry out the above-mentioned processing, as shown by the solid line arrow in FIG.
a (not including the variable length code data Va1) is the memory 51
Are stored in order from the lowest address Lad to the highest address Had, and from the first bit Fb to the last bit Lb. Then, as indicated by the solid arrow, the address Had from the highest value of the memory 51 to the lower address Lad
Of the sync code data SYb, the data corresponding to the variable length code data Vb is stored in order from the first bit Fb to the last bit Lb, and the variable length code data Va1 is stored.
The data corresponding to is stored from the last bit Lb to the end.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0092

[Correction method] Change

[Correction content]

As described above, in this example, the variable length code data Va and Vb are stored in the memory 31 on the encoder side.
When storing the variable length code data Va, the variable length code data Va is sequentially stored from the lower address of the memory 31 to the higher address, and the variable length code data Vb is sequentially stored from the higher address of the memory to the lower address. At 38, the address from the register 37, the write address from the write address generation circuit 36, and the central address are compared. If the write address is larger than the central address, and if the write address is smaller than the central address and the write address is Only when it is larger than the address from the register 37, the variable length code data Vb is written to the memory 31, and at the time of reading, the variable length code data read from the low address to the central address is set as the synchronization code data SYa, and the address of the highest value is set. To the central address The variable length code data is converted to the sync code data S.
Since it is output as Yb, the conversion from the variable length code data to the synchronous code data is simplified, the utilization efficiency of the storage capacity is improved, the configuration can be simplified, and the loss amount of image information is minimized. be able to.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/133 Z

Claims (5)

[Claims] 1. A storage means for storing first and second input digital data, and a write address signal which sequentially advances from a minimum write address signal when storing the first input data in the storage means. However, when the second input digital data is stored in the storage means, a write address signal is sequentially incremented from the maximum write address signal, contrary to the case where the first input digital data is stored in the storage means. To the storage means, read address generation means for supplying a read address signal to the storage means, and write address generation at the time when the first input digital data is stored in the storage means. Write address storage means for storing a write address signal from the means, It has a comparing means for comparing the write address signal from the write address generating means and the write address signal stored in the write address storing means when the second input digital data is stored in the storing means. When the first input digital data is stored in the storage means and then the second input digital data is stored in the storage means, the write address signal stored in the write address storage means is stored in the comparison means. A digital data storage device, characterized in that the second input digital data is stored in the storage means until the write address signals currently generated by the write address generation means coincide with each other. 2. The first and second digital data are data of a variable length code block, respectively, and two synchronous code blocks are stored by storing the first and second digital data in the storage means. The digital data storage device according to claim 1, wherein the digital data storage device is generated. 3. The digital data storage device according to claim 2, wherein the data arrays in the variable-length blocks are arranged in descending order of importance. 4. A storage means for storing first and second input digital data, and a write address signal which sequentially advances from a minimum write address signal when storing the first input data in the storage means. However, when the second input digital data is stored in the storage means, the write address signal is sequentially stepped from the maximum write address signal, contrary to the case where the first input digital data is stored in the storage means. To the storage means, and when reading the first input digital data stored in the storage means, a read address signal that sequentially advances from the smallest read address signal is supplied to the storage means. When reading the above-mentioned second input digital data stored in Digital data storage device characterized by having a read address generating means for supplying a read address signal sequentially incrementing from the maximum of the read address signal back to said storage means and when reading Rudeta from the storage means. 5. The first and second digital data are data of a synchronous code block, respectively, and two variable-length code blocks are stored by storing the first and second digital data in the storage means. The digital data storage device according to claim 4, wherein the digital data storage device is generated.