JP3186324B2 - Quantization level calculation method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital VT
The present invention relates to a quantization level calculation method and apparatus suitable for application to a quantization device such as R or a high-efficiency coding device.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a recording system of a digital VTR. In a reproducing system of the digital VTR shown in FIG. 5, a digital video signal to be recorded supplied to an input terminal 1 is supplied to a field shuffling circuit 2. The shuffled and field shuffled digital video signals are converted from DC components into higher order AC component coefficient data by a DCT (Discrete Cosine Transform) circuit 3, and the coefficient data is quantized by a quantization circuit 4, that is, a predetermined value is obtained. , And the resulting quantized data is encoded by an encoder 5. The encoded data is added with an outer code by an outer code circuit 6, and is further encoded by an inner code circuit 7. Is added to form a product code, and this data is synchronized /
After the synchronization signal and the ID (identification) data are added by the ID adding circuit 8, it is supplied to the recording head 10 via the amplifier circuit 9, and is recorded by the recording head 10 so as to form an inclined track on the magnetic tape.

FIG. 6 shows a configuration of a reproducing system for reproducing data recorded by the recording system of the digital VTR shown in FIG. 5. In the reproducing system of the digital VTR shown in FIG. The recorded signal recorded is reproduced by the reproducing head 12, and the reproduced signal is amplified by the amplifier circuit 1.
3 and supplied to the equalizer 14 via the equalizer 14, where the waveform is equalized by the equalizer 14 and the 8/10 conversion circuit 15
After that, the synchronous signal is reproduced by the synchronous reproducing circuit 16.

The signal output from the synchronous reproduction circuit 16 is subjected to error correction in an inner code error correction circuit 17,
The inner code error correction circuit 17 outputs data and an error flag. The data and the error flag are supplied to an outer code error correction circuit 18, subjected to an error correction process using an outer code, supplied to a decoder 19, and decoded by the decoder 19. Then, after being inversely quantized by the inverse quantization circuit 20, it is supplied to an IDCT (inverse discrete cosine transform) circuit 21, which performs inverse discrete cosine transform.

The output of the IDCT 21 is
The data is supplied to the shuffling circuit 22 and is arranged in the original data. Further, in the error correction circuit 23, data that cannot be corrected based on the error flag is interpolated by the data of the previous line and is not shown via the output terminal 24. It is supplied to other circuits of the digital VTR.

Here, an internal configuration of the quantization circuit 4 of the recording system shown in FIG. 5 will be described. The digital VTR has a much larger data amount than the analog VTR.
Therefore, in the related art, it is considered that data is compressed and recorded. In the example of FIG. 5, the DCT circuit 4 performs discrete cosine transform to convert digital video data into coefficient data from a DC component to a high-order AC component. The data is further compressed in a quantization circuit 4 based on a quantization level to be described later and encoded by an encoder 5.

[0007] The quantization circuit 4 shown in FIG. 5 is constituted by a buffering circuit. FIG. 7 shows the configuration of this buffering circuit.

That is, as shown in FIG. 7, the buffering circuit quantizes the component video signal (Y: luminance signal, C: chroma signal) sampled at the sampling frequency (27 MHz) in units of equal length. , Seven binary search circuits 38, 39, 40, 41, 42, 43 and 4 for correcting the quantization level from the code amount prediction.
4, a back search circuit 46 for determining a quantization level based on, for example, distortion during dubbing, a quantization circuit 47 for performing quantization, and an AC / DC shuffling for rearranging AC coefficients and DC coefficients. And a circuit 52.

DC limit value data from a VTR system controller (not shown) is supplied to the binary search circuits 38 to 44 via input terminals D1 to D7, respectively, and a VTR (not shown) is supplied via input terminals T1 to T7, respectively.
A test signal is supplied from the system controller.

[0010] A binary search circuit 38 is connected to input terminals 36 and 37 via a DCT circuit 3 as shown in FIG.
6-bit (4 × 4) input data (video data) and a synchronization signal are supplied. As shown in FIG. 9, input data ID data ID1, ID data ID2, header de <br/> over data Hd1, header data Hd2, video data (luminance signals Y1, · · · · color difference signals B-Y5 , Luminance signal Y1
1,..., Luminance signal Y20, color difference signal RY6, color difference signal BY6,.

[0011] 2 clocks counted from ID data ID1 and ID2 synchronization signal, the header data Hd1 and Hd2 corresponding to the next two clocks subsequent 640 clock DC
It corresponds to the T-converted video data. The ID data ID1 and ID2, header data Hd1 and DCT blocks your capital to 40 block is followed by H d 2.

The input data shown in FIG. 9 is supplied to the back search circuit 46 through the binary search circuits 38 to 44. The back search circuit 46 has input terminals T8 and T4.
5, a test signal and a back search on / off signal from a system controller of a VTR (not shown) are supplied. That is, the back search circuit 46 detects the distortion at the time of dubbing based on the video data from the final stage binary search circuit 44 and the back search on / off signal,
The quantization level is corrected based on the distortion.

The quantization circuit 47 has input terminals D9 and T9.
, DC limit value data and a test signal are supplied. The quantization circuit 47 quantizes the video data based on the quantization level from the back search circuit 46, and outputs maximum quantization level data, intermediate quantization level data, minimum quantization level data via output terminals 48, 49 and 50. The quantization level data is supplied to a VTR system controller (not shown).

The output of the quantization circuit 47 is as shown in FIG. As shown in FIG. 10, the quantization circuit 47
Is the same as the input data shown in FIG. 9, but after the quantization, EOB (end of block ) is added to the 13 bits of DCT-converted video data.

The quantized data shown in FIG. 10 is supplied to an AC / DC shuffling circuit 52. The AC / DC shuffling circuit 52 is supplied with a 525/625 select signal for distinguishing between video signals (for example, NTSC system and PAL system) via the input terminal 51. The AC / DC shuffling circuit 52 rearranges the quantized data from the quantizing circuit 47 into alternating current and direct current.

FIG. 11 shows output data of the AC / DC shuffling circuit 52. As shown in FIG.
The output data has an arrangement in which the direct current and the alternating current are clearly separated, and the equal length unit is two sinks.

Next, the binary search circuits 38 to
The internal configuration of 44 will be described with reference to FIG.

In the figure, 55 and 59 indicate input terminals of the binary search circuits 38 to 44 explained in FIG.
Video data is supplied to the input terminal 55, and a synchronization signal is supplied to the input terminal 59.

The video data supplied through an input terminal 55 is supplied to and stored in a FIFO (first-in-first-out) memory 56, and is also supplied to a quantization circuit 62 comprising a multiplication circuit 63 and a barrel shifter 64. Is done.

The synchronization signal supplied through the input terminal 59 is supplied to the timing generation and table circuit 60. When the synchronization signal is supplied, the timing generation and table circuit 60 supplies the multiplication circuit 63 of the quantization circuit 62 with the quantized coefficient read from the table, supplies the barrel shifter 64 with the AC shift data, and supplies the addition circuit 69 with the DC shift data. Is supplied, and a timing signal is supplied to the gate circuit 72.

The multiplication circuit 63 of the quantization circuit 62 multiplies the video data supplied through the input terminal 55 by the quantization coefficient from the timing generation and table circuit 60, and supplies the multiplied output to the barrel shifter 64. The barrel shifter 64 shifts the multiplication result from the multiplication circuit 63 based on the timing generation and the AC shift data from the table circuit 60, and supplies the shifted data to the variable length encoding circuit 65.

The variable length coding circuit 65 includes a category conversion circuit 66 for performing a category conversion, a code length conversion circuit 68 for converting a code length, and a table 67 for outputting a variable length code based on the output from the category conversion circuit 66. It consists of.

Here, the category conversion will be described with reference to FIG. In FIG. 14, the category is shown on the left side, and the actual quantization coefficient is shown on the right side. That is, as shown in FIG. 14, the category conversion circuit 66 includes a quantization circuit and a table 67.
The category conversion circuit 66 converts the quantized data from the quantization circuit 62 into category data according to an internal table. The actual quantization coefficient is a quantization circuit 6
14 shows the quantized data supplied from the second unit, and as shown in FIG. 14, outputs the category data based on the value of the actual quantized coefficient.

The output data of the category conversion circuit 66,
That is, the category data is supplied to the table 67 and the code length conversion circuit 68, respectively. The table 67 outputs variable-length code data according to the category data from the category conversion circuit 66. In the code length conversion circuit 68,
The code length of the variable length code is obtained based on the category data from the category conversion circuit 68 and the variable length code from the table 67, and the obtained code length data is supplied to the addition circuit 69.

Here, a method of calculating the code length of the variable length code will be described with reference to FIGS.

FIG. 12A shows a method of calculating the code length of the video data of the DCT block that does not employ EOB. The numerical values shown immediately below the solid-line arrows are data from the AC component to the DC component, and further below that. Are the code lengths.

The numerical values in each pair are the current value and the previous value, and the variable length code and the code length are obtained based on these values. The variable length code and code length are obtained from a table as shown in FIG. In the method shown in FIG. 12A, the value “0” is also regarded as data, so that the code length becomes longer.

FIG. 12B shows a method of calculating the code length of video data of a DCT block employing EOB.
As shown in FIG. 2B, if there is data other than “0” after “0” continues, this is regarded as an EOB.
“0” is not considered as data. Therefore, in this method, the code length becomes short. In any case, the code length is obtained by using one of the method shown in FIG. 12A and the method shown in FIG. 12B.

The code length data of the equalization unit obtained by the code length conversion circuit 68 in this way is supplied to an addition circuit 69, where the timing generation and the conversion of the equalization unit from the table circuit 60 are performed. It is added to the code length data of the DC coefficient. This addition output is output from the comparator 70
, And compared with a target value (bit rate) from a target value generation circuit 71 in a comparator 70. The comparator 70 outputs a comparison result of “1” when the addition output from the addition circuit 69 is larger than the target value, and “0” when the addition output is smaller than the target value.

The comparison result is supplied to the gate circuit 72. The gate circuit 72 is supplied with a timing signal from the timing generation and table circuit 60. The gate circuit 72 outputs a quantization coefficient based on the timing generation and the timing signal from the table circuit 60 and the comparison result from the comparator 70. This quantized coefficient is stored in selector 5
7 is supplied. In the selector 57, FIFO5
The video data read from 6 is supplied to the encoder 5 shown in FIG.

Here, the quantization level calculation system of the quantization circuit 4 shown in FIG. 7, that is, the binary search circuits 38 to 44
A method of calculating the quantization level by the following will be described.

The method of calculating the quantization level is a method generally called a binary search method or the like. For example, when the quantization level is 7 bits and the most significant bit is determined,
The quantization level is set to an intermediate value “6” between the maximum “127” and the minimum “0”.
The level is set to “3” and provisional quantization is performed at this level “63”. If the sum of the code lengths of equal length units (for 640 clocks) at this time is larger than the target bit rate, the most significant bit is “1”. "0" if smaller.

For the next sixth bit, if the most significant bit is “1”, provisional quantization is performed at the intermediate level “95” of the quantization levels “127” to “63”, and if “0”, the quantization level is “ Quantization is performed at an intermediate “31” level between “63” and “0”. If the sum of the code lengths of the equal length units (for 640 clocks) is larger than the target bit rate, the sixth bit is set to “1”, and if smaller, the bit is set to “0”. Hereinafter, similarly, the least significant bit is determined.

In this way, for example, when the quantization level is 7 bits, a total of seven binary search circuits 38 to 44 are provided as shown in FIG. The quantization level can be determined.

The quantization levels determined by the binary search circuits 38 to 44 are determined by the back search circuit 4 as described above.
In 6, after being corrected based on, for example, distortion during dubbing, it is supplied to the quantization circuit 47, and is actually used as the quantization level of the DCT coefficient.

[0036]

As described above, if a binary search circuit having the structure shown in FIG. 8 is provided as many as the number of bits of the quantization level as shown in FIG. In particular, providing the multiplier 63 of the quantization circuit 62 shown in FIG. 8 as many as the number of bits of the quantization level means that the multiplier occupies a very large mounting area in a pure logic circuit. There was an inconvenience.

Further, in the code length conversion circuit 68 of the variable length coding circuit 65 shown in FIG. 8, the code length is obtained by either the method using the EOB or the method not using the EOB. There is a disadvantage that the code amount cannot be predicted for efficient coding conversion.

The present invention has been made in view of the above point, and can simplify the circuit configuration, reduce the circuit scale as much as possible, and perform code amount prediction for efficient coding conversion. It is intended to propose a quantization level calculation method and apparatus.

[0039]

According to the method of calculating a quantization level of the present invention, a quantization coefficient is set in correspondence with an n-bit quantization level value, and when the setting is performed, the quantization coefficient is quantized. A predetermined quantization level is applied to the digital data in order to have a periodicity corresponding to the level and quantize the digital data of the equal length unit with the most optimal quantization coefficient indicated by the n-bit quantization level. Performs temporary quantization with
When determining the n-th bit of the n-bit quantization level according to the bit rate of the quantized data, and determining the (nm) -bit value of the n-bit quantization level, the (nm) bit is determined. ) Bits higher than {n- (m-1)} to n
The quantization is performed at a predetermined quantization level based on the bit value, the bit rate of the obtained quantized data is compared with a target bit rate, and (n−
m) The value of a bit is determined, and finally a quantization level of n bits is obtained.

Further, in the above description, the quantization level calculation method of the present invention employs a ｛n- (m-
1) The quantization coefficients selected by a plurality of predetermined quantization levels used based on the values of｝ bits to n bits are the same.

Further, in the above-described quantization level calculation method of the present invention, when determining the value of (nm) bits, the digital data of the equal length unit is shifted, and the value obtained by this shift is equal to the shifted value. Quantized data is obtained by adding digital data in units of length.

Further, in the above-described quantization level calculation method of the present invention, when determining the value of (nm) bits, the quantized data is obtained by shifting the digital data in equal length units. .

Further, the quantization level calculation apparatus of the present invention multiplies input digital data in equal length units by a quantization coefficient,
Quantizing means 62 for shifting and quantizing the input digital data of the equal length unit, code length converting means 65 for converting the code length of the quantized data from the quantizing means 62, and code length converting means 65 Comparing means 69, 70, and 71 for comparing the output data of each of them with a target value;
A plurality of quantization level calculation means including control means 57, 90, and 72 for determining the bits of the quantization level based on the comparison result of 0, 71 are provided in correspondence with the number of bits of the quantization level. In a quantization level calculation device which calculates all bits of a quantization level by using a level calculation means to obtain a quantization level, an arbitrary number of quantization level calculation devices among a plurality of quantization level calculation means are provided. In the quantizing means 62, the input digital data of the equal length unit is multiplied by a predetermined quantizing coefficient and shifted to obtain quantized data, and the quantized means 80 or 82 of the remaining quantization level calculating device is used. Is obtained by shifting the input digital data in equal length units and adding the input digital data to obtain quantized data, or Performed only shift it is obtained so as to obtain quantized data.

The quantization level calculating apparatus according to the present invention further comprises a quantizing means 62, 80 or 82 for quantizing input digital data in equal length units, and a quantized data from the quantizing means 62, 80 or 82. Code length conversion means 65 for converting the code length, comparison means 69, 70, 71 for comparing the output from the code length conversion means 65 with a target value, and a comparison result based on the comparison results of the comparison means 69, 70, 71. In the quantization level calculation device having control means 57, 90 and 72 for determining the bits of the quantization level, the code length conversion means 65 detects a code indicating the end of the block for each block in units of equal length, A function of determining whether or not to add this code is provided.

Further, in the above description, in the quantization level calculating apparatus of the present invention, the code length converting means 65 is replaced by the quantizing means 62 and 80.
Or a category conversion means 66 for converting the category of the quantized data from 82, and a variable length code output means 6 for outputting a variable length code based on the output of the category conversion means 66
7, a block end code detecting unit 92 for detecting a block end code indicating the end of the block output from the category conversion unit 66, and a block end code detecting unit 92.
A block end code output means 93 for outputting a block end code based on the detection output from the block end code value conversion means 94; a block end code value conversion means 94 for converting the value of the block end code from the block end code output means 93; 6
6 and the variable length code output means 67, and a second addition means for adding the output of the first addition means 96 and the output of the comparison means 95. 98 and a comparing means 95 for comparing the output from the block end code value converting means 94 and the output from the second adding means 98.

[0046]

According to the method of the present invention described above, the quantization coefficients are set in correspondence with the values of the n-bit quantization levels, and when the quantization coefficients are set, the quantization coefficients correspond to the quantization levels.
To have a periodicity Te, the digital data of equal length unit n
In order to quantize with the most optimal quantization coefficient indicated by the bit quantization level, provisional quantization is performed on the digital data at a predetermined quantization level, and n bits are determined according to the bit rate of the quantized data. When the n-th bit of the quantization level is determined and the value of the (nm) bits of the n-bit quantization level is determined, ｛n− (m−) higher than the (nm) bits 1) Quantization is performed at a predetermined quantization level based on the values of｝ to n bits, the obtained bit rate of the quantized data is compared with a target bit rate, and (n− m) Determine the value of the bits and finally obtain an n-bit quantization level.

Further, according to the method of the present invention described above,
The quantization coefficients selected by a plurality of predetermined quantization levels used based on the values of {n- (m-1)} bits to n bits higher than (nm) bits are the same. To

Further, according to the method of the present invention described above,
When determining the value of (nm) bits, the digital data of the equal length unit is shifted, and the value obtained by this shift is added to the digital data of the equal length unit to obtain quantized data. .

Further, according to the method of the present invention described above,
When determining the value of (nm) bits, quantized data is obtained by shifting digital data in units of equal length.

Further, according to the configuration of the present invention, in the quantization means 62 of an arbitrary number of quantization level calculation devices among the plurality of quantization level calculation means, a predetermined quantization The quantized coefficient is multiplied and shifted to obtain quantized data, and the quantizing means 80 or 82 of the remaining quantizing level calculating device shifts the input digital data in equal length units, Is added to obtain quantized data, or quantized data is obtained by shifting only the input digital data.

Further, according to the configuration of the present invention, the code length conversion means 65 detects a code indicating the end of a block for each block in equal length units, and determines whether or not to add this code. .

Further, according to the configuration of the present invention described above,
The category of the quantized data from the quantization means 62, 80 or 82 is converted by the category conversion means 66, and based on the output of the category conversion means 66, the variable length code output means 67
And outputs a variable-length code. The block end code indicating the end of the block output from the category conversion means 66 is detected by the block end code detection means 92. Based on the detection output from the block end code detection means 92, a block is output. The end code is output by the block end code output means 93, the value of the block end code from the block end code output means 93 is converted by the block end code value conversion means 94, and the output from the category conversion means 66 and the variable length code are output. The variable length code from the output means 67 is added by the first addition means 96, and the output of the first addition means 96 and the output of the comparison means 95 are added by the second addition means 98, and the block end code value conversion is performed. Means 9
The output from the second adding unit 98 and the output from the second adding unit 98 are compared by a comparing unit 95.

[0053]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a quantization level calculating method and apparatus according to the present invention will be described below in detail with reference to FIG.

In FIG. 1, portions corresponding to those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral 80 denotes a quantization circuit. In this example, this quantization circuit 80 is constituted by a barrel shifter 64 and an addition circuit 81 as shown in the figure. A timing generation circuit 90 differs from the timing generation and table circuit 60 shown in FIG. 8 in that a table for outputting a quantization coefficient is not used.

Here, while the components of the quantization circuit 62 shown in FIG. 8 are the multiplication circuit 63 and the barrel shifter 64, the configuration of the quantization circuit 62 can be changed to the barrel shifter 64 and the addition circuit 81 in this example. The reason for this will be described with reference to FIG.

In FIG. 3, when the quantization level is n bits, n
The quantization levels from the first bit to the first bit are shown. As can be seen from FIG. 3, when n is 7, the n-th bit (7th bit) in FIG. 3 has one quantization level of “63” as described above, but the sixth bit ( n-
After the first bit), two quantization levels are selected according to the previous value, that is, the value of the seventh bit.

That is, when the total number of bits is 7 bits, when the most significant bit is determined to be "1" or "0",
The next 6th bit is quantized at a quantization level according to the value of the 7th bit, and determined based on the result of comparing the quantized data with the above-described target value.
Quantize at the quantization level according to the value of the bit, determine based on the result of comparing the quantized data with the above-described target value, and so on. Similarly, values of all bits before the bit The value of the bit is determined based on the result of comparing the result with a target value.

In this example, the quantization level is defined as index data for selecting a quantization coefficient for quantizing the input DCT coefficient. That is, the quantization coefficients corresponding to the quantization levels shown in FIG. 3 are selected.

In the present embodiment, for example, 16 quantization coefficients are prepared, and a periodicity is provided in accordance with the quantization level. For example, when the quantization level is 7 bits, in FIG. 3, for example, the seventh bit has one quantization level, the sixth bit has two quantization levels, and the fifth bit has four quantization levels. The fourth bit has a quantization level of 8
Therefore, the same quantization coefficient is output for each quantization level from the sixth bit to the fourth bit. For example, although there are two quantization levels in the sixth bit, the same quantization coefficient is assigned to these two quantization levels.

In this way, for example, in the multiplying circuit 63 shown in FIG. 8, the timing generation and the quantization coefficient from the table circuit 60 can be fixed, so that it is not necessary to have a table of the quantization coefficient. .

Further, multiplying the video data (DCT coefficient data) by the quantization coefficient which is a fixed value in the multiplication circuit 63 means that the multiplication circuit 63 becomes unnecessary. For example, when multiplying “2” by “3”,
If “3” is a fixed value, “2” is “10” in binary,
The result of multiplication is "110" in binary. Therefore, this shifts “2” (“10”) to “100” and adds the original “2” (“10”) to this to obtain the same “6” (“110”) as the multiplication result. be able to.

That is, when the value to be multiplied by the video data is not a power of 2, if the value to be multiplied is fixed, the video data is simply shifted, and the shifted video data and the video data before the shift are added. .

Accordingly, as described above, if the same quantization coefficient is given to a plurality of quantization levels in a certain bit, that is, if the fixed value is set, the barrel shifter 64 and the addition The circuit 81 can form the quantization circuit 80.

That is, in this example, among the binary search circuits 38 to 44 shown in FIG. 7, at least the configuration of the quantization circuits of the binary search circuits 38 to 41 is simplified by using no simple multiplication circuit as shown in FIG. Can be configured.

As described above, in this example, for a plurality of quantization levels corresponding to a certain bit of the quantization level,
Since the same quantization coefficient is given by giving the quantization coefficient periodicity, when the quantization level is 7 bits, at least the 7th to 4th bits of the binary search circuit corresponding to the 7th to 4th bits are used. The quantization circuit eliminates the need for a multiplication circuit and a table for outputting the quantization coefficient, thereby significantly reducing the circuit scale, reducing the circuit mounting area, and greatly improving the design efficiency. Moreover, the calculation speed can be improved.

In the above example, the multiplier is fixed,
The number of divisions can be changed by changing the shift amount. For example, when “2” is multiplied by “5”, if “5” is a fixed value, “2” is “1” in binary.
The result of multiplication is “1010” in binary, so that “2” (“10”) is shifted by 2 bits to “1000”, and the original “2” (“10”) is added to this. ), The same "10"("1010") as the multiplication result can be obtained.

FIG. 2 is a block diagram showing another example of the quantization level calculation device of the present example. Hereinafter, another example of the quantization level calculation device of the present example will be described with reference to FIG.

In FIG. 2, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral 82 denotes a quantization circuit. As shown in this figure, in this example, the addition circuit 81 shown in FIG. 1 is not required. That is, this example shows a configuration in which the quantization level is a power of two. When the quantization level is a power of 2, it is only necessary to change the shift amount in the barrel shifter 64.
The addition circuit 81 shown in FIG. 1 is not required.

For example, when “2” is multiplied by “4”,
When “4” is a fixed value, “2” is a binary number “1”.
The result of multiplication is “100” in binary, so this is only by shifting “2” (“10”) to “1000”, and the same as the multiplication result “8” (“1000”). ) Can be obtained.

As described above, in this example, when the quantization level is a power of two, the configuration of the quantization circuit 82 is only the barrel shifter 64, which is simpler than the circuit configuration shown in FIG. As a result, the circuit mounting area can be further reduced, the design efficiency can be greatly improved, and the operation speed can be significantly improved.

In the above example, the multiplier is fixed,
The number of divisions can be changed by changing the shift amount. For example, when "2" is multiplied by "8", if "8" is a fixed value, "2" is represented by a binary number "1".
0, and the result of multiplication becomes “10000” in binary.Therefore, this is the same as the multiplication result “16” by simply shifting “2” (“10”) by 3 bits to “10000”.
("10000").

Next, the internal configuration of the code length conversion circuit 68 shown in FIG. 1 will be described with reference to FIG. In the present example, the code length conversion circuit 68 compares the code lengths when EOB is detected, and outputs the more efficient code length.

As described with reference to FIGS. 12 and 13, in the code amount prediction, there are a method using EOB and a method not using EOB. In this example, when code amount prediction or quantization of digital data is performed, an EOB is detected for each DCT block in units of equal length, and whether or not an EOB is added is detected. To do.

In FIG. 4, reference numeral 91 denotes an input terminal to which the category data from the category conversion circuit 66 shown in FIG. 1 is supplied.
6 is supplied to the adder circuit 96 and the EOB detection circuit 92, respectively.

The EOB detection circuit 92 is the category conversion circuit 6
The EOB is detected from the category data from No. 6 and the detection result is supplied to the table 93. The table 93 supplies a value based on the detection result from the EOB detection circuit 92 to the value conversion circuit 94. The value conversion circuit 94 continues to supply, for example, data of the value “1FF” to the comparator 95 until data indicating EOB is supplied.

On the other hand, the code length data from the table 67 shown in FIG. 1 is supplied to the addition circuit 96, and this code length data is added to the category data from the category conversion circuit 66 shown in FIG. The result is supplied to an addition circuit (accumulation circuit) 98, and is added to the output of the comparator 95, whereby the code length is accumulated. This adding circuit 9
The output of 8 is supplied to a comparator 95. The comparator 95 compares the value from the value conversion circuit 94 with the value from the addition circuit 98, and supplies the smaller value to the addition circuit 69 shown in FIG. give feedback.

That is, in this circuit, the addition output from the addition circuit 98, ie, the category data from the category conversion circuit 66 and the table 6 until the EOB is detected.
7 is output as code length data, and when EOB is detected, the code length data from the value conversion circuit 94 and the code length data from the addition circuit 98 are compared. , The smaller one is output. Then, the code length is calculated until the end of the block. Therefore, in this example, both the method using EOB and the method not using EOB are used, and the code lengths obtained by both methods are compared, and as a result, the shorter one is always selected. It is possible to predict the code amount for efficient coding conversion.

As described above, in this embodiment, both the method using EOB and the method not using EOB are used, and the code lengths obtained by both methods are compared, and as a result, the shorter one is always selected. Therefore, it is possible to predict the code amount for efficient coding conversion.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.

[0082]

According to the present invention described above, the quantization coefficients are set in correspondence with the n-bit quantization level values, and the quantization coefficients are set in correspondence with the quantization levels when setting.
To have a periodicity Te, the digital data of equal length unit n
In order to quantize with the most optimal quantization coefficient indicated by the bit quantization level, provisional quantization is performed on the digital data at a predetermined quantization level, and n bits are determined according to the bit rate of the quantized data. When the n-th bit of the quantization level is determined and the value of the (nm) bits of the n-bit quantization level is determined, ｛n− (m−) higher than the (nm) bits 1) Quantization is performed at a predetermined quantization level based on the values of｝ to n bits, the obtained bit rate of the quantized data is compared with a target bit rate, and (n− m) Since the value of the bit is determined and finally the quantization level of n bits is obtained, the circuit configuration can be simplified and the circuit scale can be made as small as possible.

Further, according to the present invention described above, (n-
{n− (m−1)} bits to n higher than m) bits
Since the same quantization coefficient is selected by a plurality of predetermined quantization levels used based on the value of the bit, in addition to the above-described effects, a table for outputting the quantization coefficient is unnecessary, As a result, the circuit configuration can be simplified, and the calculation speed can be improved.

Further, according to the present invention, (n-
m) When determining the bit value, the digital data in the equal length unit is shifted, and the value obtained by this shift and the digital data in the equal length unit are added to obtain the quantized data. Therefore, in addition to the above-described effects, it is possible to eliminate the need for using a multiplication circuit that complicates the circuit configuration and reduces the operation speed.

Further, according to the present invention, (n-
m) When deciding the bit value, the digital data in the equal length unit is shifted to obtain the quantized data. Therefore, in addition to the above-described effects, multiplication that complicates the circuit configuration and slows down the operation speed is performed. It is not necessary to use a circuit, and it is not necessary to use an adder circuit. As a result, the circuit configuration can be simplified, and the calculation speed can be greatly improved.

Further, according to the present invention described above, in the quantizing means of the arbitrary number of quantizing level calculating devices among the plurality of quantizing level calculating means, a predetermined quantizing is performed on the input digital data of the equal length unit. The quantized data is obtained by multiplying and shifting the coefficients, and the quantizing means of the remaining quantization level calculating device adds the shifted input digital data of the equal length unit and this input digital data. Since quantized data is obtained or quantized data is obtained only by shifting input digital data, in addition to the above-described effects, the circuit configuration can be further simplified and the circuit scale can be reduced as much as possible. .

Further, according to the present invention described above, the code length conversion means detects a code indicating the end of a block for each block in equal length units, and determines whether or not to add this code. In addition, it is possible to perform code amount prediction for efficient coding conversion.

Further, according to the present invention, the category of the quantized data from the quantization means is converted by the category conversion means, and the variable length code output means outputs the variable length code based on the output of the category conversion means. The block end code indicating the end of the block output from the category conversion means 66 is detected by the block end code detection means, and the block end code is output based on the detection output from the block end code detection means. And the value of the block end code from the block end code output means is converted by the block end code value conversion means, and the output from the category conversion means and the variable length code from the variable length code output means are subjected to the first addition. And an output of the first adding means and an output of the comparing means are added by a second adding means. Since the output from the output and a second adding means et be compared with comparison means, in addition to the effects described above, the code amount prediction for efficient encoding transformation can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a quantization level calculation method and apparatus according to the present invention.

FIG. 2 is a configuration diagram illustrating another example of a quantization level calculation method and apparatus according to the present invention.

FIG. 3 is an explanatory diagram showing an example of a quantization level for explaining an embodiment of a quantization level calculation method and apparatus according to the present invention;

FIG. 4 is a configuration diagram showing a main part of an embodiment of a quantization level calculation method and apparatus according to the present invention.

FIG. 5 is a configuration diagram illustrating an example of a recording system of a digital VTR.

FIG. 6 is a configuration diagram showing an example of a reproduction system of a digital VTR.

FIG. 7 is a configuration diagram showing a main part of a conventional quantization device.

FIG. 8 is a configuration diagram of a quantization level calculation device showing a main part of a conventional quantization device.

FIG. 9 is an explanatory diagram showing a data format used for describing a conventional quantization level calculation device.

FIG. 10 is an explanatory diagram showing a data format used for describing a conventional quantization level calculation device.

FIG. 11 is an explanatory diagram showing a data format used for describing a conventional quantization level calculation device.

FIG. 12 is an explanatory diagram showing a relationship between an EOB (end of block) and a code length for explaining a conventional quantization level calculation device.

FIG. 13 is an explanatory diagram showing an example of a variable-length code table for explaining a conventional quantization level calculation device.

FIG. 14 is an explanatory diagram showing a category conversion table used for explaining a conventional quantization level calculation device.

[Explanation of symbols]

56 FIFO (first in first out) 57 selector 62, 80, 82 quantization circuit 64 barrel shifter 65 variable length code conversion circuit 66 category conversion circuit 67, 93 table 68 code length conversion circuit 69, 81, 96, 98 addition Circuit 70 Comparator 71 Target value generation circuit 72 Gate circuit 90 Timing generation circuit 92 EOB detection circuit 93 Table 94 Value conversion circuit 95 Comparator

Claims (7)

(57) [Claims] 1. A quantization coefficient is set corresponding to an n-bit quantization level value, and at the time of setting, the quantization coefficient is given a periodicity corresponding to the quantization level, and is equalized. In order to quantize the digital data of the unit with the most optimal quantization coefficient indicated by the n-bit quantization level, provisional quantization is performed on the digital data at a predetermined quantization level, and the quantized data is When determining the n-th bit of the n-bit quantization level according to the bit rate, and determining the value of the (nm) bit of the n-bit quantization level, the value of the (nm) bit is determined to be smaller than the (nm) bit. Top ｛n
-Quantization is performed at a predetermined quantization level based on the values of (m-1)｝ to n bits, the bit rate of the obtained quantized data is compared with a target bit rate, and based on the comparison result, And (n-m) -bit values are determined, and finally an n-bit quantization level is obtained. 2. A higher order {n} than the above (nm) bits
2. A quantization coefficient selected by a plurality of predetermined quantization levels used based on a value of-(m-1)｝ bits to n bits is made equal.
A method for calculating the described quantization level. 3. When determining the value of the (nm) bits, if the quantization coefficient is not a power of 2, the digital data of the equal length unit is shifted, and the shift is performed. 2. The quantization level calculation method according to claim 1, wherein a quantization value is obtained by adding a value and the digital data of the equal length unit. 4. When determining the value of (nm) bits, if the quantization coefficient is a power of 2, the digital data of the equal length unit is shifted to obtain quantized data. 2. The method for calculating a quantization level according to claim 1, wherein: 5. Quantizing means for multiplying input digital data of an equal length unit by a quantization coefficient, shifting the input digital data and quantizing the input digital data of the equal length unit, and quantizing from the quantizing means. Code length converting means for converting the code length of data, comparing means for comparing output data of the code length converting means with a target value, and control for determining a bit of a quantization level based on a comparison result of the comparing means A plurality of quantization level calculation means corresponding to the number of bits of the quantization level, and calculating all the bits of the quantization level using the plurality of quantization level calculation means. In the apparatus, in the quantization means of any number of the quantization level calculation means among the plurality of quantization level calculation means, a predetermined quantization coefficient is assigned to the input digital data of the equal length unit. In addition, the quantization means of the remaining quantization level calculation device adds the shifted input digital data of the equal length unit and the input digital data to obtain the quantized data. A quantization level calculating device, wherein quantized data is obtained, or quantized data is obtained by shifting only input digital data. 6. A quantizing means for quantizing input digital data in equal length units, a code length converting means for converting a code length of the quantized data from the quantizing means, In a quantization level calculation device having comparison means for comparing an output with a target value, and control means for determining a bit of a quantization level based on a comparison result of the comparison means, A quantization level calculation device characterized by having a function of detecting a code indicating the end of a block for each block in units and determining whether or not to add the code. 7. The code length conversion means, a category conversion means for converting a category of the quantized data from the quantization means, and a variable length code output for outputting a variable length code based on an output of the category conversion means. Means, a block end code detecting means for detecting a block end code indicating the end of the block of the output from the category converting means, and a block end for outputting a block end code based on the detection output from the block end code detecting means. Code output means; a block end code value conversion means for converting the value of the block end code from the block end code output means; and an output from the category conversion means and a variable length code from the upper variable length code output means. First adding means for performing the above, second adding means for adding the output of the first adding means and the output of the comparing means, Output and quantization level calculating apparatus according to claim 6, characterized in that is constituted by a comparator means for comparing the output from said second adder means from the lock end code value conversion means.