JPH06289099A - Scanning circuit - Google Patents

Abstract

PURPOSE:To make it possible to prevent the increase in area of an LSI-chip circuit and the erroneous operation caused by clock skew by making a single- phase clock, which is imparted into an FF of a scanning cell, flow in the reverse direction with respect to the flow of the data of the scanning cell. CONSTITUTION:At the time of a test mode, each FF of a scanning cell 102 propagates the scan data in synchronization with a clock from scan-in Si to scan-out SO through a scan data line 105. The clock is supplied into each FF from a clock CLK through a clock line 106. The clock is propagated from the side of the so toward the side of the S1. A delay time is generated during the propagation. The closk is delayed from, e.g. the FF 203 and propagated into the FF 204. Therefore, the FF 204 accepts the next data at the next clock. At the time point when the data are outputted to a data-output terminal Q, the time is after the determination of the previous data at the FF 203. Therefore, the operation at this time point by the clock does not directly affect on the operation of the FF 203.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan circuit in an LSI designed for testability.

[0002]

2. Description of the Related Art In recent years, it has become difficult to sufficiently test large-scale and highly integrated LSIs, which is a serious problem. Therefore, it is necessary to perform testability design considering the test from the design stage.

Under the above background, until now,
Several testability techniques have been developed and put into practice. Among them, a scan design method is one of the most commonly used test facilitation methods.

In the scan design method, the function of the shift register is added to the flip-flop of the sequential circuit so that the state of the flip-flop can be directly controlled and observed from the outside. This makes it possible to handle the sequential circuit as a combinational circuit, and facilitates test pattern generation using the combinational circuit test generation algorithm.

A number of scan design methods have been developed so far, for example, IBM's LSSD method and NEC.
Scan path method, Sperry-Univac scan set method, Fujitsu random access scan method, Hitachi scan bus method, etc. are known.
M, NEC, Sperry-Univac, Fujitsu and Hitachi are all manufacturer names, and each method is a unique name for each company).

When it is difficult to test a single LSI chip, it is naturally difficult to test a board on which the LSI chip is mounted. In order to solve such a problem, a boundary scan method for facilitating a board test has been proposed.

FIG. 4 shows an example of a conventional clock signal circuit, and in particular, a scan design method is extended to a board. As shown in FIG. 4, a boundary scan cell 102 having a shift function is inserted in each input / output terminal of a chip 401, and a plurality of chips 401 on a board 402 are serially connected by a scan path 304. Scan campus 304 has scan-in SI and scan-out SO
Is connected to the outside by.

In the above structure, the board 402
Scan path 30 from outside the system through scan-in SI
4 to access the chip 401 from the scan cell 102 to perform a necessary test.
Thereby, the data is obtained from the scan-out SO and the test result is taken out. By the way, this boundary scan is an IEEE standard (IEEE EEP1149.1).

In order to realize various scan design methods including boundary scan as described above, some caution is required. One of them is that when the scan circuit operates as a shift register and a clock skew occurs, that is, variations in AC characteristics such as rise time and fall time of the clock supplied to the scan flip-flop. If it occurs, there is a problem of malfunction.

In many cases, the wiring length is short and the load is light between the scan data out and the scan data in of the adjacent scan flip-flops serially connected to the scan path. For this reason, the time taken for the scan data to propagate is relatively short, and there is a possibility of malfunction when clock skew occurs.

For example, consider the operation of a shift register as shown in the block diagram of FIG. Incidentally, as shown in FIG. 6, the flip-flop F1 and the flip-flop F
The data input terminal D and the data output terminal Q are serially connected to each other, and the clock of the same phase is supplied to the clock input terminal C. Then, the data of the flip-flop F1 is shifted to the flip-flop F2 in synchronization with the rising edge of the clock.

FIG. 8 is a timing chart showing how the circuit of FIG. 6 operates normally. 8A shows the state of the signal supplied to the clock input terminal C of the flip-flop F1, FIG. 8B shows the state of the signal supplied to the clock input terminal C of the flip-flop F2, and FIG. 8C.
Shows the state of the data output from the data output terminal Q of the flip-flop F1, and FIG. 7D shows the state of the data output from the data output terminal Q of the flip-flop F2.

As shown in FIGS. 8A and 8B, the clock of the clock input terminal C of the flip-flop F1 and the clock of the clock input terminal C of the flip-flop F2 simultaneously rise at time t1. Therefore, the state of the data output terminal Q of the flip-flop F1 is as shown in FIG.
As shown in FIG.
The data is switched from n to data Sn + 1. The state of the data output terminal Q of the flip-flop F2 is as shown in FIG.
The data has been switched from 1 to data Sn.

That is, the flip-flops F1 and F2 are
Together, the data is sequentially shifted in synchronization with the clock input to the clock input terminal C.

However, if the flip-flops F1 and F2 are
If a clock is input to the clock input terminal C, the data will not be shifted normally.

FIG. 7 is a timing chart showing a state when the circuit of FIG. 6 is not operating normally due to skew. 6A shows the state of the signal supplied to the clock input terminal C of the flip-flop F1, FIG. 6B shows the state of the signal supplied to the clock input terminal C of the flip-flop F2, and FIG. The state of the data output from the data output terminal Q of the flip-flop F1 and the state of the data output from the data output terminal Q of the flip-flop F2 are shown in FIG.

Now, due to clock skew, FIG.
As shown in (a), the clock of the clock input terminal C of the flip-flop F1 rises at time t1, and as shown in (b) of the figure, the clock of the clock input terminal C of the flip-flop F2 rises at time t2. Be present. In this case, there is a time difference T between the rising edge of the clock of the flip-flop F1 and the rising edge of the clock of the flip-flop F2. Then, the state of the data output terminal Q of the flip-flop F1 is switched from the data Sn to the data Sn + 1 at the timing of almost time t1, as shown in FIG. On the other hand, the state of the data output terminal Q of the flip-flop F2 takes in the data Sn + 1 which is the data of the data output terminal Q of the flip-flop F1 at a timing of almost time t2, as shown in FIG. Switches from data Sn to data Sn + 1. That is, since the clock skew continuously occurs in time, the data of the flip-flop F2 is switched to the same data as the data of the flip-flop F2 with a time difference of time T.

That is, the shift of the data from the flip-flop F1 to the flip-flop F2 in synchronization with the clock is not normally performed. That is, the data that should originally be switched to the data Sn becomes the same data Sn + 1 as the flip-flop F1. This means that the shift register operation shifts by one extra step.

In order to solve the above problems, for example, in the IBM (manufacturer name) LSSD (unique name) system, as shown in FIG. Prevents malfunction due to clock skew. In FIG. 5, the data D is directly input to the NAND circuit NAND1 connected to the clock C and is input to the NAND circuit NAND2 connected to the clock C via the inverter INV1. NAND circuit N
The output of the AND1 is input to the NAND circuit NAND5, and the output of the NAND circuit NAND2 is output to the NAND circuit NAND6. On the other hand, the scan data S constituting the scan path is the NAND circuit NAND3 to which the clock A is applied.
NAND circuit N that is directly input to and is given clock A
It is input to AND4 via the inverter INV2. The output of the NAND circuit NAND3 is input to the NAND circuit NAND5, and the output of the NAND circuit NAND4 is the NAND circuit NA.
Input to ND6. The output of the NAND circuit NAND5 is connected to the NAND circuit NAND6, and the output of the NAND circuit NAND6 is connected to the NAND circuit NAND5. Then, the output of the NAND circuit NAND5 is derived as the output L1. On the other hand, the output of the NAND circuit NAND5 is given to the NAND circuit NAND7 to which the clock B is input, and the output of the NAND circuit NAND6 is given to the NAND circuit NAND8 to which the clock B is input. NAND circuit N
The output of the AND 7 is input to the NAND circuit NAND 9, and the output of the NAND circuit NAND 8 is input to the NAND circuit NAND 10. The output of the NAND circuit NAND9 is connected to the NAND circuit NAND10, and the output of the NAND circuit NAND10 is connected to the NAND circuit NAND9. Then, the output of the NAND circuit NAND9 is derived as the output L2.

In the above-mentioned configuration, the system including the clock A, the clock B, the scan data S, etc. is not operated during the normal operation, and the normal system is constituted by the inverter INV1, the NAND circuits NAND1, NAND2, NAND5, NAND6. As a flip-flop, the data at the data input terminal D is output L in synchronization with the clock input terminal C
Output as 1.

On the other hand, when these are operated as shift registers at the time of test, the clock input terminal C is made inactive and the flip-flop is composed of the inverter INV2, the NAND circuits NAND3, NAND4, NAND5 and NAND6. , Holds the scan data S in synchronization with the clock A. Next, this held data is transferred to the NAND circuits NAND7, NAND8, N
It is taken in by a flip-flop composed of AND9 and NAND10 in synchronization with the clock B, and is output to the output L2. In other words, the clock A and the clock B are alternately applied, and the scan data S is fetched in synchronization with the clock A and shifted so as to be output in synchronization with the clock B. The data output of the output L2 does not change until the data is fetched. As a result, the operation as the shift register can be normally maintained even if the clock is skewed.

[0022]

As described above, the conventional clock signal circuit uses a flip-flop having a circuit configuration in which clocks are multi-phased in order to prevent malfunction due to clock skew. For this reason, it is inevitable that the circuit area will be larger than that of a normal flip-flop, and that the number of clocks will be increased due to the multiphase. For this reason,
There is a problem that the clock wiring area also increases. When the circuit area of the flip-flop is increased, the area of the chip on which the circuit is integrated is naturally increased.

In the case of the boundary scan system,
It is necessary to equip each input / output terminal of the chip with a boundary scan cell. Therefore, there is also a problem that the area of the peripheral circuit portion of the chip including the I / O buffer increases in the tendency of increasing the scale and increasing the number of pins.

The present invention has been made in view of the above, and an object thereof is to suppress an increase in the circuit area of an LSI chip and, at the same time, to prevent a malfunction due to a clock skew during a scan operation. To provide a circuit.

[0025]

The scan circuit of the present invention comprises a plurality of scan cells each having a clock-synchronous flip-flop, which are serially connected and serially shifted based on a control signal. Configured to operate as registers, clock lines are placed along the columns of these shift registers,
In order to propagate the clock in the direction opposite to the data propagation direction in the shift register, one of the clock lines on the data output side as the serial shift register is configured as a clock input end.

[0026]

The single-phase clock given to the flip-flop is caused to flow in the opposite direction to the data flow of the scan cell, thereby increasing the clock delay toward the upstream side of the data flow, and each scan cell. The operation of the shift register composed of the flip-flops is ensured.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a clock signal circuit according to an embodiment of the present invention. As shown in FIG. 1, the LSI chip 101 adopting the boundary scan method is
In addition to the internal circuit 104 in which the original function of this chip is made into a circuit, scan cells 102 are inserted in each input / output terminal for connecting the internal circuit 104 and an external circuit (not shown). Each scan cell 102 has a scan data line 10
5, scan-in SI to scan-out SO
Serially connected up to and forming a scan path. The clock from the clock CLK is the clock line 10
It is supplied to each scan cell 102 via 6 and used for shift register operation and operation for fetching external input data and internal output data. The scan data is given from the scan-in SI, sequentially propagates through the scan cells 102 via the scan data line 105 in synchronization with the clock from the clock CLK, and is output from the scan-out SO. Also, the clock is the clock CLK
From the scan line 1 to the scan-in SI through the clock line 106, and each scan cell 1
02 in sequence.

In the configuration as described above, the internal circuit 10
It is possible to perform a test such as giving arbitrary data from the scan-in SI to 4 and taking out the operation state of the internal circuit 104 through the scan-out SO.

FIG. 2 is a block diagram showing in detail the area 103 surrounded by the dotted line in FIG. As shown in FIG. 2, the external input Ein1 connected to the outside of the LSI chip 101 is connected to the internal circuit output Iout1 connected to the internal circuit 104 via the scan cell 102 (A). Similarly, the external input Ein2 connected to the outside of the LSI chip 101 is connected to the internal circuit 104 via the scan cell 102 (B) to output the internal circuit Iou.
connected to t2. The flip-flops 203 and 204 are of a general-purpose type, and each clock input terminal C is fed from the clock CLK through the clock line 106.
The clock is connected. External input Ein1, Ein2
Are scan cells 102 (A) and 102, respectively.
It is input to one input terminal of the selector circuits 207 and 208 of (B). Data from the data output terminals Q of the flip-flops 203 and 204 are input to the other input ends of the selector circuits 207 and 208, respectively. The selector circuits 207 and 208 select the input data based on the control signal CS1 and output the internal circuit outputs Iout1 and Iout1, respectively.
Send to Iout2. The data output terminal Q of the flip-flop 203 is connected to the scan data line 105 (C) connected to the scan-out SO side, and its output is sent as scan data. On the other hand, the data output terminal Q of the flip-flop 204 is connected to the scan cell 102.
It is connected to the scan data line 105 (b) connected to the input terminal of the selector circuit 205 of (a), and sends the scan data. Scan data flip-flop 203,
The outputs of the selector circuits 205 and 206 are input to the data input terminal D of 204, respectively. Selector circuit 2
Reference numerals 05 and 206 each have a selector circuit 2 at one input end.
The outputs of 07 and 208 are connected, and the scan data from the scan data lines 105 (b) and 105 (a) are input to the other input ends. The selector circuits 205 and 206 are
Select one of the two inputs based on the control signal CS2,
It is applied to the data input terminal D of the flip-flops 203 and 204.

The operation of the above-described structure will be described below.

When the internal circuit 104 is normally operated,
The selector signals 207 and 208 select external inputs Ein1 and Ein2 by the control signal CS1, and the selector circuits 205 and 206 select selector circuits 207 and 208 by the control signal CS2. As a result, the data given to the external inputs Ein1 and Ein2 from the external circuit are
As it is, it is transmitted to the internal circuit outputs Iout1 and Iout2 and taken into the internal circuit 104. At this time, the flip-flops 203 and 204 operate with the clock supplied to the clock input terminal C through the clock line 106. The data from the data output terminals Q of the FFs 203 and 204 are sent to the scan data lines 105 (c) and 105 (b). Since the selector circuits 205 and 206 do not select the scan data lines 105 (c) and 105 (b), the scan path is not formed and the scan data is not propagated. In this case, the flip-flops 203, 2
04 performs an operation of constantly updating the latest data from the external inputs Ein1 and Ein2 by the clock from the clock line 106.

On the other hand, in the test mode, the control signal CS
1, the selector circuits 207 and 208 select the flip-flops 203 and 204, and the control signal CS2 causes the selector circuits 205 and 206 to select the scan data line 1.
05 (b) and 105 (a) are selected. As a result, the data input terminal D of the flip-flop 204 is connected to the scan data line 105 (a) on the scan-in SI side, and the data output terminal Q is connected to the flip-flop from the scan data line 105 (b) via the selector circuit 205. 203
Is connected to the data input terminal D of. In addition, the data output terminal Q of the flip-flop is directly scanned out S
It is connected to the scan data line 105 (c) on the O side. In this way, a scan path is formed that connects each flip-flop of all scan cells 102 through scan data line 105 from scan-in SI to scan-out SO. As a result, each flip-flop of the scan cell 102 has the clock line CLK through the clock line 106.
Scan data in synchronization with the clock supplied to
It propagates from the scan-in SI to the scan-out SO via the scan data line 105.

During this operation, the flip-flop 20
The transmission data from the data output terminals Q of the reference numerals 3 and 204 are transmitted to the scan data line 105 and the selector circuit 2
07 and 208 and internal circuit outputs Iout1 and Iout2
Through, it is also input to the internal circuit 104.

On the other hand, the flip-flop in the scan cell 102 is supplied with a clock from the clock CLK through the clock line 106, but the clock propagates from the scan-out SO side toward the scan-in SI side. As the clock propagates through the clock line 106, it naturally causes a delay time.

That is, the flip-flops 203 and 204
For example, the clock applied to the clock input terminal C of the flip-flop 203 is delayed with respect to the clock applied to the clock input terminal C of the flip-flop 203. That is, when the data at the data output terminal Q of the flip-flop 204 is fixed, the flip-flop 203 is after the previous data is fixed by a clock faster than that.

Therefore, the data from the data output terminal Q of the flip-flop 204 is transferred to the scan data line 10
5 (b) and the selector circuit 205, the clock is input to the flip-flop 203 until it is propagated to the data input terminal D of the flip-flop 203 and the input data to the data input terminal D of the flip-flop 203 is determined. There is no. That is, there is sufficient time close to one cycle of the clock until the next clock arrives at the flip-flop 203.

When the next clock propagates through the clock line 106, it propagates to the flip-flop 203 earlier than the flip-flop 204. At this point, the flip-flop 203 fetches the data at the data input terminal D and outputs the data. Output to the output terminal Q. This data is propagated to the next stage through the scan data line 105.

This clock propagates to the flip-flop 204 later than the flip-flop 203. Therefore, at the time when the flip-flop 204 fetches the next data at the next clock and outputs the next data to the data output terminal Q, the flip-flop 203 has determined the previous data. Therefore, the operation of this clock at this point does not directly affect the operation of the flip-flop 203.

That is, by reversing the flow direction of the scan data on the scan data line 105 and the flow direction of the clock on the clock line 106, the clock for passing the data is made to be more than the clock for receiving the data. Is also delayed. As a result, the shift register operation of the scan path can be performed as the initial purpose of propagating the data one stage of the flip-flop every clock.

FIG. 3 is a schematic block diagram showing an application example of the present invention. As shown in FIG. 3, the LSI chip 101 has an R
The OM 301, the RAM 302, and the macro cell 303 are arranged. The scan path 304 connected to the scan-in / out terminal Si / o serially connects these functional areas. Scan-in /
By propagating the clock in the direction opposite to the sending direction of the scan data input / output from the out terminal Si / o, the scan data on the scan path can be reliably transferred.

As described above, by making the flow of the scan data and the flow of the clock reverse to each other, in order to prevent the malfunction due to the clock skew during the shift register operation of the scan circuit, the clock is multiphased. No countermeasure is required, and the shift register operation can be sufficiently performed using an ordinary flip-flop having a small circuit area. Therefore, the area of the scan circuit including the clock wiring region can be minimized.

In the above embodiment, the delay time on the upstream side and the downstream side of the clock flow is obtained by the natural delay time of the clock line 106. However, in order to increase the delay time, a buffer is required. It is also possible to interpose a circuit element such as, and the same effect can be obtained.

[0044]

As described above, according to the clock signal circuit of the present invention, when data is supplied to the flip-flop that operates as a shift register with a single-phase clock, the clock is supplied in the direction opposite to the data flow. The operation of the shift register can be ensured, malfunction due to clock skew can be reliably prevented with a simple configuration, no additional wiring or elements are required, and the chip area is economically increased without increasing the chip's intended purpose. Can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a clock signal circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a main part of the configuration of FIG.

FIG. 3 is a schematic configuration diagram showing an application example of the present invention.

FIG. 4 is an explanatory diagram of an example of a conventional clock signal circuit device.

FIG. 5 is a block diagram of a flip-flop having a multi-phase clock configuration used in another example of the conventional clock signal circuit device.

FIG. 6 is a block diagram of a general shift register.

FIG. 7 is a timing chart explaining an operation when a clock skew occurs in the configuration of FIG.

FIG. 8 is a timing chart illustrating an operation when there is no clock skew in the configuration of FIG.

[Explanation of symbols]

 101 LSI chip 102 Scan cell 104 Internal circuit 105 Scan data line 106 Clock line 203, 204, 205, 206 Flip-flop 207, 208, 209, 210 Selector circuit 301 ROM 302 RAM 303 Macrocell 401 Chip 402 Board F1, F2 Flip-flop

Claims (1)

[Claims] 1. A plurality of scan cells each having a clock-synchronous flip-flop, the flip-flops being connected in series based on a control signal to operate as a serial shift register. A clock line is arranged along the column of the shift register, and one end of this clock line on the data output side as the serial shift register is arranged to propagate the clock in the direction opposite to the data propagation direction in the shift register. Scan circuit with the clock input terminal.