JPH06283670A - Integrated circuit device having bump for power supply bus on active circuit part - Google Patents

Abstract

PURPOSE: To reduce the impedance of a power supply path, and minimize noise caused by the power supply path, by arranging a plurality of metal protrusions on a mutual connection metal layer covering bonding pads on a semiconductor chip. CONSTITUTION: Bonding pads 21p and a protective oxide layer 26 are formed on a silicon layer 24 on the surface of which an active circuit is formed. A window is opened on the upper surface of the bonding pad 21p of the protective oxide layer 26. An interconnection metal layer 27 is buried in the window and covers the protective oxide layer 26. On the metal layer 27, metal protrusions 28p and additional metal protrusions 30 rp are formed at specified intervals, and electrically connected with the metal layer 27. Solder caps 29p are formed on tops of the protrusions 28p, 30 rp. The additional solder caps 30 rp are desirably formed above the active circuit part of the silicon layer 24 surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly, to those having a power bus formed on a chip.

[0002]

Large scale integrated circuit (VL)
One of the problems facing designers of SI) is how to reduce the noise generated on the power bus on the chip. Many factors contribute to the noise on such power buses. For example, one of such factors is switching in a high speed output buffer circuit. As the driving performance of the output buffer circuit is improved, the change in the transient state becomes faster, and the parasitic inductance associated with the connection between the buffer output circuit and the power supply bus increases, which causes noise. Other conspicuous factors are chip size and refresh current. Larger chips for large capacity memory devices employ longer on-chip power buses and therefore also increase inductance. The dynamic RAM device, (the 16 megabit ^{DRAM, 2 24} memory cells are incorporated) DRAM large current for each refresh period required is for the ground _{(V ss)} for the power supply _{(V dd)} Causes a large voltage drop on the bus.

Designers have attempted to minimize noise on the on-chip power bus in various ways. For example, an output buffer circuit modified to operate in a staggered manner minimizes the noise voltage, which may be referred to as the "pollution source voltage." Further, for example, if the output buffer circuit is arranged near the power supply pad along the periphery of the silicon chip, the current traveling distance becomes short, and the power supply bonding pad and the lead finger of the lead frame are connected. When the wire bonding is shortened, the inductance is reduced.

[0004]

[Means for Solving the Problems] 16 Mbit DRA
The M design calls for new techniques to further reduce noise on the on-chip power bus. Therefore,
One object of the present invention is to provide an integrated circuit constructed to minimize noise on the power supply bus. Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the drawings and the following description.

One of the integrated circuit devices is disclosed herein as the present invention. The device of one embodiment of the present invention includes a semiconductor chip having an electrical circuit connected to a bonding pad. A metal layer covers the bonding pad and a metal bump is connected to the metal layer. The metal bump receives power there for the electrical circuit. The method of the present invention allows a designer to form a power bus in a metal layer. This metal layer may be laid over the active circuit on the semiconductor chip.

[0006]

FIG. 1 is a top view showing an integrated circuit device according to the prior art. For a VLSI designer, a method of manufacturing an integrated circuit device by connecting a semiconductor chip to a lead frame by wire bonding is shown. It was well known. The integrated circuit device 9 includes a gate array and a DRA.
As long as it is formed on the semiconductor chip 10 like M, any type of MOS device may be used.
The active circuit device of the semiconductor chip 10, not shown here, corresponds to the corresponding bonding pad 1 for external connection.
It is connected to 1a-11p. In a DIP type package, typically 16 bonding pads 11 made of aluminum are provided. The bonding pad 11 is usually arranged along the periphery of the semiconductor chip 10. The wire bond 12 connects the lead finger 13 and the bonding pad 11. The wire bond 12 is typically made of gold. The chip 10 is integrally sealed together with a part of the wire bond 12 and the lead finger 13 with a material such as plastic. The integrated circuit device 9 is typically mounted on a printed circuit board.

FIG. 2 is a partial side view of the end portion of the integrated circuit device 9 near the bonding pad 11p.
The semiconductor chip 10 includes a silicon layer 14 and a protective oxide layer 1.
6, and formed by the pix 17. Active circuitry is provided in the silicon layer 14 according to known techniques. As shown in the figure, aluminum bonding pads 11p are laid on the upper surface of the silicon layer 14. Structurally, the protective oxide layer 16 is a silicon layer 14
And so as to cover the upper surface of the bonding pad 11. The pix 17 is applied so as to cover the protective oxide layer 16. The device was etched through the pix 17 and protective oxide layer 16 to form the window 1
8p is formed on the surface of the bonding pad 11p. In many cases, the semiconductor chip 10 is mounted on a chip fixing base 15 for connection with a lead frame.
One end of the wire bond 12p is connected to the lead finger 13p. The other end of the wire bond 12p passes through the window 18p and is connected to the bonding pad 11p. The dotted line in FIG. 2 indicates the sealing member.

The integrated circuit device 9 of FIGS. 1 and 2 receives an externally supplied power source. This external power is received by connecting the lead finger to a power source. Power is distributed from the power supply to the lead fingers, then wirebonds, and via the bond pads, and is widely distributed across the chip. It is a ground potential _{V ss} and usually + 5V
A positive potential of V _dd is supplied through separate lead fingers. For example, in FIG. 1, V _ss may be connected to the lead finger 13a, and V _dd may be connected to the lead finger 13p.

FIG. 3 is a side view showing a preferred embodiment of the present invention. Shown here is one end of a semiconductor chip 20, which is similar to one end of the integrated circuit device 9 of FIG. On the silicon layer 24, the bonding pad 21p and the protective oxide layer 26 formed thereon are deposited in the usual manner. The protective oxide layer 26 and the bonding pad 21p are covered with an interconnect metal layer 27 (in the protective oxide layer 26, the interconnect metal layer 27 reaches the bonding pad 21p and forms an electrical connection. Etching process is performed). The metal bump 27 is formed on the interconnect metal layer 27 on the bonding pad 21p.
p is on. The metal bump 28p has a solder cap 29p on the top thereof.

The interconnect metal layer 27 is an additional metal layer overlying the protective oxide layer 26 of the semiconductor chip so that, in this embodiment, the locations of the power distribution welding pads are different. Interconnected. In this embodiment, the corrosion resistant moisture resistant material is formed of a three layer metal system, as shown in FIG. Such a three-layer metal-based interconnect metal layer 27 includes a first
A layer 27a of chrome or tantalum is present as a layer, which adheres to the protective oxide layer 26 and the welding pad 21p and acts as a connecting layer. Then, as the second layer, there may be a thick layer 27b of nickel or copper that minimizes the resistance and provides good step coverage. The third layer is a surface layer 27c, with a corrosion resistant metal such as gold or palladium on top. The interconnect metal layer 27 is also referred to as a "barrier metal" layer because it also acts as a diffusion barrier. Combinations of various barrier metals are suitable for coating the aluminum weld pad 21p and other exposed metal portions (not shown) of the tip 20. Properties of interest include adhesion of the protective oxide layer 26 to the aluminum weld pad 21, stress resistance, process tolerance and selectivity, thickness, cost, and the like. Adhesive metals are chrome, titanium, tungsten titanium (T
I: W). Acts as a barrier to aluminum, that is, migration of aluminum
Nickel and copper are the ones that prevent the above, and are inexpensive enough to provide good step coverage with sufficient thickness along the chip surface. Gold is a good choice for the surface layer as it can reduce corrosion and other reactions.

In the preferred embodiment herein, the interconnect metal layer 27 is 1-KA Cr, 5-KA in terms of ease of operation and process steps in accelerated life temperature testing.
It is composed of Cu and 5-KA Au. These metals may be deposited by a low pressure sputtering process with a single stage vacuum pump to prevent contamination and oxidation at the contact surfaces. Conventional optical pattern drawing by reversal photoresist and contact transfer is also suitable. The chemical etching of gold and copper is carried out by the corrosive iron cyanide in the presence of the ammonium iodide / iodine mixture in the chrome. The laminated thickness of the multilayer metal patterned for protection from activation is on the order of about 13 μm (0.5 mils) on either side of the bonding pad 21p. This is an aluminum bonding pad 21
It serves to protect p from the reaction of the etching process.

Referring again to FIG. 3, the metal bumps 28p electrically connected to the interconnect metal layer 27 serve as connecting means for connecting the chip 20 to an external power source. Such connection arrangements and the devices in which they are employed belong to the known technique of flip-chip interconnection. Such flip-chip interconnect devices are described in an article entitled "Assembling Multiple Chips with Flip-Type Integrated Circuits", co-authored by the present inventors. This article is the 12th issue of December 1989 concerning parts, mixed parts and manufacturing technology of IEEE Transactions.
It is published in Volume 4. The metal bump 28p is shown in FIG.
As shown in the above embodiment, it may be provided with a solder cap 29p and may be any mixture containing copper, or just solder. The solder cap 29p is
Reflow connection is also possible. The raised object 28p may be formed by copper plating. The copper thin film is sputtered on the integrated circuit 20 between + 05-KA and 10-KA. The ridge plating window is drilled using 25-50 μm thick dry photoresist, which is often available. In order to achieve a bump height of 85-100 μm, it is preferred to overlay the photoresist layers in two layers, as is already known. The solder cap 29p attached to the raised object 28p is plated immediately after copper plating. Solder plating component is 10 tin 90
It is a boron fluoride solution of lead. The reason for setting this component ratio is
Not only can this component ratio be immediately adjusted, but 60 tin 4
This is because a remelting temperature higher than that of a solder plating component such as 0 lead solder can be achieved. By such solder plating, it is possible to cover the resist with solder up to 13 μm in an umbrella shape.

Interconnect metal layer 27 and solder cup 29
The entire process for forming the metal bumps 28 with an arrow can be described as follows. Barrier metallization resist coating and patterning are applied. The barrier metal is etched. Apply copper underlayer. A thick resist for copper undercoating is applied and patterning is performed. Apply copper bump plating. Plate the solder cup. Strip the thick resist. An etching process is performed on the copper undercoat. Then, cleaning is performed. Forming an interconnect metal layer that is connected to the bond pads advantageously results in the formation of additional metal bumps. Thus, one for one bonding pad
One or more electrical connections are possible. FIG. 4 is a side view of the semiconductor chip 20 of FIG. 3, showing an additional bump 30rp. The additional ridges 30rp are interconnect metal layers 27.
It is connected to the. The additional ridges 30rp may be conveniently located to overlie the active circuit area of the integrated circuit device 20. A protective oxide layer 26 protects the active circuitry of integrated circuit 20 from electrical signals via additional ridges 30rp. The utility of having additional ridges overlying the active circuit area is a notable advantage and will be discussed later. The two metal bumps 30 of FIG.
Regarding the rp and 28p, the arrangement interval between the raised objects is of concern because the pattern accuracy becomes a problem when the clearance between the raised objects is smaller than the thickness of the resist used. is there. Desirably, the diameter of the ridges is equal to or larger than the height of the ridges, and the gap between the ridges is equal to or larger than the diameter of the ridges. Therefore, in the embodiment of FIG. 4, two metal bumps 28p, 3
0 rp has a diameter of about 100 μm and a height of 85 μm, and the distance between them is about 100 μm.

FIG. 5 is a top view of the additional raised integrated circuit device of FIG. The additional ridge 30rp is closer to the center of the chip 20 than the ridge 28p and covers the active circuit area. Additional bump 30rp
Are connected to the ridges 28p by an interconnect metal layer 27. External power is provided by the interconnect metal layer 27 through both of the two ridges 28p, 30rp as shown in FIGS.
Can be conveniently provided for the active circuit of the integrated circuit device 20 of FIG. This outstanding advantage allows the semiconductor chip to be designed with constraints around the circuit itself, rather than constraints around the bond pads. With respect to the buffer circuit, the layout can be determined from a deep consideration from the standpoint of circuit design, rather than from the requirement from the peripheral bonding. The on-chip power bus is formed by patterning the interconnect metal layer 27, and
Easily designed by patterning metal bumps. Thus, a wider, thicker, and on-chip power bus made of metal with lower resistance than usual is possible.
At multiple points along the length of the power bus, it is possible to make contact at the current distribution points, and even direct contact. Then, it is convenient that wire bonding can be eliminated. Thick, wide power buses will have lower resistance, smaller inductance, and even minimal voltage drop, which reduces noise while improving device performance.

FIG. 6 is a top view of integrated circuit device 40, showing the pattern and placement of interconnect metal layers and ridges. Of course, any pattern or arrangement that the designer considers suitable can be adopted. Two power buses 4
1, 42 supply V _ss and V _dd to the electrical devices of the semiconductor chip 43, respectively. The power bus 41 is made of a pattern embedded in the interconnect metal layer of the device 40, and by way of example only, two connecting pieces 4 are provided.
It is composed of 1a and 41b. Two pieces 41a, 4
Connected to 1b are metal bumps 41c, 41
d and 41e. Device 4 as described above
The protective oxide layer of 0 separates the two pieces 41a and 41b from any circuits in the underlying layer of the chip 43 by an etching process. Connection is made. The V _dd power bus 42 includes interconnect metal strips 42a, 42b, 42c, 4 and 4.
It consists of 2d. Metal bumps 42e, 42f, 42g, 4
2h and 42i are connected to the metal piece 42. Since it is patterned, the pieces 41 and 42 do not come into contact with each other and do not cause a short circuit. From the designer's perspective, the raised power bus of integrated circuit device 40 as shown in FIG. 6 would be formed as follows. Through the electrical model, the path of the power bus is determined to satisfy the best noise performance. Place bumps where necessary. Interconnect metal layers are designed to interconnect the bumps and bond pads, and also the power bus and bond pads. Form a pattern in the interconnect metal. Form a photoresist pattern for the bumps. Thus, in applications such as DRAM designs, designers may, from a design perspective, place bumps, interconnects, as opposed to placing output buffers near bond pads located on the periphery of the chip. It is permissible to place the output buffer at the most convenient location for external power supply to the desired point via the metal or bonding pad.

[0016]

The present invention has several other advantages.
It is possible to place metal bumps on existing integrated circuits with bonding pads without requiring redesign of the circuit in question. Stress in the chip can be minimized by placing the ridge near the center of the chip. The stress on the metal ridges can be minimized by placing multiple ridges on the chip.
The use of interconnect metal layers allows for bus placement from one end of the chip to the other without additional use of a silicon utilization surface, thus minimizing bus interconnection. The device assembly output is increased by reducing the failure rate due to the additional ridges. The processing steps required to form an interconnect metal layer like that on the protective oxide layer of an integrated circuit act like a screening operation for chips damaged by protective oxidation. Defective chips are sorted in-house, improving product reliability for customers.

Although the present invention has been described with reference to the preferred embodiments, the description herein is merely illustrative and should not be construed as a limiting concept. Many modifications to the details of the embodiments of the invention, including additional embodiments of the invention, will be apparent to those of ordinary skill in the art to which the description herein refers, and It should also be confirmed that it can be produced by the person. Similar modifications in additional embodiments are expected to be within the spirit and true scope of the invention as set forth in the following claims.

<Other Disclosure Items> 1. The IC device consists of: A semiconductor chip having an active circuit formed on a surface thereof. A terminal in an electrical contact with an active circuit for the purpose of transferring power to the active circuit. A hole in the antioxidant layer that covers the terminal such that an electrical connection is made to the terminal through the hole. A patterned metal layer that covers the oxide layer and active circuitry and fills the holes that carry power to the terminals. Multiple receiving metal embankments connected to a patterned metal layer. 2. The patterned metal layer of the device of the preceding paragraph consists of: Metal adhesive layer. A metal barrier layer overlying the metal adhesion layer. A metal passivation layer overlying the metal barrier layer. 3. The semiconductor chip power trunk line having an active circuit surface having terminals and an opening exposing the terminals, and the insulating layer covering the active circuit surface are formed of the following. In order to transfer power to various terminals, a strip-shaped metal piece covering the insulating layer, which is connected to various terminals of the semiconductor chip through the openings, and a plurality of strip-shaped metal layers bonded to receive the power Metal embankment. 4. The power main line of the preceding paragraph including the strip-shaped metal piece is composed of the following. Metal adhesive layer adjacent to various terminals. A metal semiconductor layer on the adhesive layer and a metal corrosion layer on the semiconductor layer. 5. In the power trunk line of the preceding paragraph, the metal adhesion layer is chrome, the metal semiconductor layer is copper, and the metal corrosion layer is gold. 6. The packaged semiconductor device consists of: A semiconductor chip that has an active circuit surface that mounts terminals that have been processed in the exterior material. An insulating layer that covers the active circuit surface of a semiconductor chip with holes above the terminals. A power supply trunk line covered with an insulating layer that is in electrical contact with each individual terminal through a hole, the terminal having a plurality of metal embankments bonded to a power receiving terminal that penetrates through an exterior material. 7. The packaged semiconductor device of the preceding clause, wherein the power supply trunk comprises a strip of patterned metal layer.

[Brief description of drawings]

FIG. 1 is a top view showing a conventional integrated circuit.

2 is a partial side view of an end portion of the integrated circuit device 9 of FIG. 1, showing a vicinity of a bonding pad 11p.

FIG. 3 is a side view showing a preferred embodiment of the present invention.

FIG. 4 is a side view of another preferred embodiment of the present invention.

FIG. 5 is a top view of the device of FIG.

FIG. 6 is a top view showing patterns and arrangements for interconnect metal layers and metal bumps.

FIG. 7 is a side view schematically showing a three-layer metal-based barrier metal in the interconnect metal layer shown in FIG.

[Explanation of symbols]

 11 (11a ... 11p) Bonding pad 18p Window 20 Semiconductor chip 21p Bonding pad 24 Silicon layer 26 Protective oxide layer 27 Interconnect metal layer 28p Metal bumps 29p Solder cap 30rp Additional metal bumps

Claims (1)

[Claims] 1. A semiconductor chip having an active circuit formed on a surface thereof, a power supply terminal electrically connected to the active circuit and supplying power to the active circuit, and an electric power supply to the power supply terminal covering the power supply terminal. A protective oxide layer that is provided with a window so as to secure the electrical connection, an interconnect metal layer that covers the protective oxide layer and the active circuit, and fills the window for supplying power to the power supply terminals; An integrated circuit device comprising a plurality of metal bumps connected to an interconnect metal layer for receiving a supply.