JPH06283386A - Chip component - Google Patents

Abstract

PURPOSE:To suppress crosstalk between adjacent elements by providing a ground conductor and an electrode for taking out the ground conductor adjacent to each passive element. CONSTITUTION:A square insulation substrate 11 with a plurality of recessed parts is provided at both opposing edges and a plurality of lower layer conductors 12 are provided in the direction of width on the insulation substrate 11 so that both edge parts reach the recessed part. The lower layer conductor 12 is connected to a rear surface electrode 17 via a through hole. Further, an upper layer conductor 14 is formed on a thick-film dielectric 13 formed on the lower layer conductor 12. Then, a ground conductor 18 is formed similarly as the lower layer conductor 12 and then an electrode 19 for taking out ground conductor for grounding the ground conductor 18 is provided, thus reducing the crosstalk between adjacent passive elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component for noise suppression in electronic circuits, especially digital circuits.

[0002]

2. Description of the Related Art Generally, as a noise countermeasure for electronic circuits, particularly digital circuits, (1) a method of using a capacitor,
(2) Method using ferrite beads or coil,
(3) There is a method of using a resistor. The case of using a capacitor, which is the most typical noise removal method, will be described below.

As a noise removal method using a capacitor, a method is known in which a signal conductor path and a ground conductor path are connected via a capacitor to allow noise to escape to the ground conductor and be removed. As a capacitor to use,
For example, there is a chip type three-terminal capacitor shown in FIG. FIG. 4B shows an equivalent circuit diagram of the chip type three-terminal capacitor. The chip-type three-terminal capacitor has signal electrodes 1 and 2 at both ends and a ground electrode 3 at the center.

Furthermore, a chip-type three-terminal capacitor array in which the chip-type three-terminal capacitors are networked to improve the packaging density has been partially put into practical use. FIG. 5 (a),
(B) shows a perspective view and an equivalent circuit diagram of the chip type three-terminal capacitor array, respectively. In the figure, 4 is an insulating substrate, 5 is an electrode, and a plurality of capacitors are formed on the insulating substrate 4 together with a dielectric. 6 is a protective coat. This chip-type three-terminal capacitor array is connected through solder in parallel to the ground conductor path and the signal conductor path that are aligned like bus lines as shown in FIG. 5B, for example. In addition, in FIG. 5B, 7 is a capacitor part.

[0005]

However, in the chip type capacitor array configured as described above, noise is generated in the adjacent element and the adjacent terminal due to the influence of electrostatic induction and electromagnetic inductive coupling due to mutual capacitance and mutual inductance between the elements. May be induced. This phenomenon is generally called crosstalk, and its influence is greater as the signal frequency becomes higher. Further, in recent years, rapid chip formation has been advanced in order to meet the demand for higher density, and particularly, in the case of array chips, there is a tendency to further reduce the interval between adjacent elements and promote crosstalk.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide an excellent chip component in which crosstalk between adjacent elements is suppressed.

[0007]

In order to achieve the above object, the chip component of the present invention comprises a rectangular insulating substrate having a plurality of recesses or protrusions at opposite end edges thereof, and a surface to a back surface of the insulating substrate. A plurality of terminal electrodes formed, and a plurality of passive elements formed on the surface of the insulating substrate so as to be connected to the terminal electrodes, and a ground conductor adjacent to each passive element on the insulating substrate, and a ground A conductor take-out electrode is provided.

[0008]

With this structure, the ground conductor is interposed between the capacitor elements, and the ground conductor is grounded by the ground conductor take-out electrode, so that the crosstalk between the elements is significantly reduced. As a result, it is possible to easily realize an array of passive components, which has been difficult to form into chips due to crosstalk, and to realize excellent chip components that can suppress crosstalk even in a high frequency region.

[0009]

Embodiment 1 A first embodiment of the present invention will be described below with reference to the drawings. 1 (a), (b),
(C) is a perspective view, a sectional view, and an equivalent circuit diagram of the chip type three-terminal capacitor array in the first embodiment of the present invention. Note that FIG. 1B shows A of FIG.
It is a sectional view of the -B side. In FIG. 1, 11
Is an insulating substrate such as a rectangular alumina having a plurality of recesses at opposite end edges facing each other, 12 is a plurality of lower layer conductors connected so that both ends reach the recesses in the width direction on the insulating substrate 11, It is connected to the back surface electrode 17 through the through hole. 13 is a thick film dielectric formed on the lower layer conductor 12, 14 is a common upper layer conductor formed on the thick film dielectric 13, and crystallized glass 15 is provided so as to cover the thick film dielectric 13 and the upper layer conductor 14. Is forming. A protective coat 16 covers the crystallized glass 15. Normally, when a thick film dielectric is used, a two-layer coating of crystallized glass and amorphous glass is used to ensure reliability. Recently, however, a resin coating with particularly high reliability has been developed. 14
A resin coat may be directly applied on the top. Further, although the insulating substrate having the through hole is used in this embodiment, it is not particularly limited. Further, the insulating substrate may be formed with a convex portion instead of the concave portion, and the lower layer conductor may be formed on the convex portion.

Reference numeral 18 is a ground conductor formed in the same manner as the lower layer conductor 12, and reference numeral 19 is a ground conductor take-out electrode provided for grounding the ground conductor.

In FIG. 1C, a terminal 1 and a terminal 6, a terminal 2 and a terminal 7, a terminal 3 and a terminal 8 and a terminal 4 and a terminal 9 respectively form a three-terminal capacitor. Terminal 2
-7, the terminals 4-9 are lower conductors, the terminals 1-6, the terminals 3-8, and the terminals 5-10 are ground conductors. That is, the ground conductor is provided adjacent to each lower layer conductor.

Generally, as a method of reducing crosstalk, (1) shorten the parallel running distance between two signal lines, (2) increase the distance between two signal lines,
(3) It is known that a ground line is provided between two signal lines to be grounded, etc. In this embodiment, (1) and (3) are adopted in a chip type three-terminal capacitor array. is there.

The chip-type three-terminal capacitor array configured as described above has a structure in which the ground conductor is formed between the adjacent signal lines and is grounded by the electrode for extracting the ground conductor. It is possible to realize a chip-type three-terminal capacitor array that can be used even in a high frequency region.

The insulating substrate 11 is used in this embodiment.
Although two 3-terminal capacitors are built in above, one or multiple elements may be used in some cases.

(Embodiment 2) A second embodiment of the present invention in which the present invention is applied to the present chip resistor array will be described below with reference to the drawings.

2 (a), 2 (b) and 2 (c) are a perspective view, a sectional view and an equivalent circuit diagram of the chip resistor array, respectively. Note that FIG. 2B shows a cross-sectional view of the CD plane of FIG. In FIG. 2, 21 is an insulating substrate made of alumina or the like, and 22 is a conductor formed on the insulating substrate 21, which is connected to the back surface electrode 27 through a through hole. Reference numeral 23 is a resistor provided so as to partially overlap the conductor 22, 24 is a protective coat for protecting the resistor, 25 is a ground conductor, and 26 is a ground conductor extraction electrode.

Here, in FIG. 2B, the terminal 2-6
And between terminals 4-8 are ground conductors and are formed adjacent to the resistor.

The chip type resistor array configured as described above can bring about the same effect as that of the first embodiment.

(Embodiment 3) A third embodiment of the present invention in which the present invention is applied to a chip type ferrite bead array will be described below.

FIG. 3 is an equivalent circuit diagram of a chip type ferrite bead array showing a third embodiment of the present invention. In FIG. 3, a ground conductor is provided between the terminals 2-5 and is formed adjacent to the bead element 31.

The chip type ferrite bead array configured as described above can bring about the same effect as that of the first embodiment.

[0022]

As described above, according to the present invention, a ground conductor and a ground conductor lead-out electrode are provided adjacent to each passive element and grounded to reduce crosstalk between adjacent passive elements. be able to. As a result, it is possible to easily realize a chip of a passive element array, which has been difficult to achieve in the past, and it is possible to provide and realize a chip type array of passive elements having a small crosstalk even in a high frequency region.

[Brief description of drawings]

1A is a perspective view of a chip-type three-terminal capacitor array according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the chip-type three-terminal capacitor array taken along the line AB of FIG. (C) is an equivalent circuit diagram of the chip type three-terminal capacitor array in the embodiment.

2A is a perspective view of a chip-type resistor array according to a second embodiment of the present invention, FIG. 2B is a cross-sectional view of the chip-type resistor array taken along the CD plane of FIG. 2A, and FIG. Equivalent circuit diagram of the chip resistor array in the embodiment

FIG. 3 is an equivalent circuit diagram of a chip type ferrite bead array according to a third embodiment of the present invention.

FIG. 4A is a perspective view of a conventional chip-type three-terminal capacitor, and FIG. 4B is an equivalent circuit diagram.

5A is a perspective view of a conventional chip-type three-terminal capacitor array, and FIG. 5B is an equivalent circuit diagram.

[Explanation of symbols]

 11, 21 Insulating substrate 12, 22 Lower conductor 13 Thick film dielectric 14 Upper conductor 15 Crystallized glass 16, 24 Protective coat 17, 27 Backside electrode 18, 25 Ground conductor 19, 26 Ground conductor take-out electrode 23 Resistor 31 Bead element

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Ikeda 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Koji Nishida, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] 1. A rectangular insulating substrate having a plurality of recesses or protrusions on opposite edges thereof, a plurality of terminal electrodes formed from the front surface to the back surface of the insulating substrate, and the terminal electrodes on the surface of the insulating substrate. A chip component having a plurality of passive elements formed so as to be connected to each other, wherein a ground conductor and a ground conductor take-out electrode are provided on the insulating substrate adjacent to each passive element.