JPH06282947A - Picture signal reproducing device - Google Patents

Abstract

PURPOSE:To perform an interpolative correction of data capable of obtaining a visually natural picture to a decoding disabled block at the time of a high- speed reproduction. CONSTITUTION:The interpolative corrections of data X1 to X8 of each line in a X block are performed by using data of lines a7, a8, b1, b2 being adjacent to the X block in regenerated blocks A, B being adjacent to upper and sides of the decoding disabled block X. Thus, a satisfactory corrected picture is attained since the interpolation corrections are performed by using latest data of blocks to the decoding disabled block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal reproducing apparatus such as a digital VTR, and more particularly to an image signal reproducing apparatus capable of reproducing undecodable data of a television moving image signal reproduced at high speed such as search reproduction. .

[0002]

2. Description of the Related Art An orthogonal transform coding system has been known as a technique for compressing and coding an image signal with high efficiency. This is to group the image signals into blocks each having N vertical pixels × M horizontal pixels, perform orthogonal transform such as discrete cosine transform in block units, and perform quantization, entropy coding, etc. on the transformed coefficients. It is something to do.

In such a coding method, coding is performed in block units. Therefore, when high-speed playback such as search playback is performed, if image data is lost, the effect thereof is over a plurality of blocks and the image quality is greatly degraded. Becomes

Conventionally, as a method for interpolating and correcting such error block data at the time of search reproduction to obtain a reproduced image, a frame interpolation method is known in which the error block is replaced only by the image of the previous frame.

FIG. 6 shows a modification operation by the frame interpolation method. If the block X of the frame #n cannot be decoded now, the data of the block X is replaced with the reproduced data of the block A at the same position on the screen in the previous frame # n-1 and reproduced.

[0006]

However, in such a frame interpolation method, when an image moves rapidly or the search speed becomes faster, the error block is replaced with an image completely different from the surrounding blocks in the same field. That is, there was a problem that it was a great visual obstacle.

The present invention has been made in order to solve the above problems, and it is an image signal capable of performing interpolation correction so that an error block gives a visually natural image even during high-speed reproduction. It is intended to provide a reproducing device.

[0008]

SUMMARY OF THE INVENTION According to the present invention, an image signal is blocked for each plurality of pixels and the encoded data is decoded,
An image signal reproducing apparatus for reproducing an image signal, comprising: interpolation means for interpolating the data of the undecodable block by interpolation data generated from a block around the undecodable block by a prescribed method. Can be changed based on the error status of the block adjacent to the undecodable block.

[0009]

According to the present invention, when a block coded image is retouched at the time of search reproduction, interpolation is performed by the data of the block having a small time difference from the non-decodable block, so that a visually natural image retouching is performed. Is done.

[0010]

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a diagram showing an interpolation correction method for undecodable blocks during search reproduction when the present invention is applied to a digital VTR.

FIG. 2A shows a case in which a head mounted on a rotary drum (not shown) performs a helical scan to search and reproduce a track 11 obliquely formed on the magnetic tape 10, and a track 11a indicated by a dotted line. Indicates the head scanning at that time. Further, the shaded portion 11b is an actual reproducible region because the azimuths of the heads match during recording and during reproduction.

FIG. 2B shows a reproduction screen. Capital letter A,
X and B are coding blocks, X is an undecodable block (error block), and A and B are regenerated blocks. In this case, since blocks A and B adjacent to the top and bottom of the error block X are reproduced, interpolation between frames is performed using the image data of the top and bottom blocks A and B instead of the conventional interframe interpolation. Give.

The processing method at that time will be described with reference to FIG. In FIG. 1, uppercase letters A, X, and B indicate coding blocks, as in FIG. 2, and lowercase letters with subscripts indicate image signal lines included in the respective coding blocks X, A, and B. The lines with odd subscripts are the lines of odd fields of the image signal, and the lines with even subscripts are the lines of even fields. For the sake of explanation, the coding block is 8 × 8 in the frame (N = 8, M =
8) It is assumed to be composed of pixels.

It is now assumed that the block X cannot be decoded and the blocks A and B located above and below X on the screen can be decoded. In the reproducing system of the image signal reproducing apparatus according to the present invention, x1 to x4 corresponding to the upper N / 2 = 4 lines of the lines x1 to x8 of the undecodable block X are the top lines of the block X of the lines of the block A. x1, x
Line a, which is the line in the same field closest to 2
7, a8. That is, x1 = a
7, x2 = a8, x3 = a7, x4 = a8.

Also, x corresponding to the lower N / 2 = 4 lines
5 to x8 are similarly replaced by the lines b1 and b2 of the block B which are the lines of the same field closest to the bottom lines x7 and x8 of the block X. That is, x
5 = b1, x6 = b2, x7 = b1, and x8 = b2.

As can be seen from this example, even in the case of a block size of 8 × 8 pixels, the same data in the field in the vertical direction is 3 lines × 8 pixels in width.

FIG. 3 is a diagram showing a circuit configuration example for realizing a block interpolation modifying circuit to which the present invention is applied.

In FIG. 3, an image signal obtained by decoding a block coded signal and then scanning it in raster order is input to an input terminal 201. The input image signal is supplied to the terminal # 1 of the selection circuit 206, and the line delay circuit 20
2, 203, 204, and 205 sequentially delay each line, and branch each delay and supply the delayed signals to the terminals # 2, # 3, # 4, and # 5 of the selection circuit 206.

The selection circuit 206 is connected to the terminal # 3 in a normal state where no modification is made, and outputs a signal delayed by two lines. A line phase signal representing the intra-block phase of the input image signal in units of fields as shown in FIG. 4 is input to the input terminal 208.

Explaining the example of FIG. 1, x1, x
3, x5, and x7 correspond to the line phases 1, 2, 3, and 4 in the odd field, and x2, x4, x6, and x8 correspond to the line phases 1, 2, 3, and 4 in the even field, respectively.
Equivalent to.

The input terminal 207 receives a correction flag signal indicating whether the input image signal as shown in FIG. 4 is in the correction block or not. The line selection circuit 209 generates a line selection signal for selecting the image signal of each delay amount from the modification flag signal and the line phase signal in the relationship shown in FIG.

The line selection signal is corrected by the delay circuit 210 in the delay circuit 210 until the image signal is supplied from the input terminal 201 to the terminal # 3 of the selection circuit 206, that is, after the delay amount is corrected in the path which is not modified. Selection circuit 206
By controlling the connection of the terminals # 1 to # 5, the image signal subjected to the block interpolation modification according to the present invention is supplied to the output terminal 211.

In a device using block coding, a random access memory circuit is often used for decoding processing, conversion of a blocked signal to a raster scanning signal, and the like. When the image signal reproducing method according to the present invention is applied to such a device, it can be realized without adding a dedicated delay circuit by controlling the write or read address of the memory circuit. .

FIG. 5 is a diagram showing a configuration example in which the present invention is realized by address control of a memory circuit. In FIG. 5, reference numeral 302 denotes a random access memory circuit, which stores data input from the input terminal 301, converts the data into a reproduced image signal, and outputs the reproduced image signal from the output terminal 307. 303
Is an address generation circuit, which writes to the memory circuit 302,
Read addresses are generated in a predetermined sequence.

Reference numeral 305 denotes an offset generating circuit for modifying a block according to the present invention, which is generated in accordance with the in-block line phase supplied from the address generating circuit 303 for the block designated by the modifying flag supplied from the input terminal 304. Generate an offset amount for an address. An address addition circuit 306 adds the offset amount of the offset generation circuit 305 to the address generated by the address generation circuit 303 and then adds the offset value to the memory circuit 302.
Supply to the address input of.

Table 1 shows the offset amount with respect to the progressive scan read address when the memory circuit 302 is used as a frame memory, as a relative address in the vertical direction within the frame.

[0027]

[Table 1]

Since it is frame processing, the line phase is x
There are eight types, 1 to x8. Further, j and k are the upper block and the lower block of the error block to be modified, respectively, and represent the distance to the next unmodified block by the number of blocks. As shown in FIG. 2, blocks A and B are blocks X and X, respectively. It is 0 when adjacent.

Here, an example of realizing the image signal reproducing system of the present invention by the read address control is shown, but it goes without saying that it can also be realized by the write address control of the memory.

If a field memory is used as the memory circuit 302, it is sufficient to use only an even or odd one-sided series in the line phase of Table 1 and reduce the offset amount at the time of modification to 1/2. it is obvious. Furthermore, in the present embodiment, the case where the upper and lower blocks of the error block are reproduced has been described, but the other condition that intra-screen interpolation is possible is that the error block is adjacent to the periphery of the error block.
It is also applicable when left, right, or diagonal blocks of this block are being reproduced.

[0031]

As described above, according to the present invention,
Block-coded search By applying intra-field interpolation from neighboring lines to reproduced images on a block-by-block basis, visual correction is natural compared to the interpolation from the previous frame that was used in conventional block-coding. An image is obtained. Therefore, by applying to a VTR or the like using block coding, it is possible to provide an image signal reproducing device that can obtain a good reproduced image against partial loss of data due to high-speed reproduction such as search reproduction.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an interpolation correction method for undecodable blocks of a block-coded image according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an interpolation modification method.

FIG. 3 is a block diagram showing a circuit configuration example for realizing a block interpolation modifying circuit to which the present invention is applied.

FIG. 4 is a diagram showing a relationship between a modification flag signal, a line phase signal, and a line selection signal.

FIG. 5 is a configuration diagram in which the present invention is realized by address control of a memory circuit.

FIG. 6 is a configuration diagram showing a conventional frame interpolation method.

[Explanation of symbols]

 202-205 line delay circuit 206 selection circuit 209 line selection circuit

Claims (2)

[Claims] 1. An image signal reproducing apparatus which reproduces an image signal by decoding the encoded image data by dividing the image signal into a plurality of pixels, the interpolation being generated from a block around an undecodable block by a predetermined method. Image signal reproduction, characterized in that it comprises an interpolation means for interpolating the data of the undecodable block by data, and the predetermined method can be changed based on an error condition of a block adjacent to the undecodable block. apparatus. 2. An image signal reproducing apparatus which reproduces an image signal by decoding the encoded image data by dividing the image signal into a plurality of pixels, wherein the decoding is impossible due to the interpolation data generated by a predetermined method. An interpolating unit that interpolates block data, and an error status detecting unit that detects an error status of an adjacent block of the undecodable block, the interpolation unit interpolating based on a detection result of the error status detecting unit. An image signal reproducing device characterized by performing.