JP2917185B2 - Compressed video decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding moving image data which has been compression-encoded such as a VTR (Video Tape Recorder), and more particularly to a compression apparatus which corrects image disturbance due to a code error as naturally as possible. The present invention relates to a video decoding device.

[0002]

2. Description of the Related Art In an apparatus for compressing the amount of image data and recording it on a recording medium, or transmitting the image data through a transmission path, the image data is divided into small blocks and subjected to orthogonal transform such as discrete cosine transform to reduce energy. A method of compressing a data amount by using a bias toward a frequency component is well known. In such a device, an error correction code is adopted to prevent image distortion due to a code error occurring in the process of recording / reproduction or transmission, and for a device which cannot be corrected, some modification is usually performed on the reproduction side. .

In the case of encoding using orthogonal transform,
The effect of the code error spreads to all pixels in the block. It is difficult to perform effective retouching on such a wide range of pixels by creating retouching values using pixel data around the same screen. Therefore, conventionally, as described in JP-A-3-209998, inter-plane modification in which the entire block is replaced with a modification value created using pixel data of another screen (frame) has been studied.

[0004] However, the retouching between the screens is not effective in a moving scene, resulting in an unnatural image. Conventionally, in this regard, motion detection is performed to correct pixel data used for correction, but this also has limitations for fast-moving images and scene switching, and in order to perform motion correction. Requires a large-scale circuit. Furthermore, replacing an entire block in its entirety means discarding erroneous information in the block.

[0005]

As described above, in the prior art, in an apparatus for reproducing image data compressed and encoded by using an orthogonal transform, correction between screens is performed. There is a problem that an unnatural image is obtained by switching, and no consideration has been given to discarding erroneous information in a block.

[0006] The present invention has been made in view of the above points,
An object of the present invention is to provide a compressed moving picture decoding apparatus that performs more natural correction by utilizing information that is not erroneous in a block.

[0007]

In order to achieve the above object, a compressed moving picture decoding apparatus according to the present invention performs in-plane modification processing in a state of orthogonal transform coefficients before performing inverse transform of orthogonal transform; Means for performing inter-plane modification processing in the state of the pixel data after the inverse transformation, and configured to control which modification is performed according to the degree of error.

[0008]

Since the correction is performed before the inverse transform, the erroneous orthogonal transform coefficients in the block can be utilized. In addition, since in-plane retouching is performed as much as possible, natural retouching can be performed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a block diagram illustrating a configuration of a compressed moving picture decoding device according to a first embodiment of the present invention. Prior to the description of the block diagram of FIG. 1, a digital image compression encoding system used in each embodiment of the present invention will be described with reference to FIGS. First, the image data is divided into blocks of 8 × 8 pixels, and discrete cosine transform is performed for each block. A block 9 shown in FIG. 2 is a block after the discrete cosine transform, and a component f _ij is a discrete cosine transform coefficient of the i-th order in the vertical direction and the j-th order in the horizontal direction (hereinafter, f ₀₀ is a DC (direct current) component, and others are AC (direct current) components. (Referred to as (AC) component). After quantizing each component, the components are rearranged by zigzag scanning as indicated by arrows in the figure, and the AC component is converted into a variable length code assigned to the value on a one-to-one basis. Due to the statistical properties of the image, the energy is concentrated in the low-order components and the high-order AC components are almost zero. Therefore, by assigning a short code to this, the data amount can be compressed.

Next, an error correction product block as shown in FIG. 3 is formed from the DC component and the AC component converted into a variable length code, and is recorded on a recording medium. ID 11 indicating which block on the screen is the data after the synchronization signal 10
After that, the fixed-length DC component 12 and the AC component converted into the variable-length code are continued. The outer correction code 13 is a correction code for adding a code to a code string viewed in the vertical direction.
The inner correction code 14 is a correction code that is added to a code sequence when the code is viewed in the horizontal direction. These make a double correction. The AC component is divided into a fixed address AC component 15 and a variable address AC component 16, and the connection address 17 contains address data indicating where the continuation of the code of the fixed address AC component starts from the variable address AC component.

The embodiment shown in FIG. 1 (and each embodiment to be described later) is an apparatus for reproducing image data from a recording medium recorded by the above-mentioned encoding method. In FIG. 1, the output of a head 1 is an error corrector 2, a variable length decoder 3,
The signal is supplied to an output terminal 7 through an in-plane modifier 4, an inverse discrete cosine transformer 5, and an inter-plane modifier 6. A screen memory 8 is connected to the face-to-face modifier 6. A correction command signal is supplied from the error corrector 2 to the in-plane retouching device 4 and the inter-plane retouching determination circuit 20, and a retouching command signal is supplied from the inter-plane retouching determination circuit 20 to the inter-surface retouching device 6.

In such a configuration, the encoded signal is read from the recording medium by the head 1 and corrected by the error corrector 2. At this time, a correction instruction is issued to a subsequent circuit for a code error that cannot be corrected while an error is detected. The variable length decoder 3 restores a discrete cosine transform coefficient from the corrected variable length code. The code corrected by the error correction product block shown in FIG. 3 is input to the variable length decoder 3. Here, for example, if the code 18 in FIG. 3 is an uncorrectable error, the value of the discrete cosine transform coefficient corresponding to the variable length code including the code 18 in the output of the variable length decoder 3 becomes an error. . In addition, since the code length of the variable-length code including the code 18 is also unreliable, the starting point of the subsequent variable-length code is also unreliable, and until the starting point of the variable-length code is indicated by the next connection address. The values of the discrete cosine transform coefficients corresponding to all the variable length codes (shaded portions in FIG. 3) become invalid. Since the discrete cosine transform coefficients are encoded in the zigzag scan order shown in FIG. 2, all the lower right discrete cosine transform coefficients from the discrete cosine transform coefficients corresponding to the erroneous variable length code become invalid.

The in-plane retouching device 4 receives a retouching command from the error correcting device 2, and performs in-screen retouching processing on these invalid discrete cosine transform coefficients. The inverse discrete cosine transformer 5
The image data of 8 × 8 pixels is restored by the inverse discrete cosine transform from the discrete cosine transform coefficient subjected to the modification processing in the screen. The inter-plane retouching unit 6 performs inter-screen retouching processing using the screen memory 8 to replace all pixel data in the block for which the retouching command has been issued with pixel data of the previous screen. The circuit 20 controls so as to perform the inter-screen modification process only when the discrete cosine transform coefficient of a predetermined amount or more in the block is invalid.

As described above, according to the present embodiment, when there are few invalid discrete cosine transform coefficients in a block, the effective discrete cosine transform coefficients can be utilized.
More natural modification can be performed.

Next, a specific example of the in-plane retouching device 4 in the first embodiment will be described with reference to FIGS. FIG. 4 is a block diagram illustrating an example of the in-plane retouching device 4. As shown in the figure, the output of the variable length decoder 3 is input to one input terminal of the switch circuit 41. The output of the coefficient 0 generator 42 is input to the other input terminal of the switch circuit 41, and the output of the switch circuit 41 is supplied to the inverse discrete cosine converter 5.
Has been entered. Further, a control signal is supplied from the switch controller 43 to the switch circuit 41, and a modification command signal from the error corrector 2 (not shown) is supplied to the switch controller 43.

In such a configuration, when the switch controller 43 receives, for example, a modifying command for the code 18 shown in FIG. 3, the discrete cosine transform coefficient corresponding to the variable length code including the code 18 and the discrete cosine transform coefficient thereafter. The switch circuit 41 is controlled so that the conversion coefficient is replaced with 0.

The output of the switch circuit 41 is shown in FIG. 1
Reference numeral 9 denotes a discrete cosine transform coefficient corresponding to a variable-length code including the code 18 that cannot be corrected. As shown in the figure, all coefficients after the coefficient 19 are replaced with 0 according to the zigzag scan order. As a result, the DC component and the low-order AC component having no error are utilized, and a natural retouched image in which only the high-order AC component is cut can be obtained.

FIG. 6 is a block diagram showing an in-plane modifying unit 4 in a compressed moving picture decoding apparatus according to a second embodiment of the present invention. In this embodiment, in-plane modifying is performed using coefficients of adjacent blocks. To do. The operations of the variable length decoder 3, switch circuit 41, coefficient 0 generator 42, switch controller 43 and inverse discrete cosine transformer 5 in FIG. 6 are the same as those in the first embodiment shown in FIG. In FIG. 6, the output of the switch circuit 41 is a one-block delay circuit 50.
And one block line delay circuit 51. The output of the one-block delay circuit 50 is input directly and through a positive / negative inverter 52 to the modifying coefficient selector 53, and the output of the one-block line delay circuit 51 is also input directly and through the positive / negative inverter 54 to the modifying coefficient selector 53. The output of the coefficient 0 generator 42 is also input to the modifying coefficient selector 53. The output of the modifying coefficient selector 53 is supplied to the other input terminal of the switch circuit 41.

FIG. 7 shows discrete cosine transform coefficients on the screen. This second embodiment shown in FIG. 6, the discrete cosine transform coefficients f _ij of a block 21 caused the uncorrectable errors, discrete discrete cosine transform coefficients v _ij and left neighboring blocks 23 of the upper adjacent block 22 it is intended to modification using the cosine transform coefficients h _ij.

In FIG. 6, a one-block delay circuit 50 delays data so as to obtain a discrete cosine transform coefficient h _ij , and a one-block line delay circuit 51 delays data so as to obtain a discrete cosine transform coefficient v _ij . The modification coefficient selector 53 generates a modification value based on these coefficients and the coefficient 0, and the switch circuit 41 replaces an erroneous coefficient with the modification value.

FIG. 8 shows the output of the switch circuit 41 of the second embodiment. The component at the upper right of the diagonal line in the block has a lower degree in the vertical direction, and the correlation with the upper adjacent block 22 is more likely to be higher. Therefore, v _ij is used. because of a strong likely better correlation with adjacent blocks 23 is to perform modification with h _ij. At this time, in consideration of the fact that the odd-order component is inverted in phase in an adjacent block, the h _ij component in which j is an odd number is used by inverting the sign by a positive / negative inverter 52, and i is an odd v
_{The ij} component is used by inverting the sign by the sign inverter 54.
Further, since the lower right component is considered to have low correlation between both components, the lower right component from the predetermined coefficient is replaced with the coefficient 0.

As described above, according to the present embodiment, more accurate correction can be performed by utilizing the correlation with the adjacent block. In particular, the correlation with the adjacent block such as a vertical edge or a horizontal edge is strong. Image degradation
Effective modification can be performed.

In the second embodiment, the right upper component and the lower left component of the diagonal line are modified with v _ij and h _ij , respectively.
Both may be added at an appropriate ratio according to the order and used. Also, the lower right component has been replaced with a coefficient of 0,
Higher order components may be weakened by applying an appropriate coefficient. Furthermore, in the present embodiment, the coefficients of the upper and left adjacent blocks are used, but by using two one-block delay circuits and two one-block line delay circuits, the modification using the coefficients of the upper, lower, left, and right blocks is performed. Can also.

FIG. 9 is a block diagram showing a main configuration of a compressed moving picture decoding apparatus according to a third embodiment of the present invention. In this embodiment, the DC component in the first embodiment shown in FIG. An example is shown in which modification is performed and the encoding method is adapted to perform block shuffling. This shuffling is to change the order of the blocks in the screen, and even if there is a code error over a plurality of blocks, the positions of these blocks on the decoded screen are dispersed to reduce visual quality deterioration. Things. The configuration and operation of the variable length decoder 3, switch circuit 41, coefficient 0 generator 42, switch controller 43 and inverse discrete cosine transformer 5 in FIG. 9 are the same as those in the first embodiment shown in FIG.
Modification to replace the component with 0 is performed. In FIG. 9, the output of the variable length decoder 3 is also input to the DC component deshuffling device 44,
The C component memory 45 is connected. The output of the DC component deshuffling device 44 is supplied to a negative input terminal of a subtractor 46. A signal is also supplied from the DC component memory 45 to the DC component modified value generator 47, and the DC component modified value generator 47
Is supplied to the positive input terminal of the subtractor 46. On the other hand, a deshuffling and interplanar modifier 24 is connected instead of the interplanar modifier 6 in FIG. The output of the screen memory 8 is not directly input to the deshuffling and inter-plane modifier 24 but is supplied to one input end of the switch circuit 48. The output of the switch circuit 48 is input to the deshuffling and inter-plane modifier 24. I have. The output of the adder 49 is supplied to the other input terminal of the switch circuit 48. The output of the screen memory 8 is provided to one input terminal of the adder 49, and the output of the subtractor 46 is provided to the other input terminal. Is supplied.
A control signal is supplied from the switch controller 43 to the switch circuit 48.

In such a configuration, the deshuffling and inter-plane retouching unit 24 performs deshuffling using the screen memory 8 to restore the order of the blocks shuffled at the time of encoding, and retouching between screens. Perform processing. That is, the screen memory 8 outputs pixel data that has been deshuffled and inter-plane modified. When there is an uncorrectable error in the DC component, the inverse discrete cosine transformer 5 temporarily performs the inverse discrete cosine transform with an incorrect coefficient value, and the obtained pixel value is stored in the screen memory 8. The DC component deshuffling device 44 uses the DC component memory 45 to deshuffle the DC component of each block in the same manner as the deshuffling and inter-plane retouching device 24 performs the deshuffling. The DC component retouch value generator 47 generates a retouch value of an erroneous DC component from the DC components of the deshuffled erroneous DC component in the upper, lower, left, and right blocks. Subtractor 46
Generates the difference between the erroneous DC component used for the provisional inverse discrete cosine transform and the modified value. This difference is added by the adder 49 to all the pixel values in the block subjected to the tentative inverse discrete cosine transform. The switch controller 43 controls the switch circuit 48 to select the output of the adder 49 only from the pixel data of the block for which the DC component has been modified, of the pixel data deshuffled from the screen memory 8. . By doing so, it is possible to obtain the same result as performing the inverse discrete cosine transform after modifying the DC component.

As described above, in the third embodiment, even when there is an uncorrectable error in the DC component, the AC component can be utilized, and the information in the screen can be used more effectively. Also, when modifying a shuffled code by an adjacent block on a discrete cosine transform coefficient, it is usually necessary to provide a memory for all discrete cosine transform coefficients and complete deshuffling on the discrete cosine transform coefficient. However, according to the present embodiment, it is only necessary to provide a memory for the DC component, so that the circuit scale can be reduced.

FIG. 10 is a block diagram showing a specific example of the inter-plane modification judging circuit 20 shown in FIG. The inter-plane modification determination circuit 20 of FIG. 10 is applicable in the first to third embodiments. In FIG. 10, a modification command signal from the error corrector 2 is input to the inter-plane modifier 6 through a gate circuit 55 and a timing adjuster 56. Further, a control signal is supplied from the magnitude comparator 57 to the gate circuit 55, and two inputs of the magnitude comparator 57 are supplied with outputs of a coefficient counter 58 and a threshold value setter 59.

In such a configuration, the coefficient counter 58 counts the number of discrete cosine transform coefficients decoded in one block. This count resets at the beginning of each block. The magnitude comparator 57 compares this count value with the threshold value set by the threshold value setter 59, and performs control so that the gate circuit 55 opens when the count value is smaller than the threshold value. The discrete cosine transform coefficients are decoded in the order shown in FIG.
Only the correction command for the coefficient lower than the threshold value coefficient counted from the C component is transmitted to the next stage, and the correction command for the higher frequency coefficient is ignored. The timing adjuster 56, when receiving the modification command passed through the gate circuit 55, adjusts the timing so that the inter-plane modification processing is performed on the pixel data of the entire block in which the command has been issued.
At this time, in the case of encoding with shuffling, a change in timing due to deshuffling is also adjusted.

As described above, the inter-plane modification processing can be performed only when most components from a considerably low frequency to a high frequency are lost. When the in-plane modification is performed on the DC component as in the third embodiment shown in FIG. 9, the gate circuit 55 is closed while the coefficient counter 58 indicates the DC component. Large and small comparator 57
May be performed.

Although the discrete cosine transform is used in all of the embodiments described above, other orthogonal transforms for dividing pixel data into blocks and dividing them into two-dimensional frequency components and codes using transforms similar thereto are used. Even when the present invention is applied, the same effects as those of the above-described embodiments can be obtained. In addition, although the embodiment in which the code recorded on the recording medium is decoded has been described, the same effect can be obtained by applying the present invention to an apparatus that decodes a code transmitted through a transmission path.

[0031]

As described above, according to the present invention, in an apparatus for reproducing image data compressed and encoded by orthogonal transformation, in-plane modification on orthogonal transformation coefficients and inter-plane modification on pixel data are performed. By using in combination, it is possible to make use of the erroneous orthogonal transform coefficients in the block, and to perform more natural modification.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a compressed moving picture decoding device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a discrete cosine transform coefficient block in a digital image compression encoding system handled by the present invention.

FIG. 3 is an explanatory diagram showing a configuration of an error correction product block in a digital image compression encoding system handled by the present invention.

FIG. 4 is a block diagram showing a configuration of the in-plane retouching device of FIG. 1;

FIG. 5 is an explanatory diagram showing a configuration of an output (a modified discrete cosine transform coefficient block) of the in-plane retouching device of FIG. 4;

FIG. 6 is a block diagram showing an in-plane retoucher in a compressed moving picture decoding apparatus according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing the arrangement of discrete cosine transform coefficient blocks indicating adjacent blocks used for correction in the second embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a configuration of an output (a modified discrete cosine transform coefficient block) of the in-plane retouching device of FIG. 6;

FIG. 9 is a block diagram illustrating a main configuration of a compressed moving picture decoding apparatus according to a third embodiment of the present invention (an embodiment in which the DC component of a shuffled code is also subjected to in-plane modification).

FIG. 10 is a block diagram illustrating an example of an inter-plane modification determination circuit used in an embodiment of the present invention.

[Explanation of symbols]

 2 Error Corrector 3 Variable Length Decoder 4 In-plane Modifier 5 Inverse Discrete Cosine Transformer 6 Inter-plane Modifier 8 Screen Memory 9, 21, 22, 23 Discrete Cosine Transform Coefficient Block 20 Inter-plane Modification Judgment Circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukito Tsuboi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Visual Media Research Laboratory, Hitachi, Ltd. (72) Inventor Kenshi Ichige 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (72) Inventor Yukio Fujii 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd. Image Media Research Laboratory (56) References JP-A-5-161128 (JP, A) ( 58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/24-7/68 H04N 5/91-5/956

Claims (3)

(57) [Claims] In a compressed moving picture decoding apparatus for decoding moving picture data compressed and encoded using orthogonal transform, an in-screen modification process is performed in a state of orthogonal transform coefficients before performing inverse transform of orthogonal transform. One orthogonal transformation block, comprising: an in-plane modification means; and an inter-plane modification means for modifying between screens using pixel data of different screens in a state of pixel data after inverse transformation.
The amount of orthogonal transform coefficients that need to be modified in
If the value exceeds the threshold value, the repair by the face-to-face repair means is performed.
Cormorant that compressed moving picture decoding apparatus according to claim. 2. A moving picture compression-encoded using orthogonal transform.
In a compressed video decoding device that decodes image data,
Set all or some of the orthogonal transform coefficients of the
Replacement AC component modification means and adjacent orthogonal transform block
Generates incorrect DC component correction value using DC component
DC component correction value generation means and incorrect DC component correction
Inverse transformation of orthogonal transform block with incorrect DC component
DC component by adding to all subsequent pixel data
DC component retouching means for retouching
Compressed video decoding device. 3. A moving picture compression-encoded using orthogonal transform.
In a compressed video decoding device that decodes image data,
The orthogonal transform coefficients required by the orthogonal transform
Interpolates by numbers, and performs orthogonal transformation of odd-order with respect to the interpolation direction.
The number is provided with coefficient interpolation means for inverting the sign and using it for interpolation.
A compressed video decoding device.