JPH07274117A - Image signal reproducing device - Google Patents

Abstract

PURPOSE:To detect movement with simpler constitution by detecting movement through the use of the average value component of plural blocks around a block including an error at the time of detecting the movement of the block including the error. CONSTITUTION:A frame delay circuit 205 outputs input data to a switch 214 after it is delayed for one frame. An intra-field interpolation circuit 206 generates intra-field interpolation data for the block including image data whose error cannot be corrected and outputs it to the switch 214. The switch 214 selects image data from a frame delay circuit 205 and interpolation data from the intra-field interpolation circuit 206 in accordance with movement information of the detected error block and outputs it to a terminal 215. Namely, a system is connected to (a)-side and intra-field interpolation data is selected when movement exists. When movement does not exist, the system is connected to (b)-side and correct data or inter-frame interpolation data is outputted. Image data from the switch 214 is also outputted to a switch 204.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal reproducing device, and more particularly to an image signal reproducing device for decoding a highly efficient coded image signal and modifying undecodable data for reproduction.

[0002]

2. Description of the Related Art As a device of this type, a digital VTR for digitizing an image signal to record and reproduce has been known. In such a digital VTR, a compression coding technique is used for compressing image data and performing recording / reproduction.

An orthogonal transform coding system is known as a technique for compressing and coding an image signal with high efficiency.
This is because the image signal is grouped into blocks for each number of pixels and then the discrete cosine transform (Discrete Cosine Transfor
mation: An orthogonal transform such as DCT) is performed, and the transformed coefficient is quantized, entropy coded, and the like.

In this system, since coding is performed in block units, if an error occurs in coded data during reproduction of an image signal, a code error occurs in block units. In addition, since variable length coding is often used, a decoding error often propagates over a plurality of blocks, resulting in a large deterioration in image quality. Then, among such decoding errors, the data that cannot be completely corrected even if error correction processing is performed is
Interpolation was performed using data of blocks that are temporally and spatially close as error-correctable data (hereinafter referred to as error data).

Conventionally, when interpolating image data of a block containing such error data (hereinafter referred to as an error block), inter-frame interpolation and intra-field interpolation are often used selectively. In other words, the inter-frame correlation of the image data of the upper and lower blocks of the error block (1
The in-block addition result of the absolute value of the difference from the pixel before the frame) is obtained, and the presence or absence of the motion of the error block is estimated, and the intra-field interpolation is selected when there is motion, and the inter-frame interpolation is selected when there is no motion.

[0006]

However, when such interpolation is performed, if the motion determination for the error block is incorrect, pixel data having a low correlation with the pixel block to be interpolated is used. However, there is a problem that the image quality of the reproduced image is deteriorated due to the interpolation using the.

Further, in the above-mentioned conventional example, since the inter-frame difference of one block has to be integrated at the time of motion detection, the amount of calculation required for motion detection is large and the device becomes large.

Further, since the motion detection is performed based on the inter-frame difference of all the pixels of one block, when the decoded image signal cannot be reproduced faithfully due to the influence of noise during reproduction, the frame is not reproduced. There is a high possibility that the value of the inter-difference is erroneously obtained, and as a result, motion detection cannot be performed accurately.

In view of the above problems, the present invention detects the motion of an error block and interpolates image data by detecting the motion based on the average luminance component of blocks around the error block. An object of the present invention is to provide an image signal reproducing device which can solve the above-mentioned problems, simplify the motion detecting operation, and improve the motion detecting accuracy.

[0010]

SUMMARY OF THE INVENTION In order to solve the conventional problems and solve the above object, the present invention is an image signal reproducing apparatus for reproducing an image signal blocked for each of a plurality of pixels. An error detecting means for detecting an error in the image signal; a motion detecting means for detecting a motion of the block including the error by using an average value component of a plurality of blocks around the block including the error; Constructing means for constructing an image signal for the block containing the error based on the output of the motion detecting means.

Further, another image signal reproducing apparatus according to the present invention is an image signal reproducing apparatus for reproducing an image signal blocked for each of a plurality of pixels, and error detection for detecting an error in the image signal. Means for detecting the motion of the block including the error based on an average value component of a plurality of blocks around the block including the error and an error situation of blocks around the block including the error. And construction means for constructing an image signal for the block containing the error based on the output of the motion detection means.

Further, the image processing apparatus according to the present invention has an input means for inputting an image signal blocked for each of a plurality of pixels, an error detecting means for detecting an error in the image signal, and a block including the error. Motion detecting means for detecting the motion of the block containing the error based on the average value component of the plurality of blocks surrounding the error state detecting means for detecting the error status of the plurality of blocks surrounding the block containing the error. And control means for controlling the motion detecting means based on the output of the error situation detecting means, and constructing means for constructing an image signal for the block containing the error based on the output of the motion detecting means. It is equipped with.

[0013]

Since the present invention is configured as described above, the motion of the error block can be detected with a simple configuration. Also, since highly reliable motion detection can be performed, it is possible to construct an image signal having a high correlation with an image signal that cannot be error-corrected.

[0014]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, the operation of the recording system of the digital VTR according to the present invention will be described. FIG. 1 is a block diagram showing the configuration of a recording system of a digital VTR.

In FIG. 1, reference numeral 100 denotes an analog image signal sent from an image signal transmission system such as a video camera, which is input from an input terminal 100, converted into a digital signal by an A / D converter 101, and stored in a memory 102. Written. Then, the image data written in the memory 102 is divided into blocks of 8 pixels × 8 pixels in a frame unit as shown in FIG. 2, and the data is shuffled and read.

The image data read from the memory 102 is supplied to the DCT circuit 103. The DCT circuit 103 applies DCT to image data for each 8 × 8 pixel block.
Then, the image data is converted from the spatial domain to the frequency domain data, and the transform coefficient is output to the quantization circuit 104. The state of one block of data after DCT is shown in FIG. As is clear from the figure, one block is 8 × 8 = 6.
It is composed of DC data representing the average level of 4 pixels and AC data representing the frequency distribution of the image.

Generally, a moving image such as a video signal is temporally
The spatial correlation is high, and when DCT is applied to convert the data into frequency domain data, the components can be concentrated in a relatively low frequency domain. In addition, since the sensitivity in the high frequency region is low due to human visual characteristics, deterioration of the image is not noticeable even if the image is quantized a little coarsely. Therefore, the quantizing circuit 104 utilizes this fact to quantize the transform coefficient for each block 8 × 8 supplied from the DCT circuit 103 in coarser quantizing steps in the higher frequency region.

Then, the variable length coding circuit 105 performs zigzag scanning from the low frequency region toward the high frequency region, and assigns a variable length code such as a two-dimensional Huffman code to the quantized transform coefficient. We are trying to reduce the amount of information.

The image data variable-length coded by the variable-length coding circuit 105 is error-correction-coded for recording / transmission by the error correction circuit 106 using a Reed-Solomon product code or the like, and then is supplied to the modulation circuit 107. Is output. Then, the modulation circuit 107 performs modulation suitable for magnetic recording, and the recording / reproducing circuit 108 records it on a magnetic tape (not shown).

Next, the operation of the reproducing system of the digital VTR will be described. The image data reproduced from the magnetic tape by the recording / reproducing circuit 108 is demodulated by the demodulating circuit 109 at the time of recording, and then the code error is corrected by the error correcting circuit 110. At this time, for the uncorrectable image data, an error flag is generated for each pixel block described above and output to the interpolation circuit 116.

The image data whose code error has been corrected by the error correction circuit 110 is decoded by the variable length code decoding circuit 111 and output to the inverse DCT circuit 112 and the DC extraction circuit 114. The inverse DCT circuit 112 performs inverse DCT on the input image data, converts the frequency domain data into spatial domain data, and outputs the data to the memory 113. Then, after deshuffling the input image data in the memory 113 to restore the original image signal order, the data is output to the interpolation circuit 116.

Further, the DC extraction circuit 114 is the control circuit 1
Controlled by 15, the DC coefficient as an average value component (average luminance component) in each block is extracted from the input conversion coefficient of each block, stored for one frame, and output to the interpolation circuit 116. To do.

The interpolation circuit 116 interpolates an image relating to the image data that cannot be corrected by the error correction circuit 110 as described later, and then outputs it from the output terminal 117 to the outside.

Next, the operation of the interpolation circuit 116 as the first embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the interpolation circuit 116 as the first embodiment of the present invention. The processing of each circuit in this embodiment is
For each field, 8 (horizontal) × 4 (vertical) pixels are treated as a unit of a processing block.

In FIG. 5, image data read from the memory 113 is input to the input terminal 201 and output to the frame delay circuit 205 via the switch circuit 204. The switch 204 switches according to the error flag input from the input terminal 203, and when the error flag indicates that error correction is impossible, that is, when it is “1”, a
If the error correction is possible or there is no error, that is, if it is "0", it is connected to the side b.

The frame delay circuit 205 delays the input image data by one frame and then outputs it to the switch 214.

The image data from the input terminal 201 is also
It is also input to the intra-field interpolation circuit 206. The intra-field interpolation circuit 206 generates intra-field interpolation data for a block including image data that cannot be error-corrected according to the error flag from the input terminal 203, and outputs it to the switch 214.

The operation of the intra-field interpolation circuit 206 will be described with reference to FIG. It is assumed that the block X in FIG. 6 is an error block. As described above, in this embodiment, the processing is executed in field units. Therefore, the odd field lines x1, x3, x5, x7 of the error block X are the line a7 of the block A which is the line of the same field closest to the uppermost line x1 of the odd field among the lines of the correctly reproduced block, and the In-field linear interpolation is performed by the line b1 of the block B, which is the line of the same field closest to the lower line x7.

After the processing of the odd field is completed, the processing of the even field is performed. The even field lines x2, x4, x6, x8 of the error block X are also line a of the block A as in the case of the odd field lines described above.
8 and the line b2 of the block B are linearly interpolated.

That is, in the odd field, x
1 = (4 × a7 + b1) / 5, x3 = (3 × a7 + 2 ×
b1) / 5, x5 = (2 × a7 + 3 × b1) / 5, x7
= (A7 + 4 × b1) / 5, and in the even field, x2 = (4 × a8 + b2) / 5, x4 = (3 ×
a8 + 2 × b2) / 5, x6 = (2 × a8 + 3 × b2)
/ 5, x8 = (a8 + 4 × b2) / 5. The intra-field interpolation data generated in this way is stored in the switch 21.
4 is output.

The switch 214 responds to the motion information of the error block detected as described later, and the image data from the frame delay circuit 205 and the intra-field interpolation circuit 20.
6 and the interpolation data from 6 are selected and output to the switch 215. That is, when there is motion, it is connected to the a side to select intra-field interpolation data, and when there is no motion, it is connected to the b side to output correct data or interframe interpolation data. The image data from the switch 214 is also output to the a-side terminal of the switch 204.

Next, the motion detecting operation will be described.
The DC data from the DC extraction circuit 114 is input to the input terminal 202 and output to the delay circuit 207 and the DC averaging circuit 208.

FIG. 7 is a diagram showing the states of error blocks and blocks adjacent to the error blocks. Now, it is assumed that the DC data of the block H is input from the input terminal 202 and the error flag corresponding to the block H is input from the input terminal 203. Pattern detection circuit 209
Detects the error status of blocks around the error block X, that is, blocks A to H in FIG. 7, based on the error flag output from the input terminal 203, and DC
It outputs to the averaging circuit 208 and the switch 213. The DC averaging circuit 208 includes blocks A to A around the error block X.
Of the H, only DC data of a block that is not in error, that is, a block that can be error-corrected or a block that is correctly reproduced is selected, an average value of these DC data is calculated, and output to the absolute difference circuit 210.

The delay circuit 207 is a DC averaging circuit 2
When 08 outputs the average value of each DC data as described above, the delay time is set so as to output the DC data at the corresponding position just one frame before the block X, and one frame before the block X. The DC data of the block is output to the absolute difference circuit 210.

The difference absolute value circuit 210 is provided for each input D
The absolute value of the difference between the C data is calculated and output to the motion detection circuit 211. The motion detection circuit 211 compares the difference absolute value with a predetermined threshold value, outputs a signal indicating that there is motion when the difference absolute value is larger than the threshold value, and outputs no motion when the difference absolute value is smaller than the threshold value. It outputs the indicated signal.

The output of the motion detection circuit 211 (hereinafter, motion data) is input to the delay circuit 212 and the b-side terminal of the switch 213. The delay circuit 212 sets this motion data to 1
The frame is delayed and output to the a-side terminal of the switch 213.

Here, switching of the switch 213 will be described. The switch 213 is a pattern detection circuit 209.
It switches according to the output of, and connects to the a side in the following cases,
Outputs past movement data. First, if all the blocks A to H around the block X are error blocks, they are connected to the a-side terminal. That is, when all the surrounding blocks are error blocks, the input DC data is not correct data and has low reliability. Further, even if the corresponding block on the screen one frame before the block X is an error block, the block X is connected to the a side.
In this case, since the correct DC data of the block one frame before the block X cannot be obtained, the DC averaging circuit 208
This is because even if the difference from the output data of is taken, it becomes extremely unreliable.

That is, there are two ways to connect to the a-side terminal: when all the adjacent blocks of the error block are error blocks, and when the corresponding block of the screen one frame before the error block is the error block. Is. Therefore, connect to the b-side terminal: -At least one of the adjacent blocks of the error block
One of them is correctly reproduced (error correction is possible), and the corresponding block of the screen one frame before the error block is correctly reproduced (error correction is possible).

The switch 213 selects the motion data as described above and outputs it to the switch 214.

As described above, according to this embodiment,
When detecting the motion of the error block, the motion detection is performed by using the DC data of the blocks around the error block, so that it is possible to reduce the enormous amount of calculation conventionally required for the motion detection. Therefore, it is possible to prevent the circuit from becoming large.

Further, since the motion detection is performed only by the DC data, it is possible to avoid erroneous determination due to noise or the like at the time of recording / reproduction that tends to occur in high frequency components.

Next, a second embodiment of the present invention will be described. FIG. 8 shows an interpolation circuit 1 as a second embodiment of the present invention.
It is a block diagram which shows the structure of 16. The same components as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 8, the DC data input from the input terminal 202 is output to the frame delay circuit 216 and the absolute difference value circuit 210. That is, the absolute difference circuit 2
The DC data of the currently input block and the DC data of the block one frame before the block are input to 10, and the difference absolute value circuit 210 calculates the difference absolute value of these DC data. Motion detection circuit 211
Output to.

The pattern detection circuit 209, as described above,
An error block of blocks A to H around the error block X is detected and output to the motion detection circuit 211.

The motion detection circuit 211 is the difference absolute value circuit 2
Among the inter-frame differences of the blocks A to H output from 10, the inter-frame differences of blocks that are not error blocks are added and compared with a predetermined threshold value. Then, if it is larger than the threshold, there is a motion, and if it is smaller than the threshold, a signal without motion is output to the switch 214.

Also in this embodiment, when the motion of the error block is detected, the motion detection is performed using the DC data of the blocks around the error block, so that the calculation amount can be reduced. Further, in the present embodiment, since the configuration in which the difference between the DC data frames of blocks other than the error block is simply integrated is compared with the threshold value, it is not necessary to obtain the average value of each DC data by the averaging circuit, and the configuration is simpler. Motion detection can be performed at.

Next, a third embodiment of the present invention will be described. FIG. 9 shows an interpolation circuit 1 as a third embodiment of the present invention.
It is a block diagram which shows the structure of 16. Also in FIG.
The same components as those in the above-mentioned embodiment are designated by the same reference numerals.

In FIG. 9, the DC data input from the input terminal 202 is output to the frame delay circuit 216, the absolute difference circuit 217 and the DC averaging circuit 208. The frame delay circuit 216 delays the input DC data by one frame, and then delays the delay circuit 220 and the absolute difference value circuit 217.
Output to.

The difference absolute value circuit 217 receives these input DCs.
The difference between the data is calculated and output to the motion detection circuit 219.
The motion detection circuit 219 compares the inter-frame difference of the DC data with a predetermined threshold value for each block, obtains motion data for each block, and outputs the motion data to the DC averaging circuit 208.

The pattern detection circuit 209, as described above,
The block around the error block X, which is an error block, is detected and output to the DC averaging circuit 208 and the switch 213.

The DC averaging circuit 208 is a motion detecting circuit 21.
On the basis of the motion data from 9 and the output signal from the pattern detection circuit, only the DC data of the blocks which are not error blocks and have no motion among the blocks A to H are selected, and the average value thereof is calculated. Output to the absolute difference circuit 210.

The delay circuit 220 is the DC averaging circuit 2 described above.
When the DC data is output from 08, the input DC data is delayed so as to output the DC data of the block on the screen immediately preceding the block X by one frame, and is output to the absolute difference circuit 210.

The absolute difference circuit 210 includes a delay circuit 220.
From the DC data from the DC averaging circuit 208 and the absolute value of the difference between the DC data from the DC averaging circuit 208 and the motion detection circuit 211.
Output to. The motion detection circuit 211 compares the absolute difference value with a predetermined threshold value and outputs the motion data as described above.

Then, the connection of the switch circuit 213 is switched as described above, the motion data is selected, and the switch 2 is switched.
It outputs to 14.

In the present embodiment, the motion detection is performed using only the DC data of the blocks having no motion among the blocks A to H around the error block X. This is because it is considered that the reliability of the data is low, because the difference in is large and the average value component is not stable. On the other hand, the block with no motion has no difference between screens and the average value component is stable,
Seems to be reliable.

That is, in this embodiment, since the motion is detected using only the DC data of the block having no motion,
In addition to the effects of each of the above-described embodiments, it is possible to perform more reliable motion detection.

Therefore, when the motion adaptive interpolation is performed, erroneous motion detection is not performed, and the interpolation can be performed using the image signal having a higher correlation, so that the deterioration of the image quality of the reproduced image can be prevented. become.

In this embodiment, the motion is detected by the average value of the DC data of the blocks without motion, but there is motion / no motion according to the number of blocks with motion and the number of blocks with motion. Alternatively, the average value of the DC data of the non-existing block may be weighted and added, and the motion detection may be performed using the added DC data.

[0060]

As described above, according to the present invention, when detecting the motion of a block containing an error, the motion is detected by using the average value components of a plurality of blocks around the block containing the error. Therefore, motion detection can be performed with a simpler configuration.

Further, in another invention of the present application, since the motion detection is performed based on the average value component of the blocks around the block including the image signal in which the error cannot be corrected, and the error condition of these surrounding blocks, the motion is detected. Detection reliability is improved.
Therefore, when an image signal is constructed for a block containing an error according to the motion, it is possible to construct an image signal having a higher correlation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a recording system of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of blocking in FIG.

FIG. 3 is a diagram for explaining the operation of the variable length coding circuit in FIG.

FIG. 4 is a diagram showing a configuration of a reproduction system of a digital VTR as an embodiment of the present invention.

5 is a block diagram showing a configuration of an interpolation circuit in FIG.

FIG. 6 is a diagram for explaining the operation of the intra-field interpolation circuit in FIG.

FIG. 7 is a diagram for explaining the operation of the interpolation circuit in the embodiment of the present invention.

8 is a block diagram showing another configuration of the interpolation circuit in FIG.

9 is a block diagram showing still another configuration of the interpolation circuit in FIG.

[Explanation of symbols]

 206 In-field interpolation circuit 208 DC averaging circuit 209 Pattern detection circuit 210 Difference absolute value circuit 211 Motion detection circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location G11B 20/18 Z 8940-5D H04N 5/92 7/30 H04N 7/133 A

Claims (12)

[Claims] 1. An image signal reproducing apparatus for reproducing an image signal blocked for each of a plurality of pixels, comprising: error detecting means for detecting an error in the image signal; and a plurality of units around a block including the error. Motion detecting means for detecting the motion of the block containing the error by using the average value component of the block, and building means for building an image signal for the block containing the error based on the output of the motion detecting means. An image signal reproducing apparatus comprising: 2. The image signal is block-coded using orthogonal transform, and the motion detecting means detects motion using DC components of orthogonal transform coefficients in a plurality of blocks around the block containing the error. The image signal reproducing device according to claim 1, wherein 3. The constructing means constructs an image signal using an in-screen constructing circuit that constructs an image signal by using an image signal of a screen including the error, and an image signal by using an image signal of a screen different from the screen including the error. The image signal reproducing apparatus according to claim 1, further comprising an inter-screen construction circuit to be constructed. 4. The construction means further comprises a selection circuit for selectively outputting the image signal from the intra-screen construction circuit and the image signal from the inter-screen construction circuit according to the output of the motion detection means. The image signal reproducing apparatus according to claim 3, further comprising: 5. The motion detecting means, the average value of the DC components of the orthogonal transform coefficients in a plurality of blocks around the block containing the error, and the orthogonal transform of the corresponding block one screen before the screen containing the error. The image signal reproducing apparatus according to claim 2, wherein the motion is detected based on a difference between the coefficient and the DC component. 6. The image according to claim 2, wherein the motion detecting means detects the motion based on a difference between screens of DC components in orthogonal transform coefficients of blocks around the block including the error. Signal reproduction device. 7. The error detection means includes an error correction circuit for correcting an error in the image signal, and the error correction circuit detects an uncorrectable error. Image signal reproducing device. 8. The image signal reproducing apparatus according to claim 1, further comprising a decoding means for decoding the image signal passed through the error detecting means. 9. An image signal reproducing apparatus for reproducing an image signal blocked for each of a plurality of pixels, comprising: error detecting means for detecting an error in the image signal; and a plurality of units around a block including the error. Based on the average value component of the block of, and the error status of the blocks around the block containing the error, based on the output of the motion detection unit, which detects the motion of the block containing the error, An image signal reproducing apparatus comprising a constructing unit for constructing an image signal for a block including the error. 10. The motion detecting means, among blocks around a block containing the image signal incapable of error correction,
9. The image signal reproducing apparatus according to claim 8, wherein the motion is detected based on an average value component of blocks other than the block including the error. 11. The image signal is block-coded using orthogonal transform, and the motion detecting means detects motion using DC components of orthogonal transform coefficients in a plurality of blocks around the block containing the error. The image signal reproducing device according to claim 10, wherein 12. An input unit for inputting a block image signal for each of a plurality of pixels, an error detection unit for detecting an error in the image signal, and an average value of a plurality of blocks around the block including the error. A motion detecting unit that detects a motion of a block including the error based on a component, an error situation detecting unit that detects an error situation of a plurality of blocks around the block including the error, and an output of the error situation detecting unit Image processing, characterized in that it comprises a control means for controlling the motion detecting means based on the above, and a constructing means for constructing an image signal for the block containing the error based on the output of the motion detecting means. apparatus.