JPH06282937A - Id code detecting method and device therefor - Google Patents

Abstract

PURPOSE:To obtain an ID code detecting method and ID code detecting device capable of detecting an ID code correctly while preventing the detection error of the ID code due to a code error and detecting the ID code correctly right after the time even when data become to be discontinuity. CONSTITUTION:A coincidence between an estimated ID code 18 being the ID code of a succeeding second synchronizing block estimated from a first detected ID code 17 detected from a first synchronizing block and a second detected ID code 16 detected from the second synchronizing block is detected. When the coincidence is detected, the first detected ID code 17 is outputted as a defined ID code 20 to the first synchronizing block. When the coincidence is not detected, an ID code to the first synchronizing block is estimated from the defined ID code 21 to a synchronizing block being ahead by one block of the first synchronizing block and then, outputted as a defined ID code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ID code detecting method and an ID code detecting apparatus for detecting an ID code of a synchronization block included in digital information such as a digital audio tape recorder or a digital VTR. .

[0002]

2. Description of the Related Art In recent years, digital audio tape recorders and digital VTRs have been developed which digitize audio signals and video signals and record them without deterioration.

FIG. 4 shows an example of a reproduced data sequence of a digital VTR. In FIG. 4, 1a to 1f are synchronization blocks having a predetermined number of bits. The contents of each synchronization block are shown in FIG. In FIG. 5, reference numeral 2 is a synchronization code, which is a code for detecting the head position of the synchronization block. Reference numeral 3 denotes an ID code, which includes information such as a track number and a block number indicating a position in the track in order to distinguish this synchronization block from other synchronization blocks. Reference numeral 4 denotes a data section, which contains video or audio data and error correction code.

In order to correctly reproduce a video or audio from such a reproduction data series, the ID code 3 must be detected correctly. However, a code error usually occurs in reproduced data due to the influence of noise. Therefore, in order to prevent the detection error of the ID code due to a code error and to detect it correctly, there is known a method of correcting the detected ID data by using the ID data of the synchronization block located before the synchronization block to be detected. (For example, JP-A-59-94
941).

[0005]

By the way, in the VTR, there are cases in which reproduction is performed across recording tracks in search reproduction and the like, at which time the data series becomes discontinuous. At this time, with the above-mentioned conventional method, the ID codes of some synchronization blocks cannot be correctly detected until the ID codes are correctly detected after the position where the data string becomes discontinuous. For this reason, there is a problem that the data in this portion cannot be reproduced correctly and the reproduced image quality is deteriorated at the time of searching.

[0006] Therefore, the present invention is to solve the above problems.
An ID code detection device capable of preventing an error in detecting an ID code due to a code error, detecting the ID code correctly, and immediately detecting the ID code even when the data becomes discontinuous, and easily realizing with a small circuit scale. It is intended to be provided.

[0007]

In order to achieve the above object, the ID code detecting method of the present invention provides an ID of a second sync block succeeding a first detected ID code detected from a first sync block. A match between the estimated ID code that estimated the code and the second detected ID code detected from the second synchronization block is detected, and if a match is detected, the first detected ID code is set to the first detected ID code. Definite I for sync block
D code is output, and if no match is detected, the ID code for the first synchronization block is estimated from the definite ID code for the synchronization block immediately before the first synchronization block, and the first synchronization block is estimated. Confirmed ID for
It is output as a code.

The ID detecting apparatus of the present invention further comprises a first delay means for delaying the detected ID code detected from the sync block for one sync block period, and a sync block following from the output of the first delay means. First estimating means for estimating an ID code and outputting a first estimated ID code; and the detection I
Match detection means for detecting a match between the D code and the first estimated ID code, second delay means for delaying the confirmed confirmed ID code by one synchronization block, and synchronization that follows from the output of the second delay means. The second estimating means for estimating the ID code of the block and outputting the second estimated ID code, and the output of the first delay means when the match is detected by the match detecting means, the match is detected. If not, the selection means selects each of the second estimated ID codes as the confirmed ID code.

[0009]

According to the present invention, the ID code for the synchronization block is determined from the ID code at the beginning of the synchronization block and the ID code at the beginning of the succeeding synchronization block by the above method or configuration. Even when is discontinuous, the ID code can be correctly detected immediately after that. If an error is detected from one of two consecutive ID codes, the previously determined ID
Since the ID code is estimated and output from the code, the correct ID code can be detected even if the ID code has an error due to a code error. Furthermore, it can be realized with an extremely simple circuit configuration.

[0010]

EXAMPLES IDs using the ID code detecting method of the present invention will be described below.
An embodiment of the code detecting device will be described. FIG. 1 is a block diagram of an ID code detecting apparatus according to an embodiment of the present invention.

In FIG. 1, the ID code detected from the data string reproduced from the digital VTR is input as a signal 16. The signal 16 is delayed for one synchronization block period by the delay circuit 10 serving as the first delay means and output as the signal 17. The signal 17 is connected to one input terminal of the estimation circuit 11 as the first estimation means and the switch 13.

The estimation circuit 11 estimates the next ID code from the ID code indicated by the signal 17 and outputs it as a signal 18. In the ID code, the track number does not change in one track, the block number changes regularly,
There is such a property. Therefore, the estimation circuit 11 estimates the next ID code based on these rules.

The coincidence detection circuit 12 outputs the ID indicated by the signal 16.
It is determined whether the code and the ID code indicated by the signal 18 match, and the determination result is output as the signal 19. Here, it is assumed that the signal 19 becomes the H level when they match, and the L level when they do not match.

The switch 13 is controlled by the signal 19, and selects the signal 17 when the signal 19 is at the H level, and selects the signal 22 described later when the signal 19 is at the L level, as a signal indicating the confirmed ID code. The signal 20 is output.

Further, the signal 20 is input to the delay circuit 14 which is the second delay means and is delayed by one synchronization block period to become the signal 21. Estimating circuit 15 which is the second estimating means
Outputs the signal 22 by estimating the next ID code from the ID code indicated by the signal 21. It should be noted that the estimation circuit 15 performs estimation based on the rules of the ID code, as in the above estimation circuit 11.

Next, a more specific operation of the above embodiment will be described with reference to the timing chart. Figure 2
FIG. 6 is a timing chart showing an example of changes in signals 16 to 22. In this example, data is continuously reproduced from one track, and the ID codes are "A", "B",
"C", ..., "X", "Y", ... are recorded in this order. Also, at time t ₄ ,
The ID code indicated by the signal 16 is originally “H”, but it is assumed that it has been detected as “X” due to a code error.

Here, the signal 19 is the signal 16 as described above.
Is a signal indicating that the ID code indicated by and the ID code indicated by the signal 18 match, and becomes H level when they match. Therefore, in the example of FIG. 2, the time t ₄ when the ID code indicated by the signal 16 becomes “X” due to a code error, and the signal 17
The signal 19 becomes L level at the time t _{5 when the} ID code indicated by the signal 18 estimated from the ID code indicated by 1 becomes “Y”.

The signal 20 indicating the confirmed ID code is equal to the signal 17 when the signal 19 is at the H level. Time t ₄
In, the ID code “G” indicated by the signal 22 estimated from the ID code indicated by the signal 21 obtained by delaying the signal 20 is output as the signal 20. Similarly, at time t ₅ , the ID code “H” indicated by the signal 22 is output.

As a result of the above-described operation, the definite ID code indicated by the signal 20 is replaced by the correct code "H" in the ID code indicated by the signal 16 by replacing it with the correct code "H". It will be output with a delay. Therefore, if the reproduced data string is delayed by one synchronization period, the correct ID code for this can be obtained as the signal 20.

Next, another example of the specific operation of the embodiment will be described. FIG. 3 is a timing chart showing another example of changes in the signals 16 to 22. This example shows a case where the data sequence becomes discontinuous as in the case of VTR search reproduction. That is, "A", "B", "C",
From the reproduction of a track in which the ID code is recorded in the order of ..., From time t ₄ , "a", "b",
This is the case when the reproduction is switched to another track in which the ID code is recorded in the order of "c", ....

Here, the signal 19 becomes L level at time t _{4 when the} ID code indicated by the signal 16 and the ID code indicated by the signal 18 do not match.

The signal 20 indicating the confirmed ID code is equal to the signal 17 when the signal 19 is at the H level,
Is at the L level, it is equal to the ID code indicated by the signal 22. Therefore, although the signal 19 becomes L level at the time t ₄ , the signal 22 correctly estimates the ID code “G” during this period, so the ID code output by the signal 20 is also correct.

As a result of the operation described above, the confirmed ID code indicated by the signal 20 is the ID code indicated by the signal 16 which is output with a delay of one sync block period, and the reproduced data string is output by one sync block period. If delayed, the correct ID code for this is obtained as signal 20. That is,
Even when the data becomes discontinuous like the VTR search reproduction, the ID code can be correctly detected immediately after that.

Needless to say, the present invention is not limited to the above-mentioned embodiments, and may be applied to other embodiments within the scope of the claims.

[0025]

As described above, according to the present invention, even if there is an ID code detection error due to a code error, the output ID code is a correct ID code corrected for this. Further, even when the data becomes discontinuous, the ID code can be correctly detected immediately after that, and thereby a reproduced image with high image quality can be obtained even during VTR search reproduction. Further, since it has an extremely simple configuration, it has a feature that it can be easily realized with a small circuit scale.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of this embodiment.

FIG. 3 is a timing diagram illustrating another operation of this embodiment.

FIG. 4 is a signal diagram illustrating a reproduced data string of a digital VTR.

FIG. 5 is a signal diagram showing the contents of one sync block of a reproduced data string of a digital VTR.

[Explanation of symbols]

 10, 14 Delay circuit 11, 15 Estimating circuit 12 Match detection circuit 13 Switch

Claims (2)

[Claims] 1. An estimated ID code obtained by estimating an ID code of a subsequent second synchronization block from a first detected ID code detected from a first synchronization block and a second detection detected from the second synchronization block. Of the detected ID code of No. 1 is detected, and when the match is detected, the first detected ID code is output as a confirmed ID code for the first synchronization block,
If no match is detected, the ID code for the first synchronization block is estimated from the definite ID code for the synchronization block immediately preceding the first synchronization block, and the first synchronization block is estimated.
Output as a definite ID code for the synchronization block of
D code detection method. 2. A first delay means for delaying a detected ID code detected from a sync block for one sync block period, and an ID of a sync block following from the output of the first delay means.
The first estimating means for estimating the code and outputting the first estimated ID code, the coincidence detecting means for detecting the coincidence between the detected ID code and the first estimated ID code, and the confirmed confirmed ID code are 1 Second delay means for delaying the synchronization block; second estimation means for estimating the ID code of the following synchronization block from the output of the second delay means to output a second estimated ID code; ID which comprises an output of the first delay means when a match is detected by the means, and a selection means which selects the second estimated ID code as the confirmed ID code when a match is not detected. Code detection device.