JPH06276494A - Video system - Google Patents

Abstract

PURPOSE: To conduct zooming or horizontal panning of a short-cut image in a television receiver having a wide display format ratio screen. CONSTITUTION: A signal processor 304 has a first-in first-out line memory 356 having write and read pots asynchronously with an interpolation device 337 to selectively expand/compress an image denoted by data in a video signal. The image is cut short to control write of data to the line memory so as to specify a subset for the display image. A microprocessor supplies a control signal that has a selectable consecutive time and a selectable phase with respect to a synchronizing component of the video signal to select a border of sub-sets of the image. The microprocessor selects a consecutive time and a phase in response to a command of the user.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the field of televisions capable of displaying zoomed and / or cropped screens, and more particularly zooms in televisions having screens with a wide display format ratio. Alternatively, it relates to a method and apparatus for horizontally panning a truncated screen.
Most of today's televisions have a 4: 3 format display ratio of horizontal width to vertical height.
The wide format display ratio more closely corresponds to the display format ratio of movies, eg 16: 9. The present invention is applicable to both direct-view televisions and projection televisions.

[0002]

BACKGROUND OF THE INVENTION Televisions with a format display ratio of 4: 3, often also referred to as 4x3, have limitations in the way they can display a single video source and multiple video sources. Except for the experimental ones, the transmission of television signals of commercial broadcasting stations is broadcast in a display ratio of 4 × 3 format. Many viewers consider the 4x3 display format to be no better than the wider format display ratios associated with movies. A television with a wide format display ratio not only provides a more pleasing display, but can also display a wide display format signal source in a corresponding wide display format. Movies are truncated,
It looks like a movie without being distorted. The video source need not be truncated, for example when it is converted from film to video by a telecine device, or even by a television processor.

Wide display format ratio televisions are used to display both normal display format signals and wide display format signals in various forms, and to display these format signals in a multi-screen form. Are suitable. However, there are many problems associated with using a wide display ratio screen. Common among such problems are changing the display format ratio of multiple signal sources, generating coincident timing signals from video signals that are displayed simultaneously but asynchronously, and multi-screen display. In order to do so, switching between multiple signal sources and creating a high resolution screen from the compressed data signal may occur. These problems are solved in the widescreen television according to the invention. Widescreen televisions according to various configurations of the present invention are capable of displaying high resolution single and multiple screen displays from single and multiple video signal sources having the same or different format ratios with selectable display format ratios.

Televisions with a wide display format ratio are both interlaced and non-interlaced, and basic,
That is, it can be implemented in a television system that displays video signals at both standard horizontal scanning frequencies and multiples thereof.
For example, a standard NTSC video signal is displayed by interlacing successive fields of each video frame, each of which is produced by a raster scan at a basic or standard horizontal scan frequency of approximately 15,734 Hz. The basic scanning frequency for a video signal is variously called f _H , 1f _H or 1H. 1f
The actual frequency of the _H signal will change for different video formats. In an effort to improve the picture quality of television devices,
Systems have been developed for sequentially displaying non-interlaced video signals. Sequential scanning requires each display frame to be scanned at the same time allotted to scan one of the two fields in the interlaced format. Flicker-free AA-BB display requires scanning each field twice in succession. In each case, the horizontal scan frequency should be twice the standard horizontal frequency. The scanning frequency for such progressive scanning display or flicker-free display is variously called 2f _H or 2H. For example, 2 according to US standards
The f _H scan frequency is approximately 31,468 Hz.

In order to realize many of the display formats particularly suitable for wide-screen television, considerable signal processing is required for the main video signal. Bit data needs to be selectively compressed and decompressed according to a desired format. For example, in some cases, in order to avoid aspect ratio distortion of the display screen, 4 × 3NTS
C-video needs to be compressed by a factor of 4/3, or 4: 3. In other cases, for example, the video may need to be stretched to perform horizontal zooming operations, which usually also involve vertical zooming. Horizontal zoom operations up to 33% can be performed by compressing less than 4/3, for example 5/4. For the S-VHS format, the luminance video bandwidth up to 5.5MHz is
The 1024F _H system clock is 8 MHz, the Nyquist frequency, i.e., since a large part of the folding frequency, recalculate the incoming video to a new pixel positions
A sample interpolator is used to (recalculate).

Luminance data for the main signal comprises a FIFO line memory for compression (pause) and expansion (repetition) of the data and an interpolator for recalculating sample values to smooth the data. Sent along the main signal path including. However, when compressing and decompressing, the FIF
The relative positions of O and the interpolator are different. According to the configuration of the present invention, the switch or route selector inverts the form or topology of the main signal path with respect to the relative positions of the FIFO and the interpolator so that two FIFOs and two interpolators are required. Eliminates the need to use two main signal paths. That is, these switches can be either the interpolator preceding the FIFO (which is needed during compression) or the FIFO.
Selects before the interpolator (which is needed during decompression). These switches are responsive to route control circuitry which is responsive to the microprocessor.

The interpolator control circuit generates pixel position values, interpolator correction filter weighting information and clock gating information for the luminance data. FIF
Pause (interrupt or decimate) O data,
It is the clock gating information that causes the sample to be written at a certain clock so that compression is not performed, or the FIFO data is repeated and some samples are read a plurality of times to perform decompression. .
For example, to handle 4/3 compression (where 4/3 represents the ratio of the number of input samples to the number of output samples), every fourth sample may not be written to the FIFO. The average slope of the ramp read from the luminance FIFO is 33% higher than that of the corresponding input ramp.
Become steep. In this case, the read time of the lamp is 33% less than the time required to write the data. It is the function of the interpolator to recalculate the luminance samples written in the FIFO so that the data read from the FIFO will be smooth without ruggedness.

Decompression can be done in the exact opposite way of compression. In the case of compression, the output F is sent to the write enable signal.
Clock gating information is attached in the form of a write inhibit pulse to the IFO. To expand the data,
The clock gating information is attached to the read enable signal. This causes the data to be paused while being read from the FIFO. Luminance F
The average slope of the ramp read from the IFO is 33 more than the corresponding input ramp for 3/4 stretch or zoom.
%shallow. In this case, it is the function of the interpolator located after the FIFO to recalculate the sample data from the state having the unevenness to the smooth state after the expansion. In the case of decompression, the data is interrupted as it is being read from the FIFO and clocked to the interpolator. This is not the case with compression where the data is continuously clocked through the interpolator. In both cases, the clock gating operation can easily be done in a synchronous manner. That is,
Events occur based on the rising edge of the 1024f _H system clock.

There are numerous advantages to this arrangement for luminance interpolation. Clock gating operations, i.e., data decimation and data repetition, can be performed synchronously. Without the use of switchable video data topologies to switch the positions of the interpolator and FIFO, the write or read clock would have to be double clocked due to data interruption or repetition. The term "double-clocked" means that two data points must be written to the FIFO during one clock cycle, or two data points must be read from the FIFO during one clock cycle. is there. As a result, the write or read clock frequency must be twice the system clock frequency, and the circuit configuration cannot be operated in synchronization with the system clock. Moreover, this switchable topology requires only one interpolator and one FIFO for both compression and decompression purposes. Without the video switching arrangement described here, double clocking can be avoided only with two FIFOs to achieve both compression and decompression functions. In that case, one decompression FIFO must be placed before the interpolator and one compression FIFO must be placed after the interpolator.

The circuit for compressing and expanding the video data comprises a FIFO line memory and an interpolator. A timing circuit writes data to and reads data from the line memory and generates control signals for compressing and expanding the data. The interpolator smoothes the compressed or decompressed data in the FIFO line memory. A switching network for the first signal path to cause the line memory to precede the interpolator for data decompression and a second signal path for the interpolator to precede the line memory for data compression. The signal path of is selectively formed. This switching network is controlled, for example by a microprocessor, according to the selected display format that requires compression or decompression.

The horizontal pan video system according to the present invention comprises a video display having a wide format display ratio for displaying a video signal. A signal processor having an interpolator and a first-in first-out (FIFO) line memory with asynchronous write and read ports is provided for selectively expanding and compressing the screen represented by the data in the video signal. The screen is truncated to control the writing of data to the line memory to define the subset of the screen to be displayed (the set of pixels that are part of the original entire screen). A microprocessor for the controller provides a control signal having a selectable duration and a selectable phase for the sync component of the video signal to select a boundary of the screen subset for display. The microprocessor can select this duration and phase at the user's command.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Each of FIGS. 1 (a)-(i) illustrates some of the various combinations of single and multiple screen display formats that can be implemented in accordance with the different configurations of the present invention. . The ones chosen for illustration are to facilitate the description of certain specific circuits that make up a widescreen television in accordance with the principles of the present invention. The arrangement of the present invention, in some cases, is directed to the display format itself, apart from the particular circuit arrangement. For convenience of illustration and description, it is generally assumed that the width-to-height ratio of a video source or a normal display format for a video signal is 4 × 3, and that of a wide-screen display format for a video source or a video signal is generally The width-to-height ratio is 16 × 9. The structure of the present invention is not limited by these definitions.

FIG. 1 (a) shows a direct-view type or projection type television having a display ratio of a normal format of 4.times.3. 16 × 9 format display ratio screen is 4 × 3
When transmitted as a format display ratio signal, black bars appear at the top and bottom. This is generally called a mail box format. In this case, the observed screen is small with respect to the display area available for display.
Alternatively, a 16 × 9 format display ratio source may be converted prior to transmission to fill the viewing plane vertically of a 4 × 3 format display. However, in that case, considerable information is truncated from the left and / or right. In yet another alternative, the postbox format may be stretched vertically rather than horizontally, but this causes distortion due to vertical stretching. None of these three methods are particularly attractive.

FIG. 1 (b) shows a 16 × 9 screen. Video sources with a display ratio of 16x9 format are perfectly displayed without truncation and without distortion. 16x9 format display ratio mail box screen (this is originally a 4x3 format display ratio signal)
Are sequentially scanned by line doubling or line addition to provide a large display with sufficient vertical resolution. A widescreen television according to the present invention can display such a 16x9 format display ratio signal regardless of the primary video source, secondary video source, or external RGB source.

FIG. 1 (c) shows a main signal of 16 × 9 format display ratio in which an insertion screen of 4 × 3 format display ratio is inserted and displayed. If both the primary and secondary video signals are 16x9 format display ratio sources, the inset screen will also have a 16x9 format display ratio. The inset screen can be displayed in many different positions.

FIG. 1 (d) shows a display format in which the main and sub video signals are displayed as a screen of the same size. Each display area has an 8x9 format display ratio,
This, of course, differs from 16x9 and 4x3.
In order to display a 4x3 format display ratio source in such a display area without horizontal or vertical distortion, the left and / or right side of the signal must be truncated. If you can tolerate some aspect ratio distortion from squeeze the screen horizontally, you can cut down the screen and display more. As a result of the horizontal packing, things in the screen become vertically elongated. The wide-screen television of the present invention can perform any combination of truncation and aspect ratio distortion, from maximum truncation processing with no aspect ratio distortion to no truncation with maximum aspect ratio distortion.

The data sampling limitation of the sub video signal processing path complicates the generation of a high resolution screen of the same size as the display from the main video signal. Various methods can be developed to eliminate such complications.

FIG. 1 (e) shows a display format in which a 4 × 3 format display ratio screen is displayed in the center of the 16 × 9 format display ratio screen. Black bars appear on the left and right sides.

FIG. 1 (f) shows a display format in which one large 4 × 3 format display ratio screen and three small 4 × 3 format display ratio screens are displayed simultaneously.
A small screen outside the periphery of a large screen is sometimes a PI
P, that is, not the in-screen screen (parent-child screen), but POP,
That is, it is called an off-screen screen. The term PIP or picture-in-picture is used herein for these two display formats. If a widescreen television is equipped with two tuners, even if they are both internal, one internal and one external, eg a videocassette recorder, the display screen Two of them are
You can display the movement in real time according to the video source. The remaining screens can be displayed in still screen format. It will be understood that three or more moving pictures can be displayed by adding a tuner and a sub signal processing path. Also, a large screen and 3
It is also possible to switch the positions of the two small screens as shown in FIG.

FIG. 1 (h) shows another display in which a 4 × 3 format display ratio screen is displayed in the center and six small 4 × 3 format display ratio screens are displayed in columns on both sides.
Similar to the format described above, a wide screen television provided with two tuners can display two moving screens. Then, the remaining 11 screens are displayed in the still screen format.

FIG. 1 (i) shows a checkerboard display format of 12 4 × 3 format display ratio screens. Such a display format is particularly suitable for channel selection guides, where each screen is at least a static screen from a different channel. As in the previous example, the number of moving screens depends on the number of tuners and signal processing paths available.

The various formats shown in FIG. 1 are exemplary and not limiting, and are shown in the remaining figures,
It can be realized by a wide screen television described in detail below.

A general block diagram of a widescreen television configured for 2f _H horizontal scanning according to the present invention is shown in FIG. 2 and is generally designated by 10. Generally speaking, the television 10 includes a video signal input section 20, a chassis or TV microprocessor 216, a wide screen processor 30, 1f.
_H- 2f _H converter 40, deflection circuit 50, RGB interface 60, YUV-RGB converter 240, video tube drive circuit 242, direct-view type or projection type tube 244, and power supply
Contains 70. Grouping various circuits into different functional blocks is for convenience of description,
It is not intended to limit the physical positional relationship between such circuits.

The video signal input section 20 is adapted to receive a plurality of composite video signals from different video sources. The video signal can be selectively switched between the main video signal and the sub video signal. RF switch 20
4 has two antenna inputs ANT1 and ANT2. These inputs represent inputs for both reception by the radio broadcast antenna and reception from the cable. The RF switch 204 controls which antenna input is supplied to the first tuner 206 and the second tuner 208. The output of the first tuner 206 is the one-chip 202
Will be input to. The one-chip 202 performs many functions related to tuning control, horizontal and vertical deflection control, video control. The one chip shown is an industrial TA7730. One-chip baseband video signal VIDEO OUT generated from the signal from the first tuner 206
Is an input to the TV switch input of the video switch 200 and the wide screen processor 30. Video switch 20
Other baseband video inputs to 0 are AUX1 and AUX
2 is shown. These inputs can be used in video cameras, laser disc players, video tape players video games and the like. The output of the video switch 200 controlled by the chassis or TV microprocessor 216 is shown as SWITCHED VIDEO. This SWITCHED VIDEO is provided as another input to the widescreen processor 30.

Referring to FIG. 3, the switch SW1 widescreen processor provides a SEL COMP OUT video signal which is an input to the Y / C decoder 210.
One of the TV1 signal and the SWITCHED VIDEO signal is selected. The Y / C decoder 210 can be implemented in the form of an adaptive line comb filter. To the Y / C decoder 210,
In addition, two video sources S1 and S2 are also input. Each of S1 and S2 represents a different S-VHS source, each consisting of a separate luminance and chrominance signal. In response to the TV microprocessor 216, switches Y_M and C_IN, which may be implemented as part of the Y / C decoder in some adaptive line comb filters, or which may be implemented as separate switches, are provided. A pair of luminance and chrominance signals is selected as the output labeled as. The selected paired luminance and chrominance signals are then regarded as the main signal and processed along the main signal path. _M or _MN
Signal notations including "" represent the main signal path. The chrominance signal C_IN is returned to the one chip by the wide screen processor again to generate the color difference signals U_M and V_M. Here, U represents the same as (RY), and V is the same as (BY). The Y_M, U_M and V_M signals are converted to digital form by a wide screen processor for subsequent signal processing.

Functionally, the wide screen processor 3
A second tuner 208, defined as part of 0, produces the baseband video signal TV2. Switch SW2
The TV2 signal and the S signal are input to the Y / C decoder 220.
Select one of the WITCHED VIDEO signals. Y / C
Decoder 220 can be implemented as an adaptive line comb filter. The switches SW3 and SW4 are used for the Y / C decoder 22.
0 luminance and chrominance outputs, and Y_
Select one of the luminance and chrominance signals of the external video source designated EXT and C_EXT. The Y_EXT and C_EXT signals are Y / X corresponding to the S-VHS input S1.
The C decoder 220 and switches SW3 and SW4 may be combined, as is done with some adaptive line comb filters. The outputs of switches SW3 and SW4 are then considered the sub-signal and are processed along the sub-signal path. The selected luminance output is shown as Y_A. Signal notations including _A, _AX and _AUX are used for the sub-signal paths. The selected chrominance is converted into color difference signals U_A and V_A. The Y_A, U_A and V_A signals are converted to digital form for subsequent signal processing. The configuration of switching video signal sources in the main and sub-signal paths allows for greater flexibility in how to select video sources for different parts of different screen display formats.

Composite sync signal COMP corresponding to Y_M
SYNC is provided to the sync separator 212 from the widescreen processor. The horizontal and vertical sync components H and V are input to the vertical countdown circuit 214. The vertical countdown circuit is a VERTICAL RESET (vertical reset) supplied to the widescreen processor 30.
Generate a signal. Widescreen processor is RG
The internal vertical reset output signal INT VERT RST OUT supplied to the B interface 60 is generated.
A switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical sync component of the external RGB source. The output of this switch is the selected vertical synchronization component SEL_VERT_SY supplied to the deflection circuit 50.
It is NC. The horizontal and vertical sync signals of the sub video signal are
Generated by sync separator 250 in the widescreen processor.

The 1f _H -2f _H converter 40 functions to convert an interlaced scanning video signal into a non-interlaced signal which is sequentially scanned. For example, each horizontal line is displayed twice, or additional horizontal line sets are generated by interpolation of adjacent horizontal lines in the same field. In some examples, whether to use the previous line or the interpolated line depends on the level of motion detected between adjacent fields or frames. The conversion circuit 40 operates in association with the video RAM 420. Video RAM is
Used to store one or more fields of a frame for sequential display. Y_2f _H ,
The converted video data as U_2f _H and V_2f _H signals are supplied to the RGB interface 60.

The RGB interface 60, shown in detail in FIG. 14, allows the selection of converted video data or external RGB video data for display by the video signal input. The external RGB signals are wide format display ratio signals adapted for 2f _H scanning. The vertical sync component of the main signal is passed to the INT VERT to the RGB interface by the wide screen processor.
Provided as RST OUT to enable the selected vertical sync (f _Vm or f _Vext ) to be provided to the deflection circuit 50. By the operation of this wide screen television, the internal / external control signals INT / EXT are generated, and the user can select the external RGB signals.
However, if such an external RGB signal is not present, selecting the external RGB signal input can result in vertical collapse of the raster and damage to the cathode ray tube or projection tube. Therefore, in order to invalidate the selection of the external RGB input which does not exist in the RGB interface circuit,
Detect the external sync signal. WSP microprocessor 3
The reference numeral 40 also controls the color and tone of the external RGB signals.

The wide screen processor 30 includes a picture-in-picture processor 320 which performs special signal processing of the sub video signal. The term screen-on-screen sometimes refers to PIP or pix-in-pix
Abbreviated as (pix-in pix). Gate array 300 combines primary and secondary video signal data in various display formats, such as those shown in the examples of Figures 1 (b)-(i). In-screen screen processor 320 and gate array 300
Is a widescreen microprocessor (WSP μ
P) Under control of 340. Microprocessor 340
Responds to the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock signals, enable signals and reset signals. Widescreen processor 30 also generates a composite vertical blanking / reset signal as a three-level sandcastle (sand castle) signal. Alternatively, the vertical blanking signal and the reset signal may be generated as separate signals. The composite blanking signal is supplied to the RGB interface by the video signal input.

The deflection circuit 50, shown in more detail in FIG. 13, receives the vertical reset signal from the widescreen processor.
It receives the 2f _H horizontal sync signal selected from the RGB interface 60 and also an additional control signal from the widescreen processor. This additional control signal relates to horizontal phase adjustment, vertical size adjustment, and left / right pin adjustment. The deflection circuit 50 supplies the 2f _H flyback pulse to the widescreen processor 30, the 1f _H -2f _H converter 40 and the YUV-RGB converter 240.

The operating voltage for the entire widescreen television is generated, for example, by a power supply 70 which can be powered by an AC mains power supply.

The widescreen processor 30 is shown in more detail in FIG. The main components of the widescreen processor are the gate array 300, the in-screen screen circuit 301,
An analog-digital converter and a digital-analog converter, a second tuner 208, a widescreen processor / microprocessor 340 and a widescreen output encoder 227. A detailed portion of the widescreen processor common to both the 1f _H and 2f _H chassis, eg the PIP circuit, is shown in FIG. P
The in-screen screen processor 320, which forms an important part of the IP circuit 301, is shown in more detail in FIG. Also,
The gate array 300 is shown in more detail in FIG. The large number of elements forming the main and sub-signal paths shown in FIG. 3 have already been described in detail.

The second tuner 208 has an IF stage 224.
And an audio stage 226 is attached. The second tuner 208 also works with the WSP μP 340.
WSP μP 340 includes input / output I / O unit 340A and analog output unit 340B. I / O section 340A
Is a tint control signal and color control signal, external R
An INT / EXT signal for selecting a GB video source and a control signal for the switches SW1 to SW6 are supplied.
The I / O part also has an EXT SYNC D from the RGB interface to protect the deflection circuit and the cathode ray tube.
Monitor the ET signal. The analog output section 340B includes the interface circuits 254, 256 and 25, respectively.
Through 8, the control signals for vertical size, left-right adjustment and horizontal phase are supplied.

The gate array 300 combines the video information from the primary and secondary signal paths to create a composite widescreen display, eg, one of those shown in different parts of FIG.
Work to make one. The clock information for the gate array is provided by the phase locked loop 374 which works in concert with the low pass filter 376. The main video signal is in analog form and is provided to the widescreen processor in YUV format as the signals labeled Y_M, U_M and V_M. These main signals are converted from analog to digital form by analog-to-digital converters 342 and 346 shown in more detail in FIG.

The color component signals are designated by the broad notations U and V, which are RY or. It can be attached to the BY signal or the I and Q signals. The system clock frequency is 1024 f _H , which is about 16 MH
Since z, the bandwidth of the sampled luminance is limited to 8 MHz. U and V signals are 500KH
Since z or wide I is limited to 1.5 MHz, the color component data can be sampled by one analog-digital converter and analog switch. This analog switch, the select line UV_MUX for the multiplexer 344, is the 8 MHz signal obtained by dividing the system clock by two. A 1 clock wide line start SOL pulse synchronously resets this signal to 0 at the beginning of each horizontal video line. Then UV_
Through the horizontal line, the MUX line reverses state every clock cycle. Since the length of the line is an even multiple of the clock cycle, once initialized, the state of UV_MUX changes to 0, 1, 0, 1, ... Without interruption. Y from analog-to-digital converters 342 and 346
And the UV data stream is shifted because the analog-to-digital converters each have a delay of one clock cycle. To accommodate this data shift, the clock gating information from the interpolator controller in main signal processing path 304 must also be delayed. If this clock gating information is not delayed, the UV data will not be properly paired when the deletion is performed. This point is important because each UV pair represents one vector. When the U component from one vector is paired with the V component from another vector, color shift occurs. The V samples from the preceding pair are
It is deleted together with the U sample at that time. This UV multiplex method is 2: 1: 1 because there are two luminance samples for each color component (U, V) sample pair.
Is called. The Nyquist frequency for both U and V is effectively reduced to one half of the luminance Nyquist frequency. Therefore, the Nyquist frequency of the output of the analog-digital converter for the luminance component is 8 MHz.
On the other hand, the Nyquist frequency of the output of the analog-digital converter for the color component is 4 MHz.

The PIP circuit and / or the gate array is
Means may be included so that the resolution of the sub-data is enhanced even with data compression. For example, paired
Many data reduction and data recovery schemes have been developed, including pixel compression and dithering and dithering. Furthermore, different dithering sequences with different numbers of bits and different pairs of pixel compressions with different numbers of bits have been considered. One of a number of specific data reduction and recovery schemes selected by the WSP μP340
The resolution of the displayed video may be maximized for each particular screen display format.

The gate array consists of FIFOs 356 and 358.
It includes an interpolator that operates in cooperation with a line memory that can be realized as. The interpolator and FIFO are used to resample the main signal as needed. The side signal can be resampled by a separate interpolator. A clock and synchronization circuit in the gate array controls the data manipulation of both the primary and secondary signals, including combining the primary and secondary signals to produce one output video signal having Y_MX, U_MX and V_MX components. The output components are converted to analog form by digital-to-analog converters 360, 362 and 364. The signals in the analog format indicated by Y, U and V are 1 for conversion to non-interlaced scanning.
It is supplied to the f _H -2f _H converter 40. Also, the Y, U and V signals are encoded into the Y / C format by the encoder 227 and are output to the wide jack ratio output signal Y_OUT_EXT_ / C_OUT_ to the jack of the panel.
EXT is generated. The switch SW5 is the encoder 2
The sync signal for 27 is C_SY from the gate array.
NC_MN and C_SYNC_AUX from PIP circuit
Select from. The switch SW6 serves as a synchronization signal for widescreen panel output, and outputs Y_M and C_SYNC_.
Select either AUX.

The portion of the horizontal sync circuit is shown in more detail in FIG. The phase comparator 228 is part of a phase locked loop including a low pass filter 230, a voltage controlled oscillator 232, a divider 234 and a capacitor 236. The voltage controlled oscillator 232 operates at 32f _H in response to a ceramic resonator or equivalent 238. The output of the voltage controlled oscillator is divided by 32 and provided to the phase comparator 228 as a second input signal at the appropriate frequency. The output of divider 234 is the 1f _H REF timing signal. 32f _H REF timing signal and 1f _H REF
The timing signal is supplied to the 1/16 counter 400. The 2f _H output is supplied to the pulse width circuit 402. By presetting the frequency divider 400 with the 1f _H REF signal, the frequency divider is guaranteed to operate synchronously with the phase locked loop of the video signal input. The pulse width circuit 402 ensures that the 2f _H -REF signal has sufficient pulse width to allow the phase comparator 404, eg, CA 1391, to operate properly. Phase comparator 404
Is a low pass filter 406 and a 2f _H voltage controlled oscillator 4
It constitutes a part of the second phase locked loop including 08. Voltage controlled oscillator 408 generates an internal 2f _H timing signal, which is used to drive a progressively scanned display. The other input signal to the phase comparator 404 is a 2f _H flyback pulse or timing signal associated therewith. The use of a second phase locked loop including the phase comparator 404 helps to make each 2f _H scan period symmetrical within each 1f _H period of the input signal. Failure to do so would result in raster separation, eg, half of the video lines would shift to the right and half of the video lines would shift to the left.

The deflection circuit 50 is shown in detail in FIG. Circuitry 500 is provided to adjust the vertical size of the raster depending on the amount of vertical overscan required to achieve different display formats. As shown diagrammatically, constant current source 502 provides a constant amount of current I _RAMP that charges vertical ramp capacitor 504. A transistor 506 is coupled in parallel with the vertical ramp capacitor and periodically discharges this capacitor in response to a vertical reset signal. Without any adjustment, the current I _RAMP gives the raster the maximum possible vertical size.
This corresponds to the magnitude of vertical overscan required to fill a widescreen display with an expanded 4 × 3 format display ratio signal source, as shown in FIG. If a smaller vertical raster size is required, the adjustable current source 508 _{pulls a} variable amount of current I from I _{RAMP.
The ADJ} is shunted to charge the vertical ramp capacitor 504 more slowly and to a smaller peak value. The variable current source 508 is responsive to the vertical size adjustment signal, eg, in analog form, generated by the vertical size control circuit. Vertical size adjustment 500 is manual vertical size adjustment 5
Independent of 10, this manual vertical size adjustment can be done with a potentiometer or rear panel adjustment knob. In either case, the vertical deflection coil 5
12 receives an appropriate amount of drive current. Horizontal deflection is
Phase adjustment circuit 518, left and right pin correction circuit 514, 2f _H
Provided by phase locked loop 520 and horizontal output circuit 516.

The RGB interface 60 is shown in more detail in FIG. The final signal displayed is
It is selected from the output of the 1f _H -2f _H converter 40 and the external RGB input. To describe the widescreen television described herein, assume that the external RGB input is a progressive scan source with a wide format display ratio. The external RGB signal and the composite blanking signal from the video signal input unit 20 are input to the RGB-YUV converter 610. External RGB
The external 2f _H composite sync signal for the signal is input to the external sync signal separator 600. The vertical synchronizing signal is selected by the switch 608. The switch 604 selects the horizontal synchronizing signal. The selection of the video signal is performed by the switch 606. Switches 604, 60
6, 608 each responds to internal / external control signals generated by WSP μP 340. The choice of internal video source or external video source is a user choice. However, if the user inadvertently selects such an external source when the external RGB sources are not connected or turned on, or if the external source disappears, the vertical raster collapses, It can cause serious damage to the cathode ray tube. Therefore, the external sync detector 602 detects the presence of the external sync signal. In the absence of this signal, a switch disable control signal is sent to each switch 604, 606, 608 to prevent such external RGB source from being selected in the absence of the signal from the external RGB source. RGB-YUV converter 610 is also WS
It receives color tone and color control signals from P μP 340.

Although not shown, the wide screen television according to the configuration of the present invention can be implemented by 1f _H horizontal scanning instead of 2f _H horizontal scanning. 1f
_{If the H} circuit is used, neither the 1f _H -2f _H converter nor the RGB interface is required. Therefore, there is no means for displaying the external wide format display ratio RGB signal of the 2f _H scanning frequency. The wide screen processor for the 1f _H circuit and the in-screen screen processor will be very similar. The gate array may be substantially the same, but not all inputs and outputs will be used. The various resolution enhancement schemes described herein generally refer to televisions operating at 1f _H scan, 2f _H
It can be adopted regardless of whether it operates by scanning.

FIG. 4 can be the same for both the 1f _H and 2f _H chassis. FIG. 4 is a block diagram showing the widescreen processor 30 shown in FIG. 3 in more detail. The Y_A, U_A and V_A signals are inputs to an in-screen screen processor 320 which may include resolution processing circuitry 370. A widescreen television according to one aspect of the invention is capable of video decompression and compression. Special effects realized by various composite display formats, some of which are shown in FIG. 1, are generated by the in-screen screen processor 320. This processor 320
It can be configured to receive the resolution processed data signals Y_RP, U_RP and V_RP from the resolution processing circuit 370. Resolution processing is not always necessary and is done during the selected display format. In-screen screen processor 320 is shown in more detail in FIG. The main components of the screen processor in the screen are the analog-digital converter unit 322, the input unit 324, the high speed switch (FS).
W) and bus section 326, timing and control section 328,
And a digital-analog converter 330. Details of the timing and control unit 328 are shown in FIG.

The in-screen screen processor 320 is, for example,
It can be implemented as a modification of the basic CPIP chip developed by Thomson Consumer Electronics Incorporated. For more information on this basic CPIP chip, see The CTC 140 Picture in P published by Thomson Consumer Electronics, Inc. of Indianapolis, Indiana.
icture (CPIP) Technical Training Manual (CTC 140
On-Screen Display (CPIP) Technical Training Manual) "
It is described in. Many features or special effects are possible. The following is an example. The basic special effect is that a small screen is placed on a large screen as shown in FIG. These large and small screens may come from the same video signal or different video signals, and they can be interchanged. In general, audio signals are always switched to accommodate large screens. The small screen can be moved to any position on the screen or can be moved to a number of predetermined positions. The zoom effect increases or decreases the size of the small screen to, for example, any of a number of preset sizes. At a certain point, for example, in the case of the display format shown in FIG. 1D, large and small screens have the same size.

In the case of the single screen mode, for example, the mode shown in FIG. 1 (b), FIG. 1 (e) or FIG. 1 (f), the user can change the content of the single screen to, for example, 1.0. : 1 to
In zoom mode, which allows you to zoom in stepwise in a range of 5.0: 1 ratio, the user can search or pan the screen contents to see the image on the screen in different areas of the screen. Can be moved. In any case, a small screen, a large screen, or a zoomed screen can be displayed as a still screen (still screen format). This feature enables a strobe format that repeatedly displays the last 9 frames of video on the screen. The frame repetition rate can vary from 30 to 0 frames per second.

The in-screen screen processor used in a widescreen television according to another configuration of the present invention differs from the current configuration of the basic CPIP chip described above. If the basic CPIP chip is used with a television having a 16x9 screen and no video speedup circuit is used, then by scanning a wide 16x9 screen, it is effectively 4/3 times horizontally. Is increased, which causes distortion of the aspect ratio. Things on the screen are horizontally elongated. When the external speedup circuit is used, aspect ratio distortion does not occur, but the screen does not fill the entire screen.

Existing in-screen screen processors based on basic CPIP chips, such as those used in conventional television, are operated in a special way with some undesirable consequences. Incoming video is sampled with a 640f _H clock locked to the horizontal sync signal of the primary video source. That is, the data stored in the video RAM associated with the CPIP chip is not sampled orthogonally to the incoming secondary video source. This is the fundamental limitation on field synchronization by the basic CPIP method. Due to the non-orthogonal nature of the input sampling rate, skewed errors occur in the sampled data. This limitation is a result of using video RAM with CPI chips that must use the same clock to write and read data. For example, video RAM35
When data from a video RAM such as 0 is displayed, skew errors appear as random jitter along the vertical edges of the screen and are generally considered very annoying.

Unlike the basic CPIP chip, the in-screen screen processor 320 according to the present invention has been modified to asymmetrically compress video data in one of a plurality of display modes. In this mode of operation, the screen is compressed 4: 1 horizontally and 3: 1 vertically. This asymmetric compression mode produces a screen with aspect ratio distortion and stores it in video RAM.
Things on the screen are packed horizontally. However, when these screens are read as usual, for example in channel scan mode, and displayed on a 16x9 format display ratio screen, the screens look correct. This screen fills the screen and has no aspect ratio distortion. With the asymmetric compression mode according to this aspect of the invention, it is possible to create a special display format on a 16x9 screen without the use of external speedup circuitry.

FIG. 11 is a block diagram of the timing and control unit 328 of the in-screen screen processor in which the above-mentioned CPIP chip is changed, for example, and this timing and control unit 328 is one of a plurality of selectable display modes. Decimation (decimatio
n) Includes circuit 328C. The remaining display modes can generate sub-screens of different sizes. Each of the horizontal and vertical decimation circuits includes a counter programmed to determine the compression factor from a table of values under the control of the WSP μP340. The range of values is 1: 1, 2: 1,
It can be 3: 1 etc. The compression factors can be symmetrical or asymmetrical, depending on how the table is organized. The control of the compression ratio can be performed by a fully programmable general purpose decimation circuit under the control of the WSP μP340.

In full screen PIP mode, the in-screen screen processor working with free-running oscillator 348 receives the Y / C input from a decoder, which may be, for example, an adaptive line comb filter, and signals this signal Y, U, V. Decode into color components and generate horizontal and vertical sync pulses. These signals are processed by an in-screen screen processor for various full screen modes such as zoom, freeze, channel scan, and so on. For example, during the channel scan mode, horizontal and vertical syncs from the video signal input may be such that the sampled signals (different channels) have unrelated sync pulses, and are apparently random in time. It will be interrupted many times because it can be switched with. Therefore, the sample clock (and read / write video RA
M clock) is determined by the free-running oscillator. For stationary and zoom modes, the sample clock is locked to the incoming video horizontal sync signal. In these special cases, the frequency of the incoming video horizontal sync is the same as the display clock frequency.

Referring again to FIG. 4, Y, U, V and C-- SYN in analog form from the on-screen screen processor.
The C (composite sync) output is Y / C by the encoder circuit 366.
It can be re-encoded into components. Encoder circuit 36
6 operates in cooperation with the 3.58 MHz oscillator 380.
This Y / C_PIP_ENC signal may be connected to a Y / C switch (not shown) that allows the recoded Y / C component to be used in place of the Y / C component of the main signal. After this point, the PIP encoded Y, U, V and sync signals are
Provides the basis for horizontal and vertical timing in the rest of the chassis. This mode of operation is based on the interpolator and F in the main signal path.
It is suitable for executing the PIP zoom mode based on the operation of the IFO.

Still referring to FIG. 5, the in-screen screen processor 320 includes an analog-digital conversion unit 322, an input unit 324, a high speed switch FSW and a bus control unit 32.
6, a timing and control unit 328, and a digital-analog conversion unit 330. In general, the in-screen screen processor 320 digitizes the video signal into luminance (Y) and color difference signals (U, V), subsamples the results and stores them in the 1 Mbit video RAM 350 as described above. In-screen screen processor 32
The video RAM 350 attached to 0 has a memory capacity of 1 megabit, which is not large enough to store one field of video data in 8 bit samples. Increasing memory capacity would be expensive and would require more complex operating circuitry.
Reducing the number of bits per sample in the sub-channel means a reduction in quantization resolution or bandwidth for the main signal, which is processed with 8-bit samples throughout. This effective bandwidth reduction is usually not a problem when the sub-display screen is relatively small, but is a problem when the sub-display screen is relatively large, for example, the same size as the main display screen. Could be. The resolution processing circuit 370 may selectively implement one or more concepts to enhance the quantization resolution or effective bandwidth of the secondary video data. For example, numerous data reduction and data recovery schemes have been developed that include anti-pixel compression and dithering and inverse dithering. The dithering circuit is located downstream of the video RAM 350, eg, in the sub-signal path of the gate array, as will be described in more detail below. Furthermore, different dithering and de-dithering sequences with different numbers of bits and different pairwise pixel compression with different numbers of bits are possible. In order to maximize the resolution of the displayed video for each particular screen display format, one of many specific data reduction and recovery schemes is used.
It can be selected by SP μP.

The luminance and color difference signals are stored in 8: 1: 1 6-bit Y, U, V format. That is, each component is quantized into 6-bit samples. There are 8 luminance samples for each pair of color difference samples. The in-screen screen processor 320 is operated in a mode such that incoming video data is sampled at the 640f _H clock frequency locked to the incoming secondary video sync signal. In this mode, the data stored in video RAM is orthogonally sampled. When the data is read from the video RAM 350 of the in-screen screen processor, this data is read using the same 640f _H clock locked to the incoming secondary video signal. However, this data is orthogonally sampled and stored, and can be read orthogonally, but due to the asynchrony of the primary and secondary video sources, cannot be directly displayed from video RAM 350. The primary and secondary video sources are considered to be in sync only when they are displaying signals from the same video source.

Further processing is required to synchronize the sub-channel, which is the output of data from the video RAM 350, with the main channel. Referring again to FIG. 4, two 4-bit latches 352A and 352B are used to recombine the 8-bit data block from the 4-bit output port of the video RAM. The 4-bit latches, the data clock frequency from 1280f _H 640
Lower to f _H.

Generally, the video display and deflection system is synchronized to the main video signal. As mentioned above, the main video signal must be sped up in order to fill the widescreen display. The secondary video signal must be vertically synchronized with the first video signal and the video display. The sub video signal can be delayed in the field memory by a fraction of one field period and expanded in the line memory. The synchronization of the sub video data to the main video data is performed by using the video RAM 350 as a field memory and the first-in first-out (FIFO) line memory device 354 for signal expansion. The size of the FIFO 354 is 2048 × 8.
The size of the FIFO depends on the read / write pointer collision (c
ollision) related to the lowest linear storage capacity reasonably considered necessary. Read / write pointer collisions occur when old data is read from the FIFO before it is time for new data to be written to the FIFO. Read / write pointer collisions also occur when new data overwrites memory before it is time to read the old data from the FIFO.

8-bit DA from video RAM 350
The TA_PIP data block is the same in-screen screen processor 6 used to sample the video data.
2048 × 8FI with 40f _H clock, ie, 640f _H clock locked to sub-signal instead of main signal
Written to FO354. FIFO 354 is a 1024f _H locked to the horizontal sync component of the main video channel.
It is read using the display clock of. By using a multi-line memory (FIFO) having independent read and write port clocks, the data sampled orthographically at the first frequency can be orthographically displayed at the second frequency. However, due to the asynchronous nature of both read and write clocks, it is not necessary to take measures to avoid read / write pointer collisions.

The primary signal path 304, the secondary signal path 306 and the output signal path 312 of the gate array 300 are shown in block diagram form in FIG. The gate array also has a clock /
It includes a synchronization circuit 320 and a WSP μP decoder 310. WSP DATA of the WSP μP decoder 310
The data and address output lines indicated by are supplied to the above-mentioned main circuit and signal path as well as the in-screen screen processor 320 and the resolution processing circuit 370. Whether or not a circuit forms a part of the gate array is almost a matter of convenience for facilitating the description of the structure of the present invention.

The gate array acts to decompress, compress, or truncate the main video channel as needed to implement different screen display formats. Luminance component Y_MN is a first-in first-out (FIFO) for a length of time according to the nature of the interpolation of the luminance component.
It is stored in the line memory 356. The combined chrominance component U / V_MN is stored in FIFO 358. Luminance and chrominance components of the side signal Y_PIP, U
_PIP and V_PIP are generated by the demultiplexer 355. If necessary, the luminance component is subjected to resolution processing by the circuit 357, and if necessary, the interpolator 3
It is expanded by 59 to produce the signal Y_AUX as output.

In some cases, the sub-display may have the same size as the main signal display as shown in FIG. 1 (d). Due to the memory limitations associated with the on-screen screen processor and the video RAM 350, there may be a lack of data points, or pixels, to fill such a large area. In such a case, the resolution processing circuit 357 can be used to recover the pixels that should replace the pixels lost during data compression or reduction into the sub video signal. This resolution processing is performed by the circuit 370 shown in FIG.
Can correspond to what is done by. For example, circuit 370 can be a dithering circuit and circuit 357 can be a dithering circuit.

The sub video input data is sampled at a frequency of 640f _H and stored in the video RAM 350. The sub data is read from the video RAM 350, and VRAM_
Shown as OUT. The PIP circuit 301 can also reduce the sub-screen asymmetrically in the horizontal and vertical directions, and at the same time, reduce it by a factor of the same integer. Referring to FIG. 10, the sub-channel data includes 4-bit latches 352A and 352B, a sub-FIFO.
Buffered and synchronized to main channel digital video by 354, timing circuit 369 and synchronization circuit 368. The VRAM_OUT data is classified by the demultiplexer 355 into Y (luminance), U, V (color components) and FSW_DAT (fast switch data). FSW_DAT indicates which field type was written to the video RAM. The PIP_FSW signal is provided directly from the PIP circuit and is provided to the output control circuit 321 to determine which field read from the video RAM should be displayed in the small screen mode.

The sub-channel is sampled at 640f _H , while the main channel is sampled at 1024f _H. The sub-channel FIFO 354 converts the data from the sub-channel sample frequency to the main channel clock frequency. In this process, the video signal is 8/5
Receives compression of (1024/640). This is greater than the 4/3 compression required to properly display the sub-channel signal. Therefore, the sub-channel must be expanded by the interpolator 359 in order to display a 4 × 3 small screen correctly. The interpolator 359 is controlled by the interpolator control circuit 371, and the interpolator control circuit 371 itself is a WSP.
Responds to μP340. The amount of decompression required by the interpolator is 5/6. The expansion coefficient X is determined as follows.

X = (640/1024) * (4/3) = 5/6

Chrominance components U_PIP and V_PIP
Is delay-matched by a circuit 367 by a length determined by the content of the interpolation of the luminance component, and signals U_AUX and V
_AUX is produced as output. The Y, U and V components of each of the main signal and the sub signal are stored in the FIFO 354, 356.
And 358 by controlling the read enable signal, each multiplexer 3 in the output signal path 312.
15, 317 and 319 combined. The multiplexers 315, 317, 319 are responsive to the output multiplexer control circuit 321. The output multiplexer control circuit 321 includes an in-screen screen processor and a WSP μP340.
Signal CLK, line start signal SOL, H_C from
Responsive to the OUNT signal, the vertical blanking reset signal and the output of the high speed switch. Multiplexed luminance and chrominance components Y_MX, U_MX and V
_MX is each digital / analog converter 36
0, 362 and 364. As shown in FIG. 4, this digital-analog converter 360, 362, 3
In the subsequent stage of 64, low pass filters 361 and 3 are respectively provided.
63 and 365 are connected. Various functions of the on-screen screen processor, gate array and data reduction circuit
WSP μP34 controlled by SP μP340
0 is a TV μP2 connected to this via a serial bus
Reply to 16. The serial bus can be a four wire bus with lines for data, clock signals, enable signals and reset signals, as shown. WS
P μP 340 communicates with various circuits in the gate array through WSP μP decoder 310.

In one case, it is necessary to compress 4 × 3 NTSC video by a factor of 4/3 to avoid aspect ratio distortion of the display screen. In another case,
The video may be stretched to provide horizontal zooming, which typically also involves vertical zooming. Horizontal zooming operations up to 33% can be achieved by reducing the compression to less than 4/3. The sample interpolator is S
It is used to recalculate incoming video to a new pixel location, as the luminance video bandwidth of up to 5.5 MHz in the VHS format occupies a large percentage of the Nyquist folding frequency, which is 8 MHz at 1024 f _H. .

As shown in FIG. 6, the luminance data Y_
The MN is passed through an interpolator 337 in the main signal path 304 which recalculates sample values based on video compression or decompression. Switch or route selector 32
The functions of 3 and 331 are FIFO 356 and interpolator 337.
To invert the topology of the main signal path 304 with respect to the relative position of. That is, these switches are used by the interpolator 337 in the FIF when needed for compression, for example.
Choose to precede O356, or to cause FIFO 356 to precede interpolator 337, as needed for decompression. Switches 323 and 331 respond to route control circuit 335, which itself responds to WSP μP 340. In small screen mode,
It will be recalled that the auxiliary video signal is compressed for storage in the video RAM 350 and for practical purposes only decompression is required. Therefore, switches corresponding to these are not required in the sub signal path.

The main signal path is shown in more detail in FIG. Switch 323 has two multiplexers 325 and 3
27. The switch 331 is embodied by a multiplexer 333. These 3
One multiplexer responds to the route control circuit 335,
The route control circuit 335 itself responds to the WSP μP 340. A horizontal timing / synchronization circuit 339 controls the operation of the latches 347, 351 and the multiplexer 353 and also generates timing signals that control the writing and reading of the FIFO. The clock signal CLK and the line start signal SOL are generated by the clock / synchronization circuit 320. The analog-digital conversion control circuit 369 uses Y_M.
Respond to the most significant bits of N, WSP μP 340, and UV_MN.

The interpolator control circuit 349 uses the intermediate pixel position value (K), the interpolator compensation filter weight (C), and the clock gating information CG for the luminance.
Clock gating information CG for Y and color components
Generates UV. FIFO data decimation so that samples are not written at some clocks to perform compression, or some samples can be read multiple times for decompression.
Alternatively, it is this clock gating information that causes the repetition.

Such compression is shown in FIG. LUMA
The _RAMP_IN line represents the luminance ramp video data written to the FIFO. WR_EN_MN
The _Y signal is valid and high. That is, when this signal is high, it indicates that data is being written to the FIFO. Four
Individual samples are prevented from being written to the FIFO. The uneven line LUMA_RAMP_OUT is
FIFO if the data was not first interpolated
Represents the luminance ramp data read from the. Note that the average slope of the ramp read from the luminance FIFO is 33% steeper than the input ramp. Also, the effective read time required to read this lamp is 33% of the time required to write data.
I also want to pay attention to the small number. As a result, 4/3 compression is performed. The interpolator 337 recalculates the luminance samples written in the FIFO so that the data read from the FIFO is smooth without unevenness.
Is a function of.

Stretching can be done in the exact opposite way of compression. In the case of compression, the write enable signal is provided with clock gating information in the form of an inhibit pulse. For data expansion, clock gating information is applied to the read enable signal. This allows
As shown in FIG. 16, when data is read from the FIFO 356, data interruption is performed. Line LUMA_R
AMP_IN represents the data before it is written to the FIFO 356, and the bumpy line LUMA_RAMP_OUT represents the data when it is read from the FIFO 356. In this case, the recalculation of the sampled data so that it is smooth from the bumpy state is done during this process by the FIFO.
This is the function of the interpolator 337 at a position subsequent to 356. For decompression, the data must be interrupted when being read from FIFO 356 and clocked into interpolator 337. This is different from the compression case where the data is continuously clocked in the interpolator 337. In both compression and decompression cases, clock gating operations can be easily and synchronously performed. That is, the event occurs based on the rising edge of the 1024f _H system clock.

There are numerous advantages to this configuration for luminance interpolation. Clock gating operations, i.e., data decimation and data repetition, can be performed synchronously. Without the use of switchable video data topologies to switch the positions of the interpolator and FIFO, the write or read clock would have to be double clocked due to data interruption or repetition. The term "double-clocked" means that two data points must be written to the FIFO during one clock cycle, or two data points must be read from the FIFO during one clock cycle. is there. As a result, the write or read clock frequency must be twice the system clock frequency, and the circuit configuration cannot be operated in synchronization with the system clock. Moreover, this switchable topology requires only one interpolator and one FIFO for both compression and decompression purposes. Without the video switching arrangement described here, double clocking can be avoided only with two FIFOs to achieve both compression and decompression functions. In that case, one decompression FIFO must be placed before the interpolator and one compression FIFO must be placed after the interpolator.

Interpolation of the sub-signal is performed on the sub-signal path 306. The PIP circuit 301 has 6-bit Y, U, V, 8:
The video RAM 350, which is a 1: 1 memory, is operated to store incoming video data. The video RAM 350 holds two fields of video data in a plurality of memory locations. Each memory location holds 8 bits of data. At each 8-bit position, there is one 6-bit Y (luminance) sample (sampled at 640f _H ) and two other bits. These other 2 bits are fast switch data (FSW_DAT) or U or V sample (8
0f _H those samples) holds a part of either one of. The value of FSW_DAT indicates which type of field was written to the video RAM. Video R
Since two fields of data are stored in the AM 350 and the entire video RAM 350 is read during the display period, both fields are read during the display scanning period.
The PIP circuit 301 uses high-speed switch data to determine which field should be read from the memory and displayed. The PIP circuit always reads the opposite field type to that written to solve the problem of motion fragmentation. If the type of field being read is the opposite of what is being displayed, the even field stored in video RAM will have the top line of that field removed when the field is read from memory. Is reversed. As a result, the small screen maintains correct interlace with no breaks in motion.

The clock / synchronization circuit 320 is a FIFO 35.
It generates the read, write, and enable signals needed to operate 4, 356 and 358. The FIFOs for the primary and secondary channels are enabled to write data for storage for the portion needed to display after each video line. Data is written from one (but not both) of the main and sub-channels required to combine the data from each source on the same line or lines of display. Sub-channel FI
The FO 354 is written in synchronization with the sub video signal, but is read out in synchronization with the main video signal. The main video signal component is synchronized with the main video signal by the FIFOs 356 and 358.
Read out from the memory in synchronization with the main video. The frequency with which the read function is switched between the main channel and the sub-channel is a function of the particular special effect selected.

The generation of another special effect, such as a truncated juxtaposed screen, is done by manipulating the read and write enable control signals to the line memory FIFO. The process for this display format is shown in FIGS.
In the case of the truncated side-by-side display screen, the sub channel 204
As shown in FIG. 7, the write enable control signal (WR_EN_AX) for the 8 × 8 FIFO 354 is (1/2) * (5/12) = 5/12 of the display effective line period, that is, about 41% (post speed). Up (post speed u
p)), or 6 of the effective line period of the sub-channel
Active for 7% (for pre speed up). This corresponds to about 33% truncation (about 67% valid screen) and 5/6 signal expansion by the interpolator. In the main video channel shown in the upper part of FIG. 8, a write enable control signal (WR_EN_MN_Y) to 910 × 8 FIFOs 356 and 358.
Is (1/2) * (4/3) = 0.6 of the display effective line period
Active for 7 or 67%. This corresponds to a truncation of about 33% and a compression ratio of 4/3 applied to the main channel video by a 910 × 8 FIFO.

In each of the FIFOs, the video data is buffered so that it can be read at a particular point in time. The effective area of time in which data can be read from each FIFO depends on the selected display format.
In the illustrated side-by-side truncation mode example, the primary channel video is displayed in the left half of the display and the secondary channel video is displayed in the right half of the display. The arbitrary video portion of each waveform is different for the primary and secondary channels, as shown. The main channel 910 × 8 FIFO read enable control signal (RD_EN_MN) is active for 50% of the display effective line period of the display starting at the beginning of the effective video immediately following the video back porch. Sub-channel read enable control signal (RD_E
N_AX) is activated for the remaining 50% of the display valid line period beginning on the falling edge of the RD_EN_MN signal and ending at the beginning of the front porch of the main channel video. The write enable control signal is synchronized with each FIFO input data (main or sub),
On the other hand, the read enable control signal is synchronized with the main channel video.

The display format shown in FIG. 1D is 2
This is especially desirable because it allows you to view the screens of almost all four fields in a side-by-side format. This display is particularly effective and suitable for a wide format display ratio display, for example, 16 × 9. Most NTSC signals are represented in 4x3 format, which of course corresponds to 12x9. Two NTSC screens with 4x3 format display ratio, these screens are truncated by 33% or 3
3% stuffed, same aspect ratio distortion introduced, 16
It can be displayed on a display with a × 9 format display ratio. Depending on the user's preference, the ratio of screen truncation to aspect ratio distortion can be set to any point between the limits of 0% and 33%. For example, it is possible to display two juxtaposed screens with 16.7% cut and 16.7% cut.

The horizontal display time required for displaying the display ratio of 16 × 9 format is the same as that for displaying the display ratio of 4 × 3 format. This is because both of them have a regular line length of 62.5 μsec. Therefore, the NTSC video signal must be sped up by 4/3 times to maintain the correct aspect ratio without causing distortion. This 4/3 coefficient is the ratio of the two display formats,

## EQU2 ## 4/3 = (16/9) / (4/3) is calculated. A variable interpolator is used in accordance with aspects of the invention to speed up the video signal. In the past, FIFOs with different clock frequencies at the input and output have been used to perform similar functions. For comparison, if two NTSC x 3 format display ratio signals are displayed on one 4 x 3 format display ratio display, each screen may be distorted, truncated, or both by 50%. Must be combined. There is no need for a speedup equivalent to that required for widescreen applications.

In all the above-mentioned operation modes, for example, in the side-by-side screen mode, PIP or POP mode, the main screen can be zoomed, that is, enlarged in the horizontal direction, the vertical direction, or both directions. In a mode where the screen is zoomed horizontally to the point where it is forced to be cut off, it would be convenient if the user could control the horizontal pan so that the user can select the part of the screen to see at any time. Is. As described in detail in connection with FIG. 6, horizontal pan control is desirable for both decompress (main screen zoom) and compress (side-by-side) modes. In the upper left corner of Figure 6, the main FIFO
Selectable interconnections of 356 and main interpolator 337 are shown. The main signal path is shown in detail in FIG. As shown in these figures, the topology of the main signal path depends on whether the system is operating in decompression mode or compression mode. The horizontal pan circuit shown here is independent of these modes and can operate with each mode. For the sake of convenience, the following description will be given only for the main luminance channel. The same pan configuration is equally valid for the main chrominance (U, V) channels.

Of course, panning only the main video signal only makes sense when the main screen is truncated during compression in the side-by-side screen mode or during decompression in the zoom mode. The effect of horizontal pan is shown in FIG. If you zoom the screen to the center, you can see most of the humans and dinosaurs in the screen, cropping some on the right side and some on the left side of the screen. Panning to the right shows most of the dinosaurs, but humans can only see their hind legs. Pan to the left to see most humans and most dinosaurs, but not the dinosaur tail.

The FIFO in the main signal path has independent write and read enable signals. By doing so, both which part of the video signal is stored in memory and when that part is displayed can be controlled independently of each other. Generally, if the signal is expanded and truncated, the truncation can be done with the write enable signal. In this way, only the video to be displayed is stored in the FIFO. further,
Horizontal panning can be done simply by manipulating the write enable window, ie, the period during which writing to the FIFO can occur, during the valid video period. This is shown in FIGS. 18 and 19. FIG. 18 shows a zoomed video signal corresponding to the screen of FIG. 17, for example. This video signal does not represent the actual waveform as it is. FIG. 19 (a) shows the write enable window timed to do a horizontal pan to the right. FIG. 19 (b) shows a write enable window timed to pan horizontally to the center. Further, FIG. 19C shows a write enable window whose time is adjusted to horizontally pan to the left. If writing is enabled early, the effect will be similar to that of the camera panning left and the displayed video will appear to scroll to the right of the display. Conversely, if writing is enabled late,
The same effect as if the camera were panned to the right, with the displayed video scrolling towards the left of the display.

If the signal is compressed and truncated, the truncation is by a write enable signal, or FIG.
The output multiplexer control circuit 321 shown in FIG. In the juxtaposed screen mode, truncation is done by switching to the sub-channel, but panning of the main signal can still be done by manipulating the write enable window as described above.

A certain amount of horizontal pan is performed by operating the read enable window or a combination of the read enable window and the write enable window depending on the display position of the main video and the amount of horizontal overscan of the display. be able to.
However, if the read enable window is set correctly, the operation of the write enable window should be sufficient.

[Brief description of drawings]

1 (a)-(i) show various display formats of a widescreen television.

FIG. 2 is a block diagram of a widescreen television adapted to operate at 2f _H horizontal scan in accordance with various aspects of the present invention.

3 is a block diagram of the widescreen processor shown in FIG. 2. FIG.

4 is a block diagram showing details of the widescreen processor shown in FIG. 3. FIG.

5 is a block diagram of an in-screen screen processor shown in FIG. 4. FIG.

6 is a block diagram of the gate array shown in FIG. 4, showing a main signal path, a sub signal path, and an output signal path.

FIG. 7 is a timing diagram used to describe the generation of the display format shown in FIG. 1 (d) using a fully truncated signal.

FIG. 8 is a timing diagram used to describe the generation of the display format shown in FIG. 1 (d) using a fully truncated signal.

9 is a block diagram showing the main signal path of FIG. 6 in more detail.

10 is a block diagram showing the sub-signal path of FIG. 6 in more detail.

11 is a timing chart of the screen processor in the screen of FIG.
It is a block diagram of a control unit.

FIG. 12 is a block diagram of a circuit that generates an internal 2f _H signal in the 1f _H -2f _H conversion.

13 is a combination block and circuit diagram for the deflection circuit shown in FIG.

FIG. 14 is a block of the RGB interface shown in FIG.

FIG. 15 is a waveform diagram used to describe video compression.

FIG. 16 is a waveform diagram used to describe video decompression.

[Fig. 17] Fig. 17 is a diagram for describing screen trimming by zooming.

FIG. 18 is a timing diagram illustrating horizontal panning of a truncated video signal.

FIG. 19 is a timing diagram for explaining horizontal panning of a truncated video signal.

[Explanation of symbols]

244 Video signal display means 304 Decompression / compression means 339 Means for generating signals for controlling writing and reading 340 Means for controlling control signal generating means 337 Interpolator 356 Line memory

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tamothy William Seager Indiana, United States 46260 Indianapolis Nashua Drive 8318 (72) Inventor Nataniel Hulk Asso, Indiana 46112 Brownsburg East State Road 136 6565

Claims (3)

[Claims] 1. Means for displaying a video signal having a wide format display ratio; for asynchronously writing and / or decompressing and / or decompressing a screen represented by the data in the video signal. And signal processing means including memory means having a read port; means for generating write control signals for controlling writing of the data to the memory means to define a subset of the screen for display; Means for controlling the write control signal generating means to provide the write control signal with a selectable duration and a selectable phase for the sync component of the video signal. 2. Means for displaying a video signal; at least one of selectively expanding and compressing a screen represented by the data in said video signal, and said selectively expanded and compressed screen And signal processing means for defining a subset of the screen for display; writing for controlling writing of the data to the signal processing means and reading from the signal processing means independently of each other; Means for generating a read control signal; controlling the write and read control signal generating means to provide the write and read control signals with a selectable duration and a selectable phase for a sync component of the video signal. And means for selecting boundaries of said subset of said screens for display. 3. Display means having a wide format display ratio for displaying a video signal; interpolator and line memory for selectively expanding or compressing a screen represented by the data in the video signal. Means for truncating the screen to define a subset of the screen for display by controlling writing of the data to the line memory; and a synchronization component of the video signal. A microprocessor for providing a control signal having a selectable duration and a selectable phase to control the truncation means to select a boundary of the subset of the screen for display. system.