JPH06275529A - Manufacturing method of compound semiconductor device - Google Patents

Abstract

PURPOSE:To enable a self-aligned electrode using selective CVD technology to be formed in a compound semiconductor device. CONSTITUTION:After the formation of the second compound semiconductor layer 102 containing Sb on the first compound semiconductor layer 101 formed on a semiconductor substrate 100, an SiO2 film 103 having an aperture part 104 is formed. Later, a W film 105 is selectively formed on the second semiconductor layer 102 exposed in the aperture part 104 using selective W-CVD technology. Through these procedures, the electrode comprising the W film 105 can be selectively formed on the second compound semiconductor layer 102 thereby enabling a self-aligned electrode or another electrode in a fine aperture part to be effectively formed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention mainly uses GaAs. III.
The present invention relates to a method for manufacturing a high-speed electronic device using a group V compound semiconductor, and particularly to a method for forming an electrode.

[0002]

2. Description of the Related Art With the advancement of epitaxial growth technology in recent years, practical application of a circuit using a high-speed device having a structure in which several kinds of compound semiconductors are laminated has been actively studied. Among them, especially heterojunction transistors (hereinafter HB
Since T) has a large current driving capability, it is expected to be applied to a high speed circuit. In order to improve the performance of the HBT, it is effective to reduce the parasitic resistance and the parasitic resistance by reducing the distance between the element and the electrode.

As an electrode forming method suitable for such a purpose, for example, a research group material MW86-10 of the Institute of Electronics and Communication Engineers.
As reported in Volume 7, pp. 1 to 6, there is a technique of forming a base electrode in a self-aligned manner with a width of a side wall of an insulating film separated from an emitter mesa. In this technique, an AuZn / Ni / Au electrode is deposited on a region including an emitter mesa having a first sidewall insulating film and an external base region, and then a second sidewall insulating film is formed on the emitter mesa. After that, Ga is used as a mask on the emitter mesa and the second sidewall insulating film.
An unnecessary region of AuZn / Ni / Au on the As base layer is removed by milling. Then, an alloy process is performed to realize a good ohmic electrode for the GaAs base layer.

[0004]

In the above-mentioned conventional example,
Since the base electrode made of AuZn / Ni / Au is processed by using milling, it lacks in fine workability and has a problem in reliability due to redeposition of Au. Also, AuZ
The n-type electrode achieves ohmic contact by alloying, and there is also a problem that heat resistance is poor in the subsequent steps.

[0005]

A side wall insulating film is formed on an emitter mesa in a self-aligned manner, and then a compound semiconductor non-alloy contact layer containing Sb is selectively grown on a GaAs base layer by using a crystal selective growth technique. To do. Next, a refractory metal is selectively deposited on the compound semiconductor non-alloy contact layer containing Sb. As a result, the heat resistant base electrode can be formed in self-alignment with the emitter mesa.

[0006]

Function: A compound semiconductor layer containing Sb (for example, GaSb
By forming the layer as a non-alloy contact layer on the GaAs layer, a good ohmic electrode for GaAs can be realized by using a refractory metal (eg, W, WSi) electrode. Select W-C for compound semiconductor layer containing Sb
It was experimentally confirmed that the VD technique is applicable.
Therefore, the compound semiconductor layer containing Sb is deposited on the GaAs base and the W electrode is successively deposited on the compound semiconductor layer containing Sb by using the sidewall insulating film formed in self-alignment with the emitter mesa as described above. it can.

[0007]

【Example】

(Embodiment 1) An embodiment of the present invention will be described with reference to the process chart of FIG. A first compound semiconductor layer 101 (for example, Ga) is formed on the semiconductor substrate 100 by using an epitaxial growth technique.
After forming As), the second compound semiconductor layer 102 containing Sb (for example, GaSb) was formed by the epitaxial growth technique (a). Next, after depositing the SiO ₂ film 103 on the sample by the CVD method, the opening portion 10 is formed in the SiO ₂ film 103 by using ordinary lithography and etching techniques.
4 was formed (b). Then, a selective W-CVD technique was applied using a low pressure CVD apparatus to selectively deposit a W film 105 on the second compound semiconductor layer 102 containing Sb exposed from the opening 104 (c). . The selective W-CVD conditions are: gas flow rate: SiH _{4 2} sccm, WF ₆ 1 sccm, total gas pressure: 0.12 torr, substrate temperature: 320 ° C.

In this embodiment, since the W film 105 is deposited on the second compound semiconductor layer 102 containing Sb by using the low pressure CVD, it is possible to form the electrode even in the fine opening 104. Become.

(Embodiment 2) Another embodiment of the present invention is shown in FIG.
This will be described with reference to the process chart of FIG. The first compound semiconductor layer 20 is formed on the semiconductor substrate 200 by using an epitaxial growth technique.
After forming 1 (for example, GaAs), a second compound semiconductor layer 202 (for example, GaAsSb) in which the Sb composition was gradually increased in the film thickness direction was formed by an epitaxial growth technique (a). Then, the sample is SiO ₂ by the CVD method.
After depositing the film 203, an opening portion 204 was formed in the SiO ₂ film 203 using ordinary lithography and etching techniques (b). Then, select W- using a low pressure CVD apparatus.
Sb exposed from the opening 204 by applying the CVD technique
W selectively with respect to the second compound semiconductor layer 202 containing
Film 205 was deposited (c). The selective W-CVD conditions are gas flow rate: SiH ₄ 2sccm, WF ₆ 1sccm, total gas pressure:
0.12 torr, substrate temperature: 320 ° C.

According to the present embodiment, since the first compound semiconductor layer 201 and the second compound semiconductor layer 202 are epitaxially grown by gradually changing the composition, the problems of lattice mismatch and band discontinuity are reduced. it can.

(Embodiment 3) Another embodiment of the present invention will be described with reference to the process chart of FIG. A first compound semiconductor layer 301 is formed on a semiconductor substrate 300 by using an epitaxial growth technique.
After forming (for example, GaAs), a second ultrathin compound semiconductor layer 302 (for example, GaS) containing Sb and having a thickness of several nm is formed.
b) and a third ultrathin compound semiconductor layer 303 having a thickness of several nm
After alternately repeating (for example, GaAs) several cycles, a second ultrathin compound semiconductor layer 302 was formed on the outermost surface by the epitaxial growth technique (a). Next, after depositing the SiO ₂ film 304 on the sample by the CVD method, the opening 305 was formed in the SiO ₂ film 304 by using the ordinary lithography and etching technique (b). Then, the selective W-CVD technique is applied using a low pressure CVD apparatus to form the opening 305.
A W film 306 was selectively deposited on the more exposed second compound semiconductor layer 302 containing Sb (c). The selective W-CVD conditions used were as follows: gas flow rate: SiH ₄ 2sccm, WF
₆ 1sccm, total gas pressure: 0.12 torr, substrate temperature: 320
℃.

According to this embodiment, the second ultrathin compound semiconductor layer 302 and the third compound semiconductor layer 302 are formed on the first compound semiconductor layer 301 layer.
The strained superlattice structure composed of the ultra-thin compound semiconductor layer 303 is adopted, and band discontinuity can be relaxed, and good ohmic contact can be realized between the W film 306 and the first compound semiconductor layer 301.

(Embodiment 4) A fourth embodiment of the present invention is shown in FIG.
It will be described with reference to the process charts shown in FIGS.

On the semi-insulating GaAs substrate 400, the sub-collector layer 4 made of high-concentration n-type GaAs by MBE method.
01, collector layer 402 made of n-type GaAs, base layer 403 made of high-concentration p-type GaAs, n-type AlGaA
After an emitter layer 404 made of s and a sub-emitter layer 405 made of high-concentration n-type GaAs and InGaAs are sequentially stacked, a WSi film 406 is formed by a sputtering method and a first SiO ₂ film 407 is subsequently formed by a CVD method ( Figure 4a). Next, the first SiO ₂ film 407, the WSi film 406, the sub-emitter layer 405, and the emitter layer 404 made of n-type AlGaAs are etched by the same mask using lithography and etching techniques to form an emitter mesa, and an external base is formed. The surface of layer 403 was exposed (Fig. 4b). Next, a second Si is added to the sample by the CVD method.
After depositing the O ₂ film 408, a resist mask 409 having openings in the emitter mesa and the external base region was formed (FIG. 5a).

Next, using the resist mask 409, R
By etching back the SiO ₂ film by IE,
The sidewall SiO ₂ film 41 is self-aligned with the emitter mesa.
The outer base layer was exposed again at the same time that 0 was formed (FIG. 5b).

Next, a base contact layer 411 made of GaAsSb is selectively formed on the external base layer 403 by MOCVD or MOMBE method (FIG. 6).
a). At this time, the Sb composition of GaAsSb is 4
It is gradually increased from the interface with 03. Then, the sample is put into a low pressure CVD apparatus, and the selective W-CVD technique is applied to the base contact layer 41 made of GaAsSb.
A W film 412 was selectively formed on No. 1 (FIG. 6b). The selective W-CVD conditions are gas flow rate: SiH ₄ 2sccm, WF ₆
1 sccm, total gas pressure: 0.12 torr, substrate temperature: 320 ° C
Is. Then, a collector contact hole 413 is formed by using a normal lithography and etching technique to expose the sub-collector layer 401, and then AuGe / Ni / Au is used.
Was formed by a lift-off method (FIG. 7).

Here, in this embodiment, Ga having an Sb gradient composition is used.
Although AsSb is used as the base contact layer 411, low contact resistance can be obtained by increasing the composition until the outermost surface of the base contact layer 411 becomes GaSb.

The same effect can be obtained by using a strained superlattice of GaAs / GaSb as the base contact layer 411 as described in the third embodiment.

In this embodiment, selective W-CVD is applied.
The W film 412 is selectively formed on the base contact layer 411 made of GaAsSb, which enables the base electrode of the HBT to be formed in self-alignment with the emitter mesa.

[0020]

According to the present invention, since the selective W-CVD technique can be applied to the compound semiconductor contact layer containing Sb, the heat-resistant electrode of the compound semiconductor device can be formed in a self-aligned manner. Will be possible.

[Brief description of drawings]

FIG. 1 is a process diagram of a first embodiment of the present invention.

FIG. 2 is a process diagram of a second embodiment of the present invention.

FIG. 3 is a process diagram of a third embodiment of the present invention.

FIG. 4 is a process chart of Example 4 of the present invention.

FIG. 5 is a process diagram of a fourth embodiment of the present invention.

FIG. 6 is a process diagram of Example 4 of the present invention.

FIG. 7 is a process chart of Example 4 of the present invention.

[Explanation of symbols]

100 ... Semiconductor substrate, 101 ... First compound semiconductor layer,
102 ... Second compound semiconductor layer, 103 ... SiO ₂ film,
104 ... Opening part.

Claims (5)

[Claims] 1. A second compound containing Sb on a first compound semiconductor layer.
Step of stacking the compound semiconductor of above, step of forming an insulating film mask on the second compound semiconductor layer, and metal selection CV
A method of manufacturing a compound semiconductor device, comprising the step of selectively depositing a metal film on the second compound semiconductor layer exposed from the insulating film mask by using the D method. 2. The second composition according to claim 1, wherein the Sb composition is gradually increased on the first compound semiconductor layer to contain the Sb.
7. A method of manufacturing a compound semiconductor device, wherein the second compound semiconductor layer is laminated so as to be a compound semiconductor. 3. The outermost surface layer according to claim 1, after forming a strained layer in which a first compound semiconductor layer and a second compound semiconductor layer having a thickness of several nm are alternately laminated on the first compound semiconductor layer. And a second compound semiconductor layer is used as a compound semiconductor device manufacturing method. 4. The method according to claim 1, wherein the first compound semiconductor layer and the second compound semiconductor are GaAs and Ga, respectively.
A method of manufacturing a compound semiconductor device which is Sb. 5. A high-concentration n-type GaAs subcollector layer, a low-concentration n-type GaAs collector layer, a high-concentration p-type GaAs base layer, an n-type AlGaAs emitter layer, and a high-concentration n-type GaAs subemitter layer on a semiconductor substrate. Steps of sequentially laminating, steps of forming an emitter mesa to expose a high-concentration p-type GaAs base layer, steps of forming a sidewall insulating film mask in a self-aligned manner with respect to the emitter mesa, and then, on the external p-type GaAs base layer. The step of selectively forming the GaSb layer after inserting the GaAsSb layer with the Sb composition gradually increased, and the GaSb layer by the selective CVD method of the metal.
A method of manufacturing a compound semiconductor device, comprising the step of selectively depositing a metal film on a layer.