JPH06274449A - Bus fight inhibiting circuit - Google Patents

Abstract

PURPOSE:To prevent a data change by switching the operating direction of a driber/receiver at the timing when data is not sent from the other processor, and transmitting the data from the processor. CONSTITUTION:When a use start signal 13 is not issued from a bus mediation circuit 6 to other processor 5, flip-flops 16, 17a, 18 and 22a, and an OR circuit 19a, AND circuits 20, 21, and a selector 27 output a use request signal 11 and data from a processor 1a, make a driver/receiver enable signal 15a inactive, and thereafter, make a processor enable signal 14 active. In such a way, in the case the driver/receiver enable signal 15a becomes a receiving state, and the bus use start signal 13 to other processor is issued, the processor 1a becomes a transmitting state by making the driver/receiver enable signal 15a active thereafter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus fight inhibiting circuit used for data transmission / reception in an information processing apparatus, and more particularly to data transmission / reception in an information processing apparatus including a processor having bidirectional data input / output terminals. The present invention relates to a bus fight suppression circuit used for.

[0002]

2. Description of the Related Art Conventional data transmission / reception means in an information processing apparatus having a processor having bidirectional data input / output terminals employs means for switching the data transmission / reception direction in response to a transmission request or a reception request.

[0003]

The conventional data transmission / reception switching means in the above-mentioned information processing apparatus is as follows.
There is a high possibility that a bus fight will occur depending on the timing of switching, and this has the drawback that garbled data frequently occurs.

[0004]

According to a first bus fight inhibiting circuit of the present invention, a data input / output terminal of a processor for inputting / outputting data via a bus is bidirectional, and the processor and the bus are connected to each other. A bidirectional driver / receiver is provided as an interface between the drivers / receivers so that the processor is in a receiving state in a normal state.
A bus fight suppression circuit for a processor that sets a receiver and switches to a transmission state only when transmitting data to the bus, and inputs a bus use request signal from the processor and a corresponding bus use permission signal. A bus arbitration unit that outputs a bus use start signal, a processor enable signal that controls the direction of input / output data to the processor, and a driver / receiver enable signal that controls the direction of input / output data to the driver / receiver An enable signal generation circuit, and when the processor transmits data in synchronization with the bus use start signal, monitors a bus use start signal for a bus use request signal from another processor and starts a bus use for the other processor If no signal is issued, the driver / receiver The driver / receiver to the receiving state by inactivating the bus enable signal, and when the bus start signal for the other processor is issued, the driver / receiver enable signal is subsequently activated to activate the processor. This includes setting the transmission state.

A second bus fight suppression circuit of the present invention is
In the first bus fight suppression circuit, a bus use permission signal to another processor is input from the bus arbitration unit and monitored.

A third bus fight suppression circuit of the present invention is
A data input / output terminal of a processor that inputs and outputs data via a bus is bidirectional, and a bidirectional driver / interface is used as an interface between the processor and the bus.
A bus fight suppression circuit for a processor having a receiver, setting the driver / receiver so that the processor is in a transmission state in a normal state, and switching to a reception state only when receiving data from the bus, When the bus use start signal is issued in response to the bus use request signal from the other processor, the driver / receiver enable signal is activated to receive the data from the other processor, and at the same time, the processor enable signal is set to the processor reception state. When the processor transmits data, a bus use start signal for a bus use request signal from another processor is monitored, and when the bus use start signal for the other processor is not issued, a bus use request signal is sent from the processor. Enable to send data and Those comprising a signal generating circuit.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the embodiment of FIG.

In FIG. 1, the processor 1 a is connected to the buses 2 and 3 via a driver / receiver 4. The other processor 5 is also connected to the buses 2 and 3. The bus arbitration circuit 6 is connected to the processor 1a and the other processor 5.

A bus control unit 7, a data transmission unit 8 and a data reception unit 9 are provided in the processor 1a, and a data ready signal 10 indicating a state in which data can be transmitted from the bus control unit 7. Is sent to the data transmission unit 8 and the AND circuit 21, and the AND circuit 21
Sends a use request signal 11 to the bus arbitration circuit 6. The bus arbitration circuit 6 returns the use permission signal 12a to the bus control unit 7 in response to the use request signal 11, and sends the use start signal 13 to the flip-flop 16 and the other processor 5. The output signal of the flip-flop 16 is input to the OR circuit 19a together with the use permission signal 12a, and the output signal of the OR circuit 19a is input to the AND circuit 20 and the flip-flop 22a. The output signal of the AND circuit 20 is input to the flip-flop 17a,
The output signal of the flip-flop 22a is input to the AND circuit 21. The output signal of the flip-flop 17a is
It is a processor enable signal 14 for selecting the transmission / reception direction of the data in the processor 1a.

The output signal of the OR circuit 19a is also input to the selector 27 through the flip-flop 18 and directly, and the output signal of the selector 27 is used for selecting the transmitting / receiving direction of the data in the driver / receiver 4. This is the receiver enable signal 15a.

Flip-flops 16, 17a, 18, 2
2a and OR circuit 19a and AND circuits 20 and 21
Also, the selector 27 causes the processor 1a to output the use request signal 11 and the data and outputs the driver / receiver enable signal 15a when the use start signal 13 is not issued from the bus arbitration circuit 6 to the other processor 5. After activation, processor enable signal 1
Activate 4

In the driver / receiver 4, the data output simultaneously with the use request signal 11 is used as a use permission signal 12a.
Is provided until it is returned, and a register 24 is provided to hold the received data in order to avoid a bus fight with the data from the other processor 5.

When the other processor 5 desires to use the buses 2 and 3, it sends a use request signal 25 to the bus arbitration circuit 6, and the bus arbitration circuit 6 returns a use permission signal 26a. To do.

Next, the operation of the bus fight suppressing circuit configured as described above will be described with reference to FIGS. 1 and 2.

In a normal state, the driver / receiver enable signal 15a is "1" and the processor enable signal 14 is "0". Therefore, the processor 1a is in a state of receiving data from the other processor 5.

When the other processor 5 sends the use request signal 25 (cycles 1 and 2), the bus arbitration circuit 6 uses the use permission signal 26a in the next cycle (cycle 2).
Is returned, and the use start signal 13 is activated during the next one cycle (cycle 3). The other processor 5 sends data (reference numeral 28) in the next cycle (cycle 3) after receiving the use permission signal 26a.

When the driver / receiver 4 receives the data from the other processor 5 via the bus 2, the driver / receiver 4 holds the data in the register 24 and transmits it to the processor 1a in the next cycle (cycle 4) ( Reference number 3
0).

When the processor 1a uses the buses 2 and 3, the data ready signal 10 is activated.
When the use start signal 13 is not issued in this state (cycles 4 and 5), the output signal of the OR circuit 19a becomes "0", so that the driver / receiver enable signal 15a is disabled (cycle 5). The flip-flop 17a operates with clock down, and during one cycle from the clock down of cycle 5 to the clock down of cycle 6, the processor enable signal 14
To activate. Therefore, in cycles 5 and 6, data from other processor 5 is not received.

At the time of clock down in cycle 5, the processor 1a outputs data (reference numeral 2).
9), the data is held in the register 23 of the driver / receiver 4. The processor 1a sends out the use request signal 11 in cycle 6, and when the use permission signal 12a is returned from the bus arbitration circuit 6 (cycle 7), the driver / receiver 4 registers in the register 23 in the next cycle (cycle 8). Then, the data held in is transmitted to the bus 3 (reference numeral 30).

The processor 1a receives the data from the other processor 5 earliest in the cycle 7, and the processor 1a sends the data from the clock down of the cycle 5 to the clock down of the cycle 6. Therefore, the data sent from the processor 1a and the data received from the other processor 5 do not bus fight.

FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is a flow chart showing the operation of the embodiment of FIG.

In this embodiment, in the first embodiment of FIG. 1, the use permission signal 26b sent from the bus arbitration circuit 6 to the other processor 5 is also input to the OR circuit 19b, and the use permission signal 26b is also monitored. It is something that is done. The configuration and operation of the other parts are the same as in the embodiment of FIG.

In the bus fight suppression circuit configured as described above, when the data is transmitted from the processor 1b, the use start signal 13 is not issued in the cycles 4 and 5, and the use permission to the other processor 5 is given in the cycle 5. When the signal 26b is not returned, the output signal of the OR circuit 19b becomes "0", so that the driver /
The receiver enable signal 15a is disabled (cycle 5). The flip-flop 17a operates by clocking up and activates the processor enable signal 14 for one cycle (cycle 6). Therefore, in cycles 5 to 7, data from the other processor 5 is not received.

During this time, the processor 1b outputs data, and the processor 1a outputs data (reference numeral 2).
9), the data is held in the register 23 of the driver / receiver 4. The processor 1a sends out the use request signal 11 in cycle 6, and when the use permission signal 12a is returned from the bus arbitration circuit 6 (cycle 7), the driver / receiver 4 registers in the register 23 in the next cycle (cycle 8). Then, the data held in is transmitted to the bus 3 (reference numeral 30). The processor 1a receives the data from the other processor 5 earliest in the cycle 7, and the processor 1a sends the data.
In cycle 6. Therefore, the data sent from the processor 1a and the data received from the other processor 5 do not bus fight.

FIG. 5 is a block diagram showing the third embodiment of the present invention, and FIG. 6 is a flow chart showing the operation of the embodiment of FIG.

In FIG. 5, the processor 1c is connected to the buses 2 and 3 via the driver / receiver 4. The other processor 5 is also connected to the buses 2 and 3. The bus arbitration circuit 6 is connected to the processor 1c and the other processor 5.

A bus control section 7, a data transmission section 8 and a data reception section 9 are provided in the processor 1c, and a data ready signal 10 indicating a state in which data can be sent from the bus control section 7 is provided. Is sent to the data transmission unit 8 and the AND circuit 21, and the AND circuit 21
Sends a use request signal 11 to the bus arbitration circuit 6. The bus arbitration circuit 6 returns the use permission signal 12c to the bus control unit 7 in response to the use request signal 11, and sends the use start signal 13 to the flip-flops 16 and 17c and the other processor 5. The output signal of the flip-flop 16 is input to the OR circuit 19c together with the use permission signal 12c, and the OR circuit 19c
Is output to the flip-flop 22a. The output signal of the flip-flop 22c is the AND circuit 2
You have entered 1. The output signal of the flip-flop 17c is the processor enable signal 14 for selecting the transmission / reception direction of the data in the processor 1c. The output signal of the flip-flop 17c whose polarity is inverted is the driver / receiver enable signal 15c for selecting the transmission / reception direction of the data in the driver / receiver 4.

The flip-flops 16, 17c, 22c, the OR circuit 19c, and the AND circuit 21 are used by the processor 1c to request the use request signal 11 when the bus arbitration circuit 6 has not issued the use start signal 13 to the other processor 5. Then, the driver / receiver enable signal 15c is made inactive, and then the processor enable signal 14 is made active.

In the driver / receiver 4, the data output at the same time as the use request signal 11 is transferred to the use permission signal 12c.
Is provided until it is returned, and a register 24 is provided to hold the received data in order to avoid a bus fight with the data from the other processor 5.

When the other processor 5 desires to use the buses 2 and 3, it sends a usage request signal 25 to the bus arbitration circuit 6, and the bus arbitration circuit 6 returns a usage permission signal 26c. To do.

Next, the operation of the bus fight suppression circuit configured as described above will be described with reference to FIGS. 5 and 6.

In this embodiment, the driver / receiver enable signal 15c is "0" and the processor enable signal 14 is "1" in a normal state. Therefore, the processor 1c is in a state of transmitting data to the other processor 5.

When the other processor 5 sends out the use request signal 25 (1 and 2 of cycle 32), the bus arbitration circuit 6
Returns the use permission signal 26a in the next cycle (cycle 2). The bus arbitration circuit 6 uses the use permission signal 2
During the next one cycle (cycle 3) after returning 6a, the use start signal 13 is activated. Other processor 5
Sends data (reference numeral 28) in the next cycle (cycle 3) after receiving the use permission signal 26a.

When the processor 1c receives the use start signal 13, the flip-flop 16 becomes "1".
Inactivate the processor enable signal 14,
The driver / receiver enable signal 15c is activated to receive data (cycle 4).

When the processor 1c uses the buses 2 and 3, the data ready signal 10 is activated.
When the use start signal 13 is not issued in this state (cycles 4 and 5), the output signal of the flip-flop 22c whose polarity is inverted becomes "1", so that the processor 1
c transmits the use request signal 11 and data in cycle 6 (reference numeral 29), and when the use permission signal 12c is returned from the bus arbitration circuit 6 (cycle 7), the driver / receiver 4 determines the next cycle ( In cycle 8), the data held in the register 23 is sent to the bus 3 (reference numeral 30).

It is in cycle 6 that the other processor 5 sends the data earliest, and in processor 8, the processor 1c sends the data to the processor 1c. Therefore, the data sent from the processor 1c and the data received from the other processor 5 do not bus fight.

[0038]

As described above, the bus fight suppression circuit of the present invention is configured to transmit the data from the processor by switching the operation direction of the driver / receiver at the timing when the data is not transmitted from the other processor. There is an effect that it is possible to suppress bus fight in an information processing device that includes a processor having bidirectional data input / output terminals, and thus it is possible to prevent data corruption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the embodiment of FIG.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

6 is a flowchart showing the operation of the embodiment of FIG.

[Explanation of symbols]

1a / 1b / 1c Processor 2/3 Bus 4 Driver / Receiver 5 Other Processor 6 Bus Arbitration Circuit 7 Bus Controller 8 Data Transmitter 9 Data Receiver 10 Data Ready Signal 11/25 Use Request Signal 12a / 12c / 26a. 26b Use permission signal 13 Use start signal 14 Processor enable signal 15a ・ 15c Driver / receiver enable signal 16 ・ 17a ・ 17c ・ 18 ・ 22a ・ 22c Flip-flop 19a ・ 19b ・ 19c OR circuit 20 ・ 21 AND circuit 23 ・ 24 Register 27 selector

Claims (3)

[Claims] 1. A data input / output terminal of a processor for inputting / outputting data via a bus is bidirectional, and has a bidirectional driver / receiver as an interface between the processor and the bus. In a bus fight inhibiting circuit for a processor, which sets the driver / receiver so that the processor is in a receiving state, and switches to a transmitting state only when transmitting data to the bus. A bus arbitration unit that inputs a request signal and outputs a corresponding bus use permission signal and a bus use start signal, a processor enable signal that controls the direction of input / output data for the processor, and input / output data for the driver / receiver To generate a driver / receiver enable signal that controls the direction of the And a bus signal generation circuit, and when the processor transmits data in synchronization with the bus use start signal, monitors a bus use start signal for a bus use request signal from another processor, and starts bus use for the other processor. When a signal is not issued, the driver / receiver enable signal is made inactive to put the driver / receiver in a receiving state, and when a bus use start signal for the other processor is issued, the driver / receiver is then received. A bus fight inhibiting circuit comprising putting the processor into a transmitting state by activating an enable signal. 2. The bus fight inhibiting circuit according to claim 1, further comprising inputting and monitoring a bus use permission signal to another processor from the bus arbitration unit. 3. A data input / output terminal of a processor for inputting / outputting data via a bus is bidirectional, and has a bidirectional driver / receiver as an interface between the processor and the bus. Is a bus fight suppression circuit for a processor that sets the driver / receiver so that the processor is in a transmission state and switches to a reception state only when receiving data from the bus, and a bus use request from another processor. When a bus start signal is issued for the signal, the driver / receiver enable signal is activated to receive the data from the other processor, and at the same time, the processor enable signal is set to the processor receiving state, and the processor transmits the data. The bus use request signal from another processor A bus use start signal for a signal, and when the bus use start signal for the other processor is not issued, the processor is provided with an enable signal generation circuit for transmitting a bus use request signal and data. Fight suppression circuit.