JPH06269018A - Carrier chrominance signal stabilizing circuit - Google Patents

Abstract

PURPOSE:To obtain a highly accurate carrier chrominance signal stabilizing circuit with simple configuration by using a phase difference signal so as to apply negative feedback control to a 1st full band pass filter. CONSTITUTION:A carrier chrominance signal stabilizing circuit 10 receives a video signal inputted from a terminal 12 of a 1st full band pass filter 14. After a phase reference signal from an oscillator 20 is phase-shifted at a 1st phase shifter 22 by 90 deg., the signal is given to a 1st phase comparator 18 together with an output signal of the 1st full band pass filter 14. A phase difference signal in response to the phase difference of both the signals from the 1st phase comparator 18 is fed back negatively to the 1st full band pass filter 14 via the 1st low pass filter 24 and a DC cut-off capacitor 26. Thus, a delay time is changed in the 1st full band pass filter 14 in response to the phase difference between the carrier chrominance signal and the phase reference signal. Thus, a jitter component of a color signal is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier color signal stabilizing circuit, and more particularly to a carrier color signal stabilizing circuit for correcting the phase of a carrier color signal based on a phase reference signal in a video tape recorder, a video disc player, a television receiver or the like. The present invention relates to a color signal stabilizing circuit.

[0002]

2. Description of the Related Art In a video tape recorder, a video disc player or the like, hue jitter is generated due to instability of a servo circuit or the like. In order to remove such a jitter component, the phase of the color burst included in the reproduced color signal may be corrected. An example of this type of burst phase correction circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-19096 [H04N 9/83], which was published on January 23, 1990.
Is disclosed in. In this conventional technique shown in FIG. 7, a color signal is input to a terminal 1, and this color signal is supplied to an automatic phase control circuit (APC circuit) 2
Given to. The APC circuit 2 controls the phase of the color signal based on the horizontal synchronizing signal Hsync and the reference frequency signal f _ref from the oscillator 4. The output from the APC circuit 2 is output to the terminal 9 through the phase adjusting circuit 3.

On the other hand, the output signal of the APC circuit 2 is
It is applied to one input of the phase comparator 6 included in the control signal generation circuit 5, and the above-mentioned reference frequency signal f _ref is applied to the other input of this phase comparator 6. Therefore, the phase comparator 6 compares the phases of these two signals and outputs a pulse having a width corresponding to the phase difference between the two signals to the horizontal synchronization signal Hsync.
Low pass filter (LP
F) Output to 8. Therefore, the LPF 8 outputs a control signal having a level corresponding to the phase difference between the two signals, and the control signal is given to the above-mentioned phase adjustment circuit 3.

In the phase adjusting circuit 3, in response to the control signal,
The phase of the color signal output from the APC circuit 2 is further finely adjusted. Therefore, the color signal whose phase is controlled by the APC circuit 2 and whose phase is finely adjusted by the phase adjusting circuit 3 is output to the terminal 9. Therefore, even if the reproduced color signal includes a jitter component, the jitter component is removed.

[0005]

Since the conventional technique described here is a feedforward system, it is possible to use, for example, an LP.
It is necessary to provide a level adjusting circuit (not shown) between the F8 and the phase adjusting circuit 3 and generate a control signal that matches the control signal level-phase characteristic of the phase adjusting circuit 3 based on the output from the LPF 8. . This kind of level adjusting circuit is complicated and expensive.

Therefore, a main object of the present invention is to provide a carrier color signal stabilizing circuit having a simple structure.

[0007]

Briefly, the present invention provides an input signal that has passed through an all-pass filter to a first input of a phase detector, and supplies the input signal to a second input of a phase detector with respect to the input signal. Supply a reference signal having a phase difference of approximately 90 degrees,
Characterized in that the phase difference signals of the first and second inputs are output from the phase detector, and the phase difference signal is supplied to the all-pass filter via the low-pass filter to perform negative feedback control.
It is a carrier color signal stabilizing circuit.

[0008]

For example, a video signal reproduced by a video tape recorder, a video disc player or the like or a video signal demodulated by a television receiver is delayed by an all pass filter and then supplied to a first input of a phase comparator. It A reference signal having a phase difference of approximately 90 degrees with respect to the input signal is supplied to the second input of the phase comparator.
On the other hand, the second phase comparator creates a burst gate pulse having substantially the same width as the input video signal, and the first phase comparator compares the phases of the input video signal and the reference carrier during the period of the burst gate pulse. Create a phase difference signal.
With this phase difference signal, the all-pass filter is subjected to negative feedback control to correct the phase of the video signal.

[0009]

According to the present invention, since the level adjusting circuit does not have to be used, the structure is simplified. With that,
Since the all-pass filter is subjected to negative feedback control by the phase difference signal, it does not become unstable due to temperature drift or the like. Further, since the control timing of the first phase comparator is set to a period substantially the same as the burst period, S /
Even if a video signal with a poor N is input, the phase can be controlled accurately.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments below with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the carrier color signal stabilizing circuit 10 of this embodiment shown in FIG. 1, a color signal input to an input terminal 12 is delayed by a first all-pass filter 14 constituting a variable delay means for a required time. It The output from the first all-pass filter 14 is supplied to one input of the first phase comparator 18. On the other hand, the reference carrier signal from the fixed oscillator 20 has its phase shifted by 90 degrees by the first phase shifter 22, and is then supplied to the other input of the first phase comparator 18. Then, the first phase comparator 18 compares the phases of the signals supplied to these two inputs. This first phase comparator 1
The output from 8 is supplied to the first all-pass filter 14 via the first low-pass filter 24 and the DC cut capacitor 26. The input color signal is sin (A + t),
Assuming that the reference signal from the oscillator 20 is sinA, the first phase comparator 18 multiplies the two signals as described later, and sin (A + t−A) = sin (t) and s as the detection output.
Output in (A + t + A) = sin (2A + t). Among them, the signal actually required for controlling the all-pass filter 14 is the former, that is, the signal including the jitter component (t).
Only sin (t). Therefore, the latter signal, that is, sin (2A + t) becomes an unnecessary signal. And
The first low pass filter 24 is used to remove this unnecessary signal. In this way, the AC control signal having an amplitude according to the magnitude of the jitter component is fed back to the first all-pass filter 14, and the delay time of the first all-pass filter 14 is controlled according to the magnitude of the jitter component. It

It is necessary to set the phase difference between the two inputs of the first phase comparator 18 to a constant value (90 degrees in this embodiment) beforehand. Therefore, in this embodiment, P
A fixed oscillator 20 having no LL function and the first phase shifter 22 generate a reference signal. At this time, the capacitor 26 is
This is useful for reducing the amount of phase shift of the first phase shifter 22 or the first APF 14.

On the other hand, the color signal passed through the first all-pass filter 14 is also supplied to one input of the second phase comparator 30. Further, the reference signal from the first phase shifter 22 is further phase-shifted by 90 degrees by the second phase shifter 28. Therefore, the signal obtained by inverting the reference carrier wave signal from the fixed oscillator 20 is supplied to the other input of the second phase comparator 30. The second phase comparator 30 is supplied from the input terminal 32 and is activated during the high level period of the burst timing signal shown in FIG. 2B, and the second phase comparator 30 shows it as shown in FIG. During the period of the burst signal BURST, the demodulation output showing the maximum value is obtained. This demodulated output is given to the second low pass filter 34 having the same function as the first low pass filter 24 described above. Therefore, after the unnecessary signal component is removed by the second low pass filter 34, the demodulated output of the second phase comparator 30 is compared with the reference voltage 38 by the level comparator 36. And the level comparator 3
In 6, the burst gate pulse BGP, which is at the high level during the burst period as shown in FIG. 2C, is created, and this burst gate pulse BGP is supplied to the first phase comparator 18. Therefore, the first phase comparator 18 is activated while the burst gate pulse BGP is at the high level.

In this way, the burst signal BURST included in the input color signal is demodulated by using the second phase comparator 30, the burst gate pulse BGP is created, and the first phase comparator is generated by the burst gate pulse BGP. Since 18 is activated, the timing at which the first phase comparator 18 is activated becomes almost the same as the burst signal period of the input color signal. That is, the timing at which the first phase comparator 18 is activated is changed following the phase change of the burst signal period of the input color signal. Therefore, even if a color signal with a poor S / N is input, the burst signal phase can be reliably detected, and accurate control can be performed.

The color signal whose burst phase has been corrected by the carrier color signal stabilizing circuit 10 thus configured is output from the output terminal 16. The luminance signal is input from the input terminal 13, passes through the second all-pass filter 15, and is output to the output terminal 17. Here, the second all-pass filter 15 is the first all-pass filter 1 described above.
4 has the same circuit configuration and has the first all-pass filter 14
Similarly, the time constant, that is, the delay time is controlled by the AC control signal from the capacitor 26. Therefore,
The second all-pass filter 15 is the first all-pass filter 14.
Therefore, the chrominance signal and the luminance signal are synchronously sent to the subsequent circuit.

The first all-pass filter 14 will now be described in more detail with reference to FIG. However, as described above, the second all-pass filter 15 is also similarly configured. The input end 40 of the first all-pass filter 14 is connected to the input terminal 12, and the output end 42 is connected to the first phase comparator 18 and the second phase comparator 18.
It is connected to each one input and output terminal 16 of the phase comparator 30. A differential amplifier 44 is provided between the input end 40 and the output end 42, and the (+) of the differential amplifier 44 is provided.
The input color signal is supplied to the input through the resistor R _A.
A parallel circuit of variable inductor 46 and capacitor 48 is connected between the (+) input and ground between resistor R _A and the (+) input. That is, the resistor R _A , the variable inductor 46, and the capacitor 48 constitute a bandpass filter, and the (+) input of the differential amplifier 44 is supplied with the input color signal that has passed through the bandpass filter. The (−) input of the differential amplifier 44 has resistors R _B and R _C (R _B =
R _C ) feeds back half of the output of the differential amplifier 44. Therefore, it will be readily understood that the circuit shown in FIG. 3 constitutes an all-pass filter as a whole.

Further, the variable inductor 46 used in the all-pass filter 14 shown in FIG. 3 will be described in detail with reference to FIG. The variable inductor 4 shown in FIG.
6 is convenient for incorporation in an integrated circuit, but it goes without saying that a variable inductor having another configuration may be used if it is not necessary to incorporate it in the integrated circuit.

Referring to FIG. 4, the variable inductor 46 of this embodiment includes differential amplifier circuits 50 and 52, and a DC bias is applied from the input end 54 to the base of the transistor Q1 of the differential amplifier circuit 50. The transistor Q1 and the transistor Q2 form a differential pair 56, and the base of the transistor Q2 is connected to the output terminal 58. A capacitor C is inserted between the DC power supply Vcc to which the collector of the transistor Q2 and the collector of the transistor Q1 are connected. The output of the differential pair 56, that is, the collector of the transistor Q2 is the transistor Q3 of the differential amplifier circuit 52.
Connected to the base of. A constant fixed bias V _B4 is supplied from the DC power supply 62 to the base of the transistor Q4 which constitutes the differential pair 60 together with the transistor Q3, and is made an AC ground. And the transistor Q
The collectors of 3 and Q4 are connected to input 54 and output 58, respectively. Incidentally, 64, 66 and 68 are constant current sources (direct current sources). Similarly, transistor Q
Transistors Q5, Q6, Q7 and Q8 interposed between the emitters of 1, Q2, Q3 and Q4 and ground
Also constitute a constant current source (current mirror circuit), and the current value changes with the control voltage given from the input terminal 64. Further, the capacitor C may be inserted between the collector of the transistor Q2 and the DC power supply 62.

In the variable inductor 46 of FIG. 4, the differential resistance of each of the transistors Q1 and Q2 is re _0.
Then, the collector potential Vc of the transistor Q2 is given by Equation 1 when the angular frequency is ω.

[0020]

[Equation 1]

When the differential resistances of the transistors Q3 and Q4 are re ₁ , i ₁ = Vc / 2re
_Since it is ₁ , the current i ₁ is expressed by the equation 2 and the equation 3 is obtained.

[0022]

[Equation 2]

[0023]

[Equation 3]

Here, when L = C · 2re ₀ · 2re ₁ , the _equation 4 is obtained.

[0025]

[Equation 4]

Therefore, the input end 54 and the output end 58 are included.
Inductance characteristics are obtained during the period. Therefore, when the variable inductor 46 is used in the all-pass filter 14 of FIG. 3, the input end 54 is connected to the (+) side of the differential amplifier 44.
It suffices to connect to the input and ground the input end 58. Also,
The control signal from capacitor 26 (FIG. 1) is input 64
Should be given to. In this case, the current of the transistors Q5 to Q8, that is, the inductance value of the variable inductor 46 changes according to the AC control signal from the capacitor 26, and thereby the time constant of the first all-pass filter 14 or the delay time changes.

Next, another embodiment of the present invention will be described with reference to FIG. The embodiment of FIG. 5 differs from the embodiment of FIG. 1 in that the first phase comparator 18 is controlled only by the output from the level comparator 36 in the embodiment of FIG. In the embodiment, the control signal of the first phase comparator 18 differs depending on whether it is synchronous or asynchronous. That is, during synchronization, the first phase comparator 18 is activated by the signal from the second phase comparator 30 described above, that is, the burst gate pulse BGP from the level comparator 36, and when asynchronous, as shown in FIG. The first phase comparator 18 is activated by a burst timing signal which is a wide pulse. With such a configuration, it is possible to accurately perform the phase control even in the weak electric field. When synchronizing,
Since the same operation as that of the embodiment of FIG. 1 is performed, the description thereof is omitted.

In the embodiment shown in FIG. 5, in the asynchronous state, the input color signal is delayed by the first all-pass filter 14 and then supplied to one input of the first phase comparator 18. On the other hand, the reference carrier signal from the fixed oscillator 20 has its phase shifted by 90 degrees by the first phase shifter 22, and is then supplied to the other input of the first phase comparator 18. Then, the first phase comparator 18 compares the phases of the signals supplied to these two inputs.

Here, when a jitter component is present in the input color signal, a phase difference signal is output from the first phase comparator 18, and the phase difference signal is output from the first low pass filter 24 and the DC cut capacitor 26. Is supplied as a control signal for the first all-pass filter 14 via. That is, the first all-pass filter 14 is subjected to negative feedback control according to the magnitude of the jitter component, and the delay time of the first all-pass filter 14 is controlled.

On the other hand, the color signal passed through the first all-pass filter 14 is also supplied to one input of the second phase comparator 30. Further, the reference carrier wave signal from the first phase shifter 22 is further phase-shifted by 90 degrees by the second phase shifter 28, and finally becomes a signal inverted with respect to the original reference carrier wave. The other input of 30 is supplied. Therefore, at the time of non-synchronization, the second phase comparator 30 cannot obtain the maximum demodulation output during the period of the burst signal BURST (FIG. 2), so that the synchronization signal missing from the second phase comparator 30 is compared in level. It is input to the device 36 and compared with the reference voltage 38. For this reason, the burst gate pulse BGP as shown in FIG. 2C is not continuously given to the first phase comparator 18 from the level comparator 36 at the time of asynchronous. On the other hand, the discontinuous burst gate pulse BGP from the level comparator 36 is smoothed by the third low pass filter 98 having a relatively large time constant, whereby a low level signal is created, and this signal is fed to the inverter. Via the AND gate 100 to one input. Therefore, the AND gate 100 allows the above-mentioned burst gate pulse BGP when asynchronous.
A pulse wider than that (the pulse shown in FIG. 2B), that is, the burst timing signal is as it is, the first phase comparator 1
8 and the first phase comparator 18 is activated at this timing.

In the embodiment shown in FIG. 5, the first phase comparator 18
Although the activation timing of is switched between synchronous and asynchronous, the operation of the first phase comparator 18 may be stopped during asynchronous.

In the embodiment shown in FIG. 6, the invention is PAL.
A line counter 102 and a switch 104 are provided to apply the method. The line counter 102 counts the horizontal synchronizing signal Hsync and gives a switch signal to the switch 104 for each line. That is, on the odd line (or even line), the switch 104 has the contact 104.
In the even line (or the odd line), the switch 104 is switched to the contact 104b. Therefore, in the odd line (or even line), the oscillator 2
The reference signal from 0 is phase-shifted by 90 degrees by the first phase shifter 22, but in the even line (or the odd line), the reference signal is supplied to the first phase comparator 18 without being phase-shifted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing a burst gate pulse.

FIG. 3 is a circuit diagram showing an example of an all-pass filter used in the embodiment of FIG.

FIG. 4 is a circuit diagram showing an example of a variable inductance used in the embodiment of FIG.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a main part when the present invention is applied to a PAL system color signal processing circuit.

FIG. 7 is a block diagram showing an example of a conventional carrier color signal stabilizing circuit.

[Explanation of symbols]

 10 ... Carrier color signal stabilizing circuit 14 ... First all-pass filter 15 ... Second all-pass filter 18 ... First phase comparator 20 ... Fixed oscillator 22 ... First phase shifter 24 ... First low-pass filter 26 ... DC cut capacitor 28 ... Second phase shifter 30 ... Second phase comparator 32 ... Input terminal 34 ... Second low-pass filter 36 ... Level comparator 46 ... Variable inductor

Claims (2)

[Claims] 1. A reference signal having an input signal that has passed through an all-pass filter supplied to a first input of a phase detector and a reference signal having a phase difference of about 90 degrees with respect to the input signal supplied to a second input of the phase detector. To output the phase difference signals of the first and second inputs from the phase detector, and to supply the phase difference signal to the all-pass filter via a low-pass filter for negative feedback control. Characteristic carrier color signal stabilization circuit. 2. A carrier color signal stabilizing circuit, wherein a demodulated output of a burst gate pulse is used as a control signal for the phase detector.