JPH06268453A - Amplifier - Google Patents

Abstract

PURPOSE:To prevent the amplification factor of an amplifier from being influenced even when the characteristics of MOS transistors depend on a gate which width and a gate length. CONSTITUTION:The size of the MOS transistors M11, M12,...M1n and the MOS transistors M21, M22,...M2n is set at the fixed gate width and gate length and parallel connection bodies and serial connection bodies for the numbers of integer multiplies based on the MOS transistors are constituted. For instance, by constituting a source ground circuit of (m) parallel connection bodies on a source side and (n) serial connection bodies on a load side, amplification whose amplification factor is (m.n)<2/1> is obtained.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is applied to electronic equipment.
The present invention relates to an amplifier composed of OS transistors.

[0002]

2. Description of the Related Art In recent years, amplifiers composed of MOS transistors have been mounted on integrated circuits and have come to be used in electronic devices.

A conventional amplifier will be described below. FIG. 5 is an example of a conventional grounded source amplifier and its circuit diagram. VIN is an input terminal, VOUT is an output terminal, V
DD is a power supply voltage application terminal. Also, M1 and M2 are M
It is an OS transistor. Further, FIG. 6 is an example of an amplifier using a conventional differential amplifier and is a circuit diagram thereof. VIN
1, VIN2 are input terminals, and VOUT1 and VOUT2 are output terminals. Further, M3 to M6 are MOS transistors.

Regarding the amplifier configured as described above,
The operation will be described below with reference to the saturation region of the MOS transistor which is actually used.

In the case of source grounding, first, the input terminal VIN
The voltage input to is converted into a current by the MOS transistor 1. That is, I ₁ = K ₁ (V _IN −V _TH ) ² , where I ₁ is the current flowing through the MOS transistor 1, K ₁ is the proportional coefficient of the MOS transistor, and V _TH is M.
It is the threshold voltage of the OS transistor. Further, the MOS transistor M2 restores the current to the voltage and amplifies it. That is, I ₂ = K ₂ (V _DD −V _OUT −V _TH ) ² and I ₁ = I ₂ K ₁ (V _IN −V _TH ) ² = K ₂ (V _DD −V _OUT −V _TH ) ² . Therefore, the amplification factor is dV _OUT / dV _IN = − (K ₁ / K ₂ ) ^1/2 . Here, since the constants K ₁ and K ₂ are determined by the gate length and the gate width of the MOS transistor, the MO
If the gate width of the S transistor is W ₁ and W ₂ , and the gate length is L ₁ and L ₂ , then dV _OUT / dV _IN =-{(W ₁ · L ₂ ) / (W ₂ · L ₁ )} ^1/2 Becomes

In the example of the differential amplifier, first, the input terminal VIN
1, the difference between the input voltage to VIN2 is the MOS transistor M
3 and M4 respectively convert into electric current. That is, the _{I 3 = K S (V IN1} -V S -V TH) 2 I 4 = K S (V IN2 -V S -V TH) 2. Here, I ₃ and I ₄ are MOS transistors M3 and
Currents flowing through M4, K _S is the proportional coefficient of the MOS transistors M3 and M4, V _S is the source voltage of the MOS transistors 3 and M4, and V _TH is the MOS transistor M.
3 and M4 threshold voltage. Furthermore, MOS
The transistors M5 and M6 respectively return the current to voltage and amplify it. That is, I ₅ = K _D (V _DD −V _OUT1 −V _TH ) ² I ₆ = K _D (V _DD −V _OUT2 −V _TH ) ² . Here, I ₅ and I ₆ are currents flowing through the MOS transistors M5 and M6, K _D is a proportional coefficient of the MOS transistors M5 and M6, and V _OUT1 and V _OUT2 are source voltages of the MOS transistors M5 and M6.

I₃= I_Five I_Four= I₆ Than K_S(V_IN1-V_S-V_TH)²= K_D(V_DD-V_OUT1-V_TH)² K_S(V_IN2-V_S-V_TH)²= K_D(V_DD-V_OUT2-V_TH)² Next, K_S ^1/2(V_IN1-V_S-V_TH) = K_D ^1/2(V_DD-V_OUT1-V_TH) K_S ^1/2(V_IN2-V_S-V_TH) = K_D ^1/2(V_DD-V_OUT2-V_TH) Is the source voltage of the MOS transistors M5 and M6.
Pressure V_OUT1, V_OUT2Difference is V_OUT2-V_OUT1= (K_S/ K_D)^1/2(V_IN1-V_IN2), And the amplification factor is d (V_OUT2-V_OUT1) / D (V_IN1-V_IN2) = (K_S/ K_D)^1/2 Becomes Where K_S, K_DIs the gate of the MOS transistor
It is determined by the gate length and gate width.
The gate width of the transistor is W_S, W_D, The gate length is L _S, L_D
Then, d (V_OUT2-V_OUT1) / D (V_IN1-V_IN2) = {(W_S・ L_D) / (W_D・ L_S)}^1/2 Becomes

[0008]

However, in the above-mentioned conventional structure, the amplification factor of the amplifier is not high because the characteristics of the MOS transistor depend on the gate width and the gate length.

That is, since there is a correction due to the processing accuracy of the mask and diffusion of the MOS transistor, the actual gate width,
The gate length is different from the design size. For example, gate length 1.
A correction amount of about 1/10 occurs in the diffusion process of about 0 μm.

In a source-grounded circuit, for example, in order to realize a quadruple amplification factor, the MOS transistor M is designed in a design dimension
The gate width of 1 and M2 may be 4: 1, and the gate length may be 1: 4. When the gate width is 10 μm and the gate length is 1.0 μm, WD ₁ = 40 (μm) and LD ₁ = 1.0.
(Μm), WD ₂ = 10 (μm), LD ₂ = 4.0 (μ
m). However, in the processing dimension, W ₁ = 40.
1 (μm), L ₁ = 0.9 (μm), W ₂ = 10.1 (μ
m) and L ₂ = 3.9 (μm), the gate width widens and the gate length narrows. The amplification factor at that time is dV _OUT / dV _IN =-((W ₁ · L ₂ ) / (W ₂ · L ₁ )) ^1/2 = -4.14, which is about 3.5% from the quadruple. .

Next, in order to realize an amplification factor of, for example, 4 times in the differential amplifier, WD _S = 40 (μm) and LD _S = 1.0 ( μ
m), WD _D = 10 (μm), and LD _D = 4.0 (μm). At the processing dimension at that time, W _S = 40.1 (μ
m), L _S = 0.9 (μm), W _D = 10.1 (μm), L
_The gate width widens and the gate length narrows as _D = 3.9 (μm). The amplification factor at that time is d (V _OUT2 −V _OUT1 ) / d (V _IN1 −V _IN2 ) = {(W _S · L _D ) / (W _D · L _S )} ^1/2 = 4.14 After all, it is shifted by 3.5% from 4 times.

Further, the same degree of deviation occurs in the absolute variation of the processing dimension. For example, the gate length is 0.9μ
The absolute variation of the finish with respect to m is about ± 0.1 μm. Amplification factor is 4.
It shifts about 5%.

Further, the characteristics of the MOS transistor change due to the short channel effect and the narrow channel effect.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide an amplifier with a high amplification factor.

[0015]

In order to achieve this object, the amplifier of the present invention sets the size of the MOS transistor to a constant gate width and gate length, and an integer multiple number of parallels based on the MOS transistor. It is composed of a connected body or a series connected body.

[0016]

With this structure, even if the characteristics of the MOS transistor depend on the gate width and the gate length, the amplification factor of the amplifier is not affected.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a source-grounded amplifier according to an embodiment of the present invention. In FIG. 1, M1
1, M12, ..., M1m are m MOs connected in parallel
The S transistors, M21, M22, ..., M2n are n MOS transistors connected in series.

FIG. 2 is a circuit diagram of a differential amplifier according to an embodiment of the present invention. In FIG. 2, M31, M32, ...
,, M3m, M41, M42, ..., M4m are respectively m parallel-connected MOS transistors, M51, M
52, ..., M5n, M61, M62, ..., M6n are n MOS transistors connected in series.

In this embodiment, a source-grounded circuit will be described. In design size, the gate width is 10μ
m and the gate length is set to 1.0 μm as a reference. That is, WD _ST = 10 (μm), LD
_ST = 1.0 (μm). At that time, in the processing dimensions,
The gate width widens and the gate length narrows as W _ST = 10.1 (μm) and L _ST = 0.9 (μm). In the embodiment of the present invention,
As shown in FIG. 1, m reference MOS transistors were connected in parallel to ground the source, and n reference MOS transistors were connected in series to form a load. The amplification factor is dV _OUT / dV _IN =-{(W ₁ · L ₂ ) / (W ₂ · L ₁ )} ^1/2 , but in parallel connection, the gate width is multiplied by the number, and in series connection Since the gate length is multiplied by that number, dV _OUT / dV _IN =-{(m · W _ST · n · L _ST ) / (W _ST · L _ST )} ^1/2 = − (m · n) It becomes ^1/2 . For example, to realize a quadruple amplification factor, n =
If 4 and m = 4, then dV _OUT / dV _IN = − (4 · 4) ^1/2 = −4, and it is possible to realize exactly 4 times.

In the differential amplifier, the gate width is 10 μm and the gate length is 1.0 in the design size, similarly to the source grounding.
It is based on the MOS transistor set to μm. In the embodiment of the present invention, as shown in FIG. 2, m reference MOS transistors are connected in parallel to form a differential amplifier.
A load was formed by connecting n OS transistors in series.
The amplification factor is d (V _OUT2 −V _OUT1 ) / d (V _IN1 −V _IN2 ) = {(W _S · L _D ) / (W _D · L _S )} ^1/2 = {(m · W _ST -N-L _ST ) / (W _ST -L _ST )} ^1/2 = (m-n) ^1/2 For example, to realize a 4-fold amplification factor, n = 4, m = 4
Then, d (V _OUT2 −V _OUT1 ) / d (V _IN1 −V _IN2 ) = (4 · 4) ^1/2 = 4, and it is possible to realize exactly 4 times.

As described above, according to this embodiment, the MOS
By setting the size of the transistor to a constant gate width and gate length, and configuring it with an integer multiple number of parallel connection bodies or series connection bodies based on the MOS transistor,
Even if the characteristics of the MOS transistor depend on the gate width and the gate length, the amplification factor of the amplifier is not affected.

Although the case where the N-channel MOS transistor is used has been described in the present embodiment, the P-channel MOS transistor can be similarly configured and the same effect can be obtained.

Although the gates are connected to each other in series in this embodiment, the gates may be connected in common as shown in FIGS. 3 and 4.

In this embodiment, the source side is a parallel connection body and the load side is a series connection body, but the source side is a series connection body and the load side is a parallel connection body. The same can be applied as an attenuator.

[0026]

According to the present invention, the size of the MOS transistor is set to a constant gate width and gate length, and the MOS transistor is constituted by an integer multiple of parallel connection bodies or series connection bodies. It is possible to realize an amplifier having an excellent characteristic that the amplification factor of the amplifier is not affected even if the characteristics of (3) depend on the gate width and the gate length.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an amplifier according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an amplifier according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of an amplifier according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional amplifier.

FIG. 6 is a circuit diagram of a conventional amplifier.

[Explanation of symbols]

 VIN, VIN1, VIN2 input terminals VOUT, VOUT1, VOUT2 output terminals VDD power supply voltage application terminals M1 to M6 MOS transistors M11, M12, M21, M22 MOS transistors

Claims (2)

[Claims] 1. An amplifier characterized in that a grounded source circuit is constituted by a parallel connection body or a series connection body using a plurality of MOS transistors of the same polarity having a reference gate width and a reference gate length. 2. An amplifier characterized in that a differential amplifier is constituted by a parallel connection body or a series connection body by using a plurality of MOS transistors of the same polarity having a reference gate width and a reference gate length.