JPH06267977A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve an electric characteristic of a MISFET by reducing resistance of a diffusion layer directly under a contact hole and a contact resistance between this diffusion layer and a conductive layer. CONSTITUTION:Prior to a process of forming a contact hole by opening an insulating film 3 between the gates 2, 2 of a pair of a MISFET formed on a semiconductor substrate 1, ion implantation is performed on the semiconductor substrate 1 in the contact hole forming region from the direction to be slanting being seen from a section of a semiconductor substrate 1 along the extending direction of the gate electrode 2 and to be vertical being seen from the section of the semiconductor substrate 1 along the direction orthogonal to the extending direction of the gate electrode 2. Next, after the contact hole is formed, a conductive layer is formed on the upper part of the MISFET in order to electrically connect the conductive layer to a diffusion layer 4 directly under the contact hole through the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a MISFET.

[0002]

2. Description of the Related Art In a manufacturing process of a MISFET, a gate electrode of a first MISFET formed on a semiconductor substrate and a second MIS formed adjacent to this MISFET.
After forming an insulating film between the gate electrode of the FET and a contact hole, a conductive layer made of polycrystalline silicon doped with impurities is formed on the upper part of these MISFETs to remove impurities in the polycrystalline silicon. By thermally diffusing into the semiconductor substrate through the contact holes,
A method of forming a low-resistance diffusion layer directly under the contact hole is known.

An example of the above process will be described with reference to FIGS. In these figures, (a) is a plan view of the semiconductor substrate, and (b) is a sectional view of the semiconductor substrate taken along the line BB of (a).

In FIG. 8, a gate electrode 21 made of polycrystalline silicon is formed on a semiconductor substrate 20. Immediately below the gate electrode 21, a thin silicon oxide insulating film 22 forming a gate insulating film of the MISFET is formed.
Are formed.

A diffusion layer (semiconductor region) 23 forming a source and a drain of a MISFET is formed on the semiconductor substrate 20 between the gate electrode 21 and the gate electrode 21 adjacent thereto. In addition, sidewall spacers 24 made of silicon oxide are provided on the sidewalls of the gate electrodes 21.
Are formed. In FIG. 8A, the side wall spacers 24 are omitted (see FIGS. 9A to 1C).
The same applies to 1 (a)).

Next, as shown in FIG.
A contact hole forming region (two gate electrodes 2
A photoresist 25 having an opening (between 1 and 21) is formed, and the insulating film 22 is etched by using this as a mask to form a contact hole 26 on the surface of the diffusion layer 23.

Next, after removing the photoresist 25,
As shown in FIG. 10, a conductive layer 27 is formed on the MISFET.
To form. The conductive layer 27 is made of polycrystalline silicon doped with impurities and constitutes, for example, a gate electrode or a wiring of the MISFET formed above the MISFET.

The conductive layer 27, as shown in FIG.
It may be used as a conductive layer for a pad. In this case, a second conductive layer (not shown) forming the gate electrode or wiring of the MISFET is formed on the conductive layer 27.

Next, the semiconductor substrate 20 is annealed to diffuse the impurities in the conductive layer 27 into the semiconductor substrate 20 through the contact hole 26, thereby lowering the resistance of the diffusion layer 23 immediately below the contact hole 26, and The contact resistance between the conductive layer 27 and the diffusion layer 23 is also reduced.

[0010]

In order to reduce the resistance of the diffusion layer immediately below the contact hole and the contact resistance between the diffusion layer and the conductive layer, the above-mentioned conventional technique is made of polycrystalline silicon which constitutes the conductive layer. It was necessary to increase the impurity concentration inside.

However, if the impurity concentration in the polycrystalline silicon is increased, the amount of side etching at the time of processing the conductive layer becomes large, and the shape controllability of the conductive layer is impaired.

Further, since the lateral spread of the diffusion layer becomes large and the diffusion layer extends to the bottom of the gate electrode, the gate breakdown voltage is lowered and the leak current is increased.
There is a problem that the electrical characteristics of T deteriorate.

An object of the present invention is to reduce the resistance of the diffusion layer immediately below the contact hole and the contact between the diffusion layer and the conductive layer without deteriorating the shape controllability of the conductive layer or deteriorating the electrical characteristics of the MISFET. It is to provide a technique capable of reducing resistance.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, the insulating film between the gate electrode of the first MISFET formed on the semiconductor substrate and the gate electrode of the second MISFET formed adjacent thereto is opened to form a contact hole. Prior to the step of forming, it is oblique when seen from the cross section of the semiconductor substrate along the extending direction of the gate electrode, and seen from the cross section of the semiconductor substrate along the direction orthogonal to the extending direction of the gate electrode. Ions are implanted into the semiconductor substrate in the contact hole formation region from the direction vertical to the vertical direction, and then a contact hole is formed, and then a conductive layer is formed on the first and second MISFETs. A method of manufacturing a semiconductor integrated circuit device, comprising a step of electrically connecting the conductive layer and a diffusion layer immediately below the contact hole.

[0017]

According to the above means, the impurity is ion-implanted into the semiconductor substrate to which the conductive layer is connected prior to the step of forming the conductive layer on the MISFET, so that the impurity concentration in the conductive layer is reduced. Therefore, the shape controllability of the conductive layer is improved.

According to the above means, when viewed from the cross section of the semiconductor substrate along the extending direction of the gate electrode, it is oblique and viewed from the cross section of the semiconductor substrate along the direction orthogonal to the extending direction of the gate electrode. By implanting ions into the diffusion layer from a vertical direction, it is possible to suppress the diffusion layer from spreading in the direction of the gate electrode. Therefore, the lateral breakdown of the diffusion layer may lower the gate breakdown voltage and increase the leakage current. Can be suppressed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. In each of FIGS. 1, 2 and 7, (a) is a plan view of the semiconductor substrate, (b) is a sectional view of the semiconductor substrate taken along the line BB of (a), and (c) is (a). 9 is a cross-sectional view of the semiconductor substrate taken along the line CC of FIG.

The present embodiment is applied to a memory cell of an SRAM in which a transfer MISFET is formed on a driving MISFET. In FIG. 1, a semiconductor substrate 1 made of p-type silicon single crystal is The gate electrode 2 of the driving MISFET is formed.

The gate electrode 2 is made of polycrystalline silicon doped with an n-type impurity (for example, phosphorus). Also,
Immediately below the gate electrode 2, a thin silicon oxide insulating film 3 forming a gate insulating film of the driving MISFET is formed.

The gate electrode 2 and another gate electrode 2 adjacent to the gate electrode 2 extend in the vertical direction of FIG. 1 (a). Hereinafter, the extending direction of the gate electrode 2 will be referred to as the Y direction, and the direction orthogonal to this will be referred to as the X direction.

On the semiconductor substrate 1 between the two gate electrodes 2 and 2, an n-type diffusion layer (semiconductor region) 4 constituting the source or drain of the driving MISFET is formed. That is, the driving MISFET is composed of an n-channel type MISFET.

A sidewall spacer 5 made of silicon oxide is formed on the sidewall of each gate electrode 2. The sidewall spacers 5 are not shown in FIG. 1 (a) (the same applies to FIG. 2 (a) and FIG. 7 (a)).

Next, as shown in FIG. 2, a contact hole forming region (two gate electrodes 2,
A photoresist 6 having a hole (between 2) is formed.

Next, as shown in FIGS. 3 and 4, the diffusion layer 4 is ion-implanted with an n-type impurity (for example, phosphorus) using the photoresist 6 and the insulating film 3 as a mask. At this time, it is perpendicular to the main surface of the semiconductor substrate 1 when viewed from the cross section of the semiconductor substrate 1 along the X direction (FIG. 3), and viewed from the cross section of the semiconductor substrate 1 along the Y direction (FIG. 4). Ion implantation is performed from an oblique direction.

Next, as shown in FIGS. 5 and 6, the insulating film 3 is etched using the photoresist 6 as a mask to contact the contact hole 7 on the surface of the diffusion layer 4.
To form. The ion implantation may be performed using the photoresist 6 as a mask after forming the contact hole 7.

Next, after removing the photoresist 6, as shown in FIG. 7, a conductive layer 8 is formed on the driving MISFET.
To form. The conductive layer 8 is an n-type impurity (for example, phosphorus).
Made of polycrystalline silicon doped with a
It constitutes the gate electrode of the transfer MISFET formed on the ET.

The conductive layer 8 may be used as a conductive layer for pads. In this case, a second conductive layer (not shown) forming the gate electrode of the transfer MISFET is formed on the conductive layer 8.

Next, the semiconductor substrate 1 is annealed to diffuse the impurities in the conductive layer 8 into the diffusion layer 4 through the contact holes 7 and to diffuse the impurities ion-implanted into the diffusion layer 4 in the previous step. As a result, the diffusion layer 4 having a high impurity concentration, that is, a low resistance is formed immediately below the contact hole 7.
a is formed (FIGS. 7 (b) and 7 (c)).

As described above, according to the present embodiment, the resistance of the diffusion layer 4 immediately below the contact hole 7 is reduced to reduce the resistance of the diffusion layer 4 and the contact resistance between the diffusion layer 4 and the conductive layer 8. can do.

Further, according to this embodiment, since the impurity is ion-implanted into the diffusion layer 4 prior to the step of forming the conductive layer 8, it is possible to reduce the impurity concentration in the conductive layer 8. The shape controllability of the conductive layer 8 is improved.

Further, according to this embodiment, the ions are perpendicular to the cross section of the semiconductor substrate 1 along the X direction and oblique from the cross section of the semiconductor substrate 1 along the Y direction. By performing the implantation, it is possible to suppress the diffusion layer 4 from spreading below the gate electrode 2, and thus it is possible to suppress the decrease in the gate breakdown voltage and the increase in the leak current.
The electrical characteristics of the ISFET are improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0035]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the resistance of the diffusion layer and the contact resistance between the diffusion layer and the conductive layer can be reduced without deteriorating the shape controllability of the conductive layer.

Further, according to the present invention, it is possible to suppress a decrease in gate breakdown voltage and an increase in leak current without deteriorating the shape controllability of the conductive layer.

[Brief description of drawings]

1A and 1B show a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, in which FIG. 1A is a plan view of a semiconductor substrate, and FIG.
Sectional drawing of the semiconductor substrate in BB line of (a), (c) is
It is sectional drawing of the semiconductor substrate in CC line of (a).

2A and 2B show a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, in which FIG. 2A is a plan view of a semiconductor substrate, and FIG.
Sectional drawing of the semiconductor substrate in BB line of (a), (c) is
It is sectional drawing of the semiconductor substrate in CC line of (a).

FIG. 3 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

7A and 7B show a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, where FIG. 7A is a plan view of a semiconductor substrate and FIG.
Sectional drawing of the semiconductor substrate in BB line of (a), (c) is
It is sectional drawing of the semiconductor substrate in CC line of (a).

FIG. 8 shows a conventional method for manufacturing a semiconductor integrated circuit device,
(a) is a plan view of the semiconductor substrate, and (b) is a sectional view of the semiconductor substrate taken along the line BB of (a).

FIG. 9 shows a conventional method for manufacturing a semiconductor integrated circuit device,
(a) is a plan view of the semiconductor substrate, and (b) is a sectional view of the semiconductor substrate taken along the line BB of (a).

10A and 10B show a conventional method for manufacturing a semiconductor integrated circuit device, wherein FIG. 10A is a plan view of a semiconductor substrate, and FIG. 10B is a sectional view of the semiconductor substrate taken along the line BB of FIG.

11A and 11B show a conventional method for manufacturing a semiconductor integrated circuit device, wherein FIG. 11A is a plan view of a semiconductor substrate, and FIG. 11B is a sectional view of the semiconductor substrate taken along the line BB of FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 gate electrode 3 insulating film 4 diffusion layer (semiconductor region) 4a diffusion layer 5 sidewall spacer 6 photoresist 7 contact hole 8 conductive layer 20 semiconductor substrate 21 gate electrode 22 insulating film 23 diffusion layer (semiconductor region) 24 side Wall spacer 25 Photoresist 26 Contact hole 27 Conductive layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H01L 21/28 A 7376-4M 27/11 7210-4M H01L 27/10 381 (72) Inventor Matsuda Nozomi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd. (72) Inventor Shoji Yoshida 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Ultra LSI Engineering Co., Ltd. (72) Inventor Chiemi Mori 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd. (72) Inventor Toyokawa Shigeya 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Taiji Iwanaga Higashi 5-20-1 Kamimizuhonmachi, Kodaira-shi, Kyoto Within Hitsuritsu Super S.I.Engineering Co., Ltd. (72) Inventor Yuki Kunimoto 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Super L・ SII Engineering Co., Ltd.

Claims (3)

[Claims] 1. A first MISF formed on a semiconductor substrate.
After forming an insulating film between the gate electrode of ET and the gate electrode of the second MISFET formed adjacent to the first MISFET to form a contact hole, the first and second MISFETs are formed. Forming a conductive layer on top of
A method of manufacturing a semiconductor integrated circuit device, comprising the step of electrically connecting the conductive layer and a diffusion layer immediately below the contact hole through the contact hole, the method including the step of forming a contact hole in the insulating film. Alternatively, after forming a contact hole in the insulating film, the contact hole is oblique when viewed from the cross section of the semiconductor substrate along the extending direction of the gate electrode, and is formed along the direction orthogonal to the extending direction of the gate electrode. A method of manufacturing a semiconductor integrated circuit device, characterized in that impurities of the same conductivity type as that of the diffusion layer are ion-implanted into the diffusion layer from a direction perpendicular to the cross section of the semiconductor substrate. 2. The first and second MISFETs are
Driving MISF that constitutes a part of SRAM memory cell
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductive layer is ET, and the conductive layer is a gate electrode of a transfer MISFET formed on the driving MISFET. 3. The conductive layer is formed of the first and second M
2. The semiconductor integrated circuit device according to claim 1, which is a pad conductive layer interposed between the gate electrode or wiring of the MISFET formed above the ISFET and the diffusion layer immediately below the contact hole. Production method.