JPH06265845A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain the small-sized, inexpensive liquid crystal display device which can receive a multicolored video signal with a small number of pins by providing a video signal input circuit which can receive one pixel by dividing it for plural times with time by optional video signal terminal allocation corresponding to the number of bits of the video signal. CONSTITUTION:The video signal input circuit 1 consists of a video RAM 10 which can store data on one pixel divisionally by plural times, a distributing circuit 11 which separates the video signal into the primary colors, and video RAMs 12-14 which store respective color data. A gradation control circuit 2 consists of gradation circuits 15-17 for respective colors which are connected to the video RAMs 12-14 respectively. A data array circuit 3 consists of S/P converting circuits 18-20 for the respective colors which are connected to the respective gradation circuits 15-17 and a data array circuit 21. The video RAM 10 inputs the data on one pixel divisionally plural times according to the frequency indication of a control circuit 5 and stores the data. Thus, the video signal is inputted plural times to handle the full-color video signal with a small number of data input terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gray scale liquid crystal display device of a simple matrix display device.

[0002]

2. Description of the Related Art Conventionally, a display control unit of a liquid crystal display device, as shown in FIG. 2, has a gradation control circuit 2, a data array circuit 3, a clock generation circuit 4, a control circuit 5 and interfaces 7, 8 for each function. It consists of 9 and 22.

The gradation control circuit 2 has an interface 22.
Are connected to the red gradation circuit 15 and the green gradation circuit 1
6 and a gray scale circuit 17 for blue. Data array circuit 3
Is a red serial-parallel conversion circuit 18 (hereinafter referred to as S / P conversion circuit 18) connected to the red gradation circuit 15, the green gradation circuit 16, and the blue gradation circuit 17, respectively, and a green serial circuit. Parallel conversion circuit 19 (hereinafter referred to as S / P conversion circuit 19), blue serial / parallel conversion circuit 2
0 (hereinafter referred to as S / P conversion circuit 20) and a data array circuit 21.

[0004]

However, in the conventional configuration, in order to support a video signal in which one pixel is composed of a plurality of bits of data, for example, 24 bits, 24 data signals, which is the number equal to the number of bits of the video signal, are used. Since an input terminal is required, there is a problem that a display control unit having a large number of input pins must be configured.

When one pixel is composed of a 3-bit video signal, 21 data signal input terminals are not used and there is a problem that they are wasted. Further, the data input terminals R0 to R
Since each of G, G0 to G3, and B0 to B3 is fixedly set to which gradation of red, green, and blue, the signal connection can be changed after the circuit board is designed. Therefore, there is a problem that the connectable video signal is restricted.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention makes one pixel a plurality of times by arbitrarily assigning data signal terminals according to the number of bits of a video signal (assignment of color and gradation). By providing a video signal input circuit capable of time-divisionally receiving a video signal, for example, eight data signal input terminals can cope with a 1-bit to 24-bit video signal.

[0007]

In the display control unit constructed as described above, a video signal of 1 bit to 24 bits can be dealt with only by providing eight data signal input terminals, so that the number of terminals of the package of the display control unit is suppressed. Therefore, an inexpensive liquid crystal display device can be constructed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a display control circuit of the present invention. The block configuration diagram of the display control circuit of the present invention comprises a video signal input circuit 1, a gradation control circuit 2, a data array circuit 3, a clock generation circuit 4, a control circuit 5 and interfaces 6 to 9 for each function. The video signal input circuit 1 includes a video RAM 10 capable of storing data of one pixel a plurality of times, a distribution circuit 11 for separating a video signal into three primary colors, a red video RAM 12 for storing data of each color, and a green video RAM 13. , A blue video RAM 14. The gradation control circuit 2 includes a red gradation circuit 15, a green gradation circuit 16, and a blue gradation circuit 17, which are connected to the red video RAM 12, the green video RAM 13, and the blue video RAM 14, respectively. The data array circuit 3 is connected to the red gradation circuit 15, the green gradation circuit 16, and the blue gradation circuit 17, and the red S /
P conversion circuit 18, green S / P conversion circuit 19, blue S
It comprises a / P conversion circuit 20 and a data array circuit 21.

[0009]

[Table 1] Next, the circuit operation will be described. The video signal and data signal input terminals DI0 to DI11 are assigned as shown in Table 1. When the number of bits of the video signal is 8 bits or less, for example ,,,,, can read data once. On the other hand, for example ,,, is an example in which data reading of a video signal of one pixel is performed twice or more times. The interface 6 stores the input video signal in the video RAM 10. Video R
In the case of ,,,, in Table 1, in the case of AM, the acquisition is performed once according to the instruction of the control circuit 5, but in the case of, of Table 1, it is acquired twice or three times according to the instruction of the control circuit 5. The data of one pixel is stored.

The distribution circuit 11 causes the video signals stored in the video RAM 10 to correspond to the data signal input terminal allocation shown in Table 1 according to the instruction of the control circuit 5, and the video RAMs 12 and 1
Store in each bit of 3 and 14. The data signal input terminal allocation in Table 1 is an example, and any allocation such as red only is possible. The crosses are invalid data and are ignored. The video signals stored in the video RAMs 12, 13, 14 are
Modulation for gradation is applied in each gradation circuit 15, 16 and 17. The respective outputs of the gradation circuits 15, 16 and 17 are converted from serial data to parallel data by the respective S / P conversion circuits 18, 19 and 20. As the parallel data, serial data is collected for 24 pixels, for example, and becomes one-time data.

The parallel data outputs of the S / P conversion circuits 18, 19 and 20 are rearranged by the video data array circuit 21 in the order corresponding to the color arrangement of the display device, and then, for example, in units of 8 bits of the interface 9. It is output from the data signal output terminals DO0 to DO7. The interface 7 inputs the vertical synchronizing signal VS, the horizontal synchronizing signal HS, and the dot clock DOTCLK, and transmits them to the clock generating circuit 4. The clock generation circuit 4 receives the input vertical synchronizing signal VS, horizontal synchronizing signal HS, and dot clock DOTC.
Frame signal FLM, alternating signal M, dot clock CL2, and latch clock C required by the display device from LK
The system clock CLK for L1 and the display controller is generated.

The control circuit 5 controls the display control unit according to the control instruction read from the interface 8 connected to the ROM or the like. FIG. 3 is a block diagram of a video interface using the present invention. The analog video signals R, G, and B are fixed in black level potential by the clamp circuit 23, converted into digital signals by the A / D conversion circuit 24, and input to the display control circuit 25. Display control circuit 25
Is a ROM having control setting data of the display control circuit 25
It is connected to 26.

[0013]

As described above, according to the present invention, the video signal can be captured a plurality of times.
Since it is possible to support full-color video signals with a small number of data input terminals, it is possible to manufacture a compact and inexpensive liquid crystal display device with a small number of pins. Further, for example, after setting the display control unit to 320 * 240, one screen 640 * 2
When connected to 40 256 color signals, the display controller
By considering two pixels as one pixel, a liquid crystal display device capable of displaying 30,000 colors or more is obtained. That is, there is an effect that multicolor display is possible even when connected to a conventional CRT control device having a small number of colors.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a block configuration of a display control device of the present invention.

FIG. 2 is an explanatory diagram showing a block configuration of a conventional display control device.

FIG. 3 is an explanatory diagram showing a block configuration of an interface using the display control device of the present invention. It is explanatory drawing which showed the data signal input terminal allocation of this invention.

[Explanation of symbols]

 1 video signal input circuit 2 gradation control circuit 3 data array circuit 4 clock generation circuit 5 control circuit 6-9, 22 interface 10, 12-14 video RAM 15-17 gradation circuit 18-20 S / P conversion circuit 21 video Data array circuit DI0 to DI11 data signal input terminals DO0 to DO8 data signal output terminals

Claims (3)

[Claims] 1. A display control circuit of a multi-color or high gradation simple matrix type display device, wherein an interface circuit receives a video signal in which one pixel is composed of a plurality of bits data from a plurality of input signal terminals, and a video signal storage video R.
A distribution circuit for distributing a video signal from the AM, color and gradation to a designated color data storage video RAM and an input circuit composed of three color data storage video RAM designated for each color are provided. A liquid crystal display device characterized by the above. 2. The video signal storage video RAM has a circuit configuration in which, when a video signal of one pixel is input a plurality of times, the video RAM is stored in different memory areas, respectively. The described liquid crystal display device. 3. The distribution circuit is a video R for storing a video signal.
2. The liquid crystal according to claim 1, wherein the liquid crystal has a circuit configuration capable of distributing a plurality of bits of video data stored in the AM to a memory corresponding to each gradation of a color data storing video RAM of each color in accordance with an instruction from a control circuit. Display device.