JPH06262818A - Image processing device - Google Patents

Abstract

PURPOSE:To easily perform layout printing and to efficiently perform recording processing in an image processing system separated into a device storing a plurality of images and a device practically recording an image. CONSTITUTION:The image read by a copier 101 or the image edited or formed by a host computer 103 is stored in an image memory unit 102 to be subjected to memory control. When a command is issued on the side of the host computer so as to record the desired image in the image memory unit 102, the image data indicated on the basis of the command content is transmitted to the copier 101. At this time, by merely transmitting a recording paper feed command to the copier 101 in the image absent area between images, wasteful image recording processing is skipped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing system, and more particularly to an image processing system for taking out a plurality of stored images and recording each of the taken out images on one recording medium.

[0002]

2. Description of the Related Art In recent years, digital color copying machines have come into widespread use in which an original is digitally color-separated and read, and color recording is performed based on the read digital color image signal. As shown in FIG. 20, this type of copying machine 1801 further includes a dedicated memory device 1802 and a host computer 1.
803 can be connected, the read image is stored in the dedicated memory device 1802, and the image editing process can be performed using the host computer 1803.

[0003]

However, in the above-mentioned conventional example, when a plurality of images stored in the memory device are layout-printed on an ink jet color printer, the printer can be controlled because there are a plurality of position information. It is difficult and the program in the memory device is complicated.

[0004]

[Means for Solving the Problems] and

The present invention has been made in view of the above problems, and enables easy layout printing in an image processing system in which a device for storing a plurality of images and a device for actually recording images are separated. The present invention is intended to provide an image processing system that enables efficient recording processing.

In order to solve this problem, the image processing system of the present invention has the following configuration. That is, an image processing system including a first device that stores a plurality of images and a second device that records as a visible image on a predetermined recording medium, the plurality of images being stored in the first device. When recording an image with the second image, the individual images to be printed stored in the first device are merged, transferred to the second device as one image, and the image recorded Between the image and the image, a predetermined command is generated and the second device simply conveys the recording medium.

[0006]

Embodiments of the image processing apparatus of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing an image processing system according to a first embodiment of the present invention.

As shown in FIG. 1, this system includes a digital color copying machine 101, a host computer 103,
The external operation device 109 is connected by a cable extending from the image memory unit 102. 107-1 is a cable connecting the image memory unit 102 and the digital color copying machine 101, and 107-2 is the image memory unit 102 and the host computer 103.
Reference numeral 107-3 denotes a cable connecting the image memory unit 102 and the external operation device 109, respectively.

Here, the above configuration will be specifically described. In the figure, 101 is a digital color copying machine (hereinafter referred to as "copying machine") equipped with a color scanner and an inkjet printer. The copying machine 101 can obtain a color copy image independently by placing a document under the pressure plate 105 and pressing the copy start key 104. Further, the image read by the color scanner of the copying machine 101 can be simultaneously sent as digital data to the image memory unit 102 via the cable 107. The sent image data is sent to the host computer 103 via a general-purpose I / F 107-2 such as GP-IB.
Sent to, enabling various image editing processes. The processed image data is sent to the scanner printer 101 via the image memory unit 102, and the edited image can be reproduced. Further, by connecting the external operation device 109, it is possible to operate the copying machine 101 from the outside with more functions.

FIG. 2 is a diagram in which an image in the image memory unit is layout-outputted by a copying machine. In the figure, 20
Reference numeral 1 is a sheet, 202 and 203 are output images, 204 is a print head scan area in which the positional information of the layout output images 202 and 203 are merged, and 205 is a print head.

FIG. 3 is an enlarged view of the print head in the vicinity of the front end and the rear end of the image in FIG. 2 and shows an electric adjusting means in the y direction. Reference numeral 301 is an image, and 302 is a print head. In the figure, (a) is the image top, and (b) is the image rear end.

Further, a circle mark means that an image is printed, and
Means that no image is printed, and each represents one pixel.

FIG. 4 shows the electrical adjustment means in the x direction,
401 is a sheet, 402 and 403 are layout output images,
Reference numeral 404 is a print head scan area, and 405 is a signal VEN that becomes High only in the image area in the x direction.

From the above description, the print head 205 in FIG. 2 can obtain the layout output images 202 and 203 by scanning the print head scan area 204.

FIG. 5 is a schematic block diagram showing the internal structure of the copying machine 101 according to the first embodiment, and FIG. 6 is a diagram for explaining the scanning of the line sensor according to the first embodiment.

In FIG. 5, 201 is a CCD line sensor (hereinafter referred to as "line sensor"), and 203 is an enlarged view thereof. As shown in FIG. 5, R, G, B,
R, G, B, ... and sensors of each color are arranged side by side.
One pixel is detected with B as one set. Reference numeral 202 is an A / D converter, 204 is a shading correction circuit, and 205 and 215.
Is a black character processing circuit, 206 is a scaling circuit, 207 is a switch unit, 208 is a data X decoding circuit, 209 is a LOG conversion circuit, 210 is a masking circuit, 211 is an edge processing circuit, 212 is a head shading circuit, 2
13 is a γ table, 214 is a binarization circuit, and 216 is a print head.

The line sensor 201, as shown in FIG.
CCD main scanning in the horizontal direction with respect to the original and CCD in the vertical direction
Sub-scanning is sequentially performed to scan the entire document with BVE and V
According to a synchronization signal such as E, the first scan, the second scan ... The line sensor 201 is driven by, for example, a pulse motor or the like, and can scan an arbitrary area under the control of a CPU (not shown). The difference in the scanning method when the data read here is sent to the printer and when it is sent to the image memory unit 102 will be described.

FIG. 7 is a diagram for explaining the details of the scanning of the line sensor according to the first embodiment.

FIG. 1A is an explanatory diagram for explaining a scanner method for printing with a printer. In the first scan, the CCD reading width is the total pixel width of the CCD,
132 pixels of pixels 1 to 132 are read. However, 128 pixels of pixels 2 to 129 are printed as the printer print width, and other pixels are discarded. This is because the copying machine adopts a binarization method such as an error diffusion method that binarizes the peripheral data of the print data when printing the data. In the second scan, the area for four pixels (129 to 132 pixels) scanned in the first scan is read again, and 2
It is used as a connection process for digitization and as print data. Thus, when printing on a printer, several pixels are overlaid on each pixel.

FIG. 7B shows the image memory unit 10.
FIG. 6 is an explanatory diagram illustrating a scanning method when sending read data to No. 2; As shown in the same drawing, the overlapping portion between the first scanning and the second scanning is eliminated, and the CCD reading width is 132 pixels in full. This is the image memory unit 1
This is because only the data is transferred to 02 and the binarization processing is not performed. As a result, the number of scans can be reduced when reading the same area as when printing, which is effective for speeding up.

As described above, in the first embodiment, the scan mode is changed when printing and when transferring to the image memory unit 102.

The image signal read by the line sensor 201 is converted into a digital signal by the A / D converter 202 and processed as a digital signal hereinafter.

FIG. 8 is a timing chart at the time of reading an original according to the first embodiment.

At the timing of reading the above-mentioned document, BVE in FIG. 8A indicates the start point of the CCD main scanning with respect to the document, and VE determines the timing of CCD scanning. The CCD reads an image for each VE while moving in the main scanning direction. When one VE is enlarged as shown in FIG. 8B, each pixel has a video clock VC.
The data is transferred in a dot-sequential manner with R, G, and B as one pixel in synchronization with LK.

The image signal is then input to the shading correction circuit 204, and white correction / black correction is performed according to the characteristics of the CCD. The signal output from the shading correction circuit 204 is input to the black character processing circuit 205.
Here, black characters in the original are detected, processing is performed to eliminate color bleeding during printing, and sharpen black characters. The data input to the black character processing circuit 205 is added with the data X for determining the processing for each pixel after the detection of the black character. This is shown in FIG. 8 (C).

FIG. 9 is a diagram showing the bit contents of the data X according to the first embodiment. Regarding black character processing, the presence or absence of the processing is added to bit 0. Further, as shown in the figure, other image processing is also added.

The image data to which the data X is added is scaled (enlarged or reduced) to a desired size by the scaling circuit 206, and the image memory unit 1 is switched by the switch unit 207.
02 via the cable 107-1. In addition, the switch unit 207 selects the magnification change circuit 206 when the image memory unit 102 is not connected.
It is also possible to directly transfer the image data from the decoding circuit 208. As a result, the copying machine 101 can be independently operated as a color copying machine. The image memory unit 102 has a capacity capable of storing image data for 3 bands.

The image signal output from the image memory unit 102 via the magnification changing circuit 206 or the cable 107-1 is input to the data X decoding circuit 208 via the switch unit 207. The data X decoding circuit 208 decodes the content of the added data X and outputs the control signal whose content is shown in FIG. 9 to each processing block. Each processing block performs processing based on the control signal.

The image data is subjected to density conversion in the LOG conversion circuit 209 and masking circuit 210 and masking calculation processing in accordance with ink characteristics, and then the image is sharpened in the edge processing circuit 211, and the head is processed. It is input to the shading circuit 212. Here, the print head 2
Since the ink discharge amount, direction, and the like are not constant among the pixels due to 16 variations, these corrections are performed by signal processing. The γ table 213 is a conversion cable that determines the density of printing and can be adjusted to a desired density.
In the binarization circuit 214, the control signals MIXDATA, NE
Based on GA and PHOTO, multivalued image data is converted into binary image data. The black character processing circuit 215 performs black character processing under the control based on the control signal KB, and the inkjet print head 216 performs printing. The operation timing of the print head 216 also follows the synchronization signals of BVE, VE, etc., like the line sensor 203 described above.

FIG. 10 is a block diagram showing a schematic structure of the image memory unit 102 of the first embodiment. From the figure, the flow of image data in the image memory unit 102 can be roughly grasped. In the figure, 601 is an input masking circuit, 602 is a smoothing circuit,
3 is a synthesis circuit, 604 is a γ table, 605 and 606 are FIFOs, 607 is an image memory, 608 is an address counter, 609 is a crystal oscillator circuit (hereinafter referred to as “OSC circuit”), 610 is a γ table, 611 is an expansion circuit, 612
Is a CPU, 613 is a region signal generation circuit, 614 is a video / CPU interface, and 615 is an I / O.

The image data transferred from the copying machine 101 is input via the cable 107-1 to the input masking circuit 6
01 is input. The image data sent is CCD
Since the characteristics of the color separation filter of No. 3 remain the same, the calculation is performed here because the characteristics are adapted to the characteristics of a general standard, for example, the NTSC standard. By the above calculation, the host computer 103
It is possible to standardize the handling of color data in and to standardize the color reproduction during printing. At this time, the data X is not calculated and is passed through.

The image data after the input masking is input to the smoothing circuit 602 and the synthesizing circuit 603. The combining circuit 603 will be described later. Smoothing circuit 6
In 02, smoothing processing is performed to prevent image deterioration due to moire. At this time, the matrix used for smoothing can be selected in three stages of 2 × 1, 2 × 2, 3 × 3, and although not shown, it can be selected by a data set from the CPU 612. Also at this time, no calculation is performed on the data X.

The γ table circuit 604 modulates the scanner input image into an image having desired gradation characteristics. This is also configured so that a free table can be set from the CPU as in the above. Both of the smoothing circuit 602 and the γ table circuit 604 can be freely selected by the user via the CPU 612 by a command from the host computer 103.

The image data corrected by the γ table circuit 604 is sent to the image memory 60 via the FIFO 605.
7 is stored in the address designated by the address generation circuit 608 which generates the address. Image memory 60
7 and the address counter 608 do not control by the image synchronization clock VCLK from the copying machine 101, but the OSC circuit 60 in the image memory unit 102.
Control is performed by the clock IVCLK obtained from the control circuit 9, for example, timing control of memory refresh is performed.
In order to perform this clock conversion, FIFOs 605 and 606 are provided for input and output of image data. Therefore, even if the copying machine 101 has an abnormality and the clock VCLK is stopped, it is possible to recover without losing the contents of the memory.

FIG. 11 shows an image memory 6 according to the first embodiment.
It is a figure explaining 07 in detail. In the figure, the memory address is a linear address in the BVE direction when viewed from the CPU 612. Since the format of the image data used in the scanner and printer of the copying machine 101 is different, in the input / output mode to the copying machine 101 (hereinafter referred to as video mode), the address calculation becomes more complicated. On the other hand, when data is transferred from the host to the image memory under the control of the CPU 612 via the I / O 615 (hereinafter, referred to as CPU mode), the image file format of the host is often line-sequential line by line in the horizontal direction. Is easy and effective.

(Data Writing from Scanner to Image Memory) FIG. 12 is a timing chart of the image data input from the scanner and the address output from the address generating circuit 608 in the first embodiment, and FIG. FIG. 6 is a diagram illustrating an image memory when data X is not supported according to the first embodiment.

Image data is sequentially written in the FIFO 605 in synchronization with the clock CLK by the timing control of BVE and VE. After a while, the address counter 608 outputs the FIFORE, and the FIFO
Image data is sequentially read from 605 in synchronization with the clock IVCLK. At the same time, the address counter 608 also sequentially counts up or performs calculation, and the data is written in the address designated by the address (FIG. 12).

Here, when the application software of the host computer 103 does not support the data X, it can be dealt with only by changing the address calculation means. In other words, if the addresses shown in FIG. 12 (FIG. 12) are sequentially output, the storage area for the data X is filled and other data is stored in the image memory 607, so that it can be dealt with. After the second line of VE, R is again applied to the address (3, n + 3, ...) At which the data X is stored.
As shown in FIG. 13, data X is written to write data.
Will eventually disappear (not be stored) from the memory 607. As a result, when the host computer does not support the data X, the image memory 60
You can use 7 effectively. In this embodiment, when the data X is not supported, data for 4 bands can be stored.

FIG. 14 is a circuit diagram showing a configuration of an address generation circuit 608 for generating an address of the image memory in the first embodiment, and FIG. 15 is a timing chart in the circuit shown in FIG.

In FIG. 14, 901, 907 and 91
0, 913, 915, 916 are registers, 902, 91
8, 919 are selectors, 903, 911 are counters, 9
Reference numerals 04, 905 and 908 are flip-flops, and 906 and 9
Reference numerals 09 and 912 denote comparators, and reference numerals 917 and 914 denote addition circuits.

As shown in FIG. 15, when the copying machine 101 is started to read an image, the BVE
Signal SET controlled by CPU 612 while is Low
Accordingly, the selector 919 selects the read start address set in the register 901 in advance.
During this period, when the HS signal created by the OSC circuit 609 based on the VE signal becomes Low. The start address is selected by the selector 902, and the clock IVCLK
Accordingly, the start address is loaded into the counter 903 (time t1). At this time, the flip-flop 904
Also the start address is set. BVE is High
At the same time as h, the image request signal REQ also becomes Low (time t2).

Generation of the line enable signal LE for defining the data read period of one line will be described. H
The output of the counter 905 reset by the S signal is compared with the line enable start value which is input to the comparator 906 and set in the register 907 in advance, and when the values match, a matching pulse is output to the flip-flop 908 ( Time t3). Similarly, when the comparator 909 matches the line enable end value set in the register 910, it outputs a match pulse to the flip-flop 908. Flip flop 9
Reference numeral 08 denotes a JK flip-flop, which is the period of these two coincidence pulses, that is, the register 907 and the register 9
The line enable signal LE can be output for a period determined by the value set to 10. This line enable signal LE
Becomes the read enable of the counters 911 and 903 and the FIFO 605, and the sequentially generated data is stored at the designated address.

The counter 911 for counting the clock IVCLK and the set value of the register 913 are compared by the comparator 9
12 compares the clock IVCLK to 4
Every second, the comparator 912 generates the load signal LD. The generated load signal LD becomes the load signal of the counter 903, and the value obtained by adding the output address of the counter 903 and the value set in the register 915 in the adder circuit 914 is added to the counter 903 via the selector 902. To load. Taking the example of FIG. 11, the value set in the register 915 becomes “m” (see FIG. 12).
(See the address of FIG. 12), and in the case of FIG. 13, it is “n” (see the address of FIG. 12).

When the count advances and the next HS is input, the value set in the flip-flop 904 and the value set in the register 916 are added together by the adder circuit 9.
It is added at 17, passed through the selectors 918, 919, and 902, and loaded into the counter 903 as the head address of the next line. The value set in the register 916 is changed depending on whether or not the data X is supported, as described above. In the case of FIG. 11, it is “4” (see the address of FIG. 12), and in the case of FIG. 12, it is “3” (see the address of FIG. 12).
Becomes As described above, the address output from the counter 903 is given to the image memory 607 via the selector 1201, and the read image is stored in the memory 607. Note that the selector 1201
Details of will be described later.

(Reading Data from Image Memory to Host) The image data stored in the image memory 607 is CP
It is sent to the I / O 615 by DMA transfer under the control of U612 and transferred to the host computer 103 via the cable 107-2. The means will be described below.

FIG. 16 is a block diagram of a control circuit for accessing the image memory 607 from the DMA and the CPU in the first embodiment. In the figure, 1201,1
Reference numeral 202 is a selector, 1203, 1205 and 1209 are addition circuits, 1204 and 1208 are registers, 1206 is a start address, 1207 is a flip-flop, and 121.
0 indicates a rate multiplier, respectively.

The image memory 607 transfers image data to and from the copying machine 101 (hereinafter, referred to as Video mode) and transfers data to and from the CPU 612 or the host computer 103 (hereinafter, CPU.
This is different from the DMA mode) in that the address generation means is different. This is because in the video mode, the transfer rate is high and the same access means as in the CPU mode cannot be taken.

The selector 1201 is a selector for switching between the Video mode and the CPU / DMA mode, and can be selected by the CPU 612 according to the desired mode. The selector 1202 can select a mode in which the CPU 612 can directly access (hereinafter, referred to as CPU mode) and a mode in which DMA transfer is performed (hereinafter, referred to as DMA mode). For example, when the CPU mode is selected, the CPU 61
An address obtained by adding the address output from 2 and the value set in the register 1204 in the adder circuit 1203 is output. This is because, in this embodiment, when the data X is supported, the image data is stored for only three bands, but the image memory is still large in capacity and therefore deviates from the space accessible by the CPU. Therefore, the accessible memory space is expanded by adding data.

In the DMA mode, the register 1206 for setting the DMA start address and the read signal IO.
The data obtained by adding the outputs of the flip-flop 1207 using the RD or the write signal IWOR as a clock is output as an address. The flip-flop 1207 is
The output of the adder circuit 1209 is latched for each pulse of the signal IORD / IOWR, and the output is returned to the adder circuit 1209 which adds the set value of the register 1208. Thus, for example, when the setting of the register 1208 is “3”, a multiple of 3 is obtained, and when the setting of the register 1208 is “4”, a multiple of 4 is obtained as the output of the flip-flop 1207. The resulting output address is the signal IORD / IOWR at the start address.
It is an address obtained by adding a certain integer multiple for each pulse of. This is because, as shown in FIG. 8, the image data is stored as dot-sequential in the linear address direction, so for example, in the case of line-sequential transfer in which only R data is desired, the start address “0” is a multiple of 4 This is because it is necessary to generate an address to which is added. Also, the flip-flop 1207 is reset when the start address is set.

Also, the IOWR pulse is input to the rate multiplier 1201 and the IOWR pulse itself is thinned out by this output, whereby the host computer 10
Reduction transfer is also possible at the time of image data transfer from No. 3. This is possible because the address is not updated by thinning out the IOWR pulse.

By the means described above, the image data stored in the memory 607 at every scanning end as shown in FIG.
It is being transferred to the host computer 103. The above description is for the case of transferring data from the scanner to the host computer 103.

(Data Writing from Host Computer to Image Memory) Next, the operation from the host to the printer will be described by returning to FIG. The image data edited by the host computer 103 is sequentially transferred to the I / O 615 via the cable 107-2. The transferred image data is
In the image memory unit 102, it is stored in the image memory 607 by DMA transfer. At this time, as described above, the addresses are sequentially generated from the start address set in the start register 1206 of FIG. 16 by the signal IORD. For example, in the case of line sequential, the register 1208 is used to generate an address for each "3" or "4".
Set the value of. Here, if the host computer 103 supports the data X, the set value is set to "4" so that the data is stored as shown in FIG. 8, and if the data X is not supported, the set value is set to "3". ", The data X is not stored as shown in FIG.

(Reading Data from Image Memory to Printer) When the data transfer from the host is completed, the counter 903 is selected by the selector 1201 shown in FIG.
Place the address bus in Video mode. The image reading in the video mode is similar to the writing, from the start address set in the register 901 of FIG.
Addresses are sequentially calculated by timing control of E, VE, and IVCLK, and reading is performed according to these addresses.

FIG. 17 shows a read timing chart when the host computer does not support the data X as shown in FIG. The LE signal becomes Low (time t11).
At the same time, the counters 903 and 911 in FIG. 14 start counting and generate an address. At this time, as shown in the timing chart, the extra data R is always read. At the same time, the 2-bit counter 920 is also operated and 2
A bit signal γSEL is generated. The signal γSEL is
By inputting to the γ table 610 of FIG. 10, the function as the γ table can be made for each color. When γSEL is 0, it is the R table, when 1 is G, when it is 2, it is B.
When γSEL is 3, the data X generation table is selected, and if the host computer 13 supports the data X, data through is set, and if it is not supported, it is constant for any input data. The data is set to be output as data X. Therefore, FIG.
As shown in FIG. 7, extra reading is always performed and this is converted into data X.

When the data transfer for the first scan is completed, the addresses are calculated as described above, and the addresses are sequentially read and printing is performed. When the printing for the first scan is completed, the data transfer for the second scan is performed next, and by repeating the above,
Get a printout of the i-image.

At this time, a connecting process as shown in FIG. 18 is also necessary, which will be described below.

FIG. 18 is an explanatory diagram showing the relationship between the print pixels and the image stored in the memory in the first embodiment.

When the data transfer of the first transfer image is completed from the host computer 103 to the image memory 607 of the image memory unit 102, 132 pixels are read from the image memory 607 in the VE direction. Of these, the print head 216 prints 128 pixels from pixel 2 to pixel 129. As described with reference to FIG. 7A, the other pixels are processed as the connecting process and are not printed.

The read start address of the data read from the image memory 607 at the time of the second scan of the print head 216 corresponds to the pixel 129 at the time of the first scan.
From the host computer 103 to the image memory 607
For data transfer black, the data transfer start address of the second transfer image is set to 132 pixels after the pixel 133, and the data is transferred to the empty area of the memory where printing is completed. As described above, by sequentially performing the transfer processing from the host computer 103 to the image memory 607, the memory can be used efficiently and effectively,
The number of transfers can also be reduced.

The γ table 610 shown in FIG. 10 is added to the image data read from the image memory 607 as described above.
After being enlarged to a desired size through the enlargement circuit 611,
It is input to the FIFO 606. Here, the clock is converted and input to the synthesis circuit 612. At this time,
At the same time, when data is read from the scanner of the copying machine 101, a memory image and a scanner image output can be obtained by the synthesizing circuit 603. This combining timing is performed based on the SELECT signal generated by the area signal generating circuit 613, and combining can be performed at a desired position.

Although the flow of the image signal has been mainly described above, the flow of the control signal will be described below.

FIG. 21 is a block diagram of the control system of the digital color copying machine 101 in the embodiment.

In the figure, reference numeral 2101 is a CPU that controls the entire copying machine, and 2102 is a ROM that stores an operation processing procedure of the CPU 2101 (a program according to a flowchart of FIG. 22 described later) and a RAM used as a work area. Is a memory unit composed of 21
03 to 2105 are drivers for driving the motor,
The drive target is a paper feed motor 2106 for conveying a recording paper or a document to be read, a scanner motor for performing a scanning movement of a carriage on which a scanner is mounted, and a head for performing a scanning movement of a carriage on which a recording head is mounted. There is a motor 2108 and the like. Reference numeral 2109 denotes various processing units, which include the various processing circuits shown in FIG.

Reference numeral 2110 denotes a bidirectional interface for exchanging control signals with the image memory unit 102, and a port different from the interface 107 in FIG. 5 is used.

As described above, the present copying machine alone can perform the copying process of the original image, but the description thereof will be omitted, and in the following, the host computer 103 (in some cases, the external operation device 109) will be described. The operation under control will be described. However, since this apparatus is not directly connected to the host computer 103, as a result, the processing based on the instruction from the memory apparatus 102 is performed.

According to the flow chart of FIG. 22, the copying machine 1
The operation contents of the CPU 2101 of 01 will be described.

First, in step S1, it is determined whether a control command is received via the interface 2110, and the process waits until the control command is received.

When the control command is received, the process proceeds to step S2, and it is determined whether or not the instruction content by the command is a document image reading and transfer request. In the case of such a request, the process proceeds to step S3, the reading of the original image mp is started, and the read image is transferred to the image memory unit 102 via the interface 107 (see FIG. 5).

If it is determined that the request is not for reading and transferring the original, the process proceeds to step S4, and it is determined whether the request is for feeding the recording paper. If it is determined that the request is a recording paper feed request, the flow advances to step S5 to convey the recording paper by the instructed amount. Although the meaning of this processing will be described later, in brief description, in addition to the recording sheet conveyance from the leading position of the recording sheet to the recordable area, as shown in images A and B in FIG. When the transferred image is printed, wasteful image recording processing (operation of the recording head, etc.) is performed between immediately after recording the image A and immediately before recording the image B. Therefore, during this period, the image memory unit 102 does not transfer the blank image data, but transmits a control command for carrying the recording paper.

If it is determined that the received control command is not one of the above, the process proceeds to step S6,
Perform the corresponding processing. This also includes a command notifying that the image data to be recorded will be transferred.

Next, FIG. 23 shows a block diagram of the control system of the image memory unit 102 of the embodiment, and FIG.
3 is a flowchart showing the operation contents in 3.

In the figure, 2301 is a CPU which controls the entire image memory unit, and 2302 is a CPU.
A ROM 2303 that stores an operation processing procedure of 2301 (a program according to the flowchart of FIG. 24) is a RAM that stores a work area of the CPU 2301, and an image management table 2303a is stored and managed. An image storage unit 2304 has the configuration shown in FIG. Reference numeral 2305 denotes an interface for exchanging control commands with the copying machine, 2306.
Is an interface for exchanging control commands with the host computer. The image management table 2303a stores management data indicating what size (vertical and horizontal dot number) of an image is stored in the image memory 607 (see FIG. 10) in the image storage unit 2304.

Description will be made with reference to the flowchart of FIG.

First, in step S11, the process waits until an instruction command is received from the host computer 103.

When any instruction command is received,
In step S12, it is determined whether it is an image data reception instruction. If it is determined that the command is such an instruction command, the process proceeds to step S13, image data is received from the host computer and stored in the image memory 607, and the image management table 23
Update the contents of 03a.

If it is determined that the received instruction command is an image reading instruction, the process proceeds from step S15 to step S16 to read the original image and send the read image transfer request command to the interface 230.
5 to the copier. As a result, on the copier side,
The original image as described above is read and the read image is transferred to the main image memory unit 102.
The transferred image data is sequentially stored in the image memory 607. Then, the process proceeds to the next step S17 to update the image management table.

If it is determined that the instruction from the host computer is an image transmission instruction, step S
In step S19, the image data instructed by the instruction command is taken out from the image memory 607 and transferred to the host computer side.

If it is determined that the instruction from the host computer is a print output instruction, step S20.
From step S21, the image (s) to be printed included in the instruction command, the print position information of each image, and the number of paper feed sections by non-printing based on the content of the image management table Calculate the length of the feed section. Then, in the next step S23, in the non-printing section, a command to that effect is transmitted to the copying machine 101, and in the printing area, the image data is transmitted from the image memory 607 to the copying machine by the processing described above. Then, the layout printing of the image is performed.

On the other hand, if it is determined that the command is not the print output instruction command, the process proceeds to step S21 and the corresponding process is performed.

As a result of the above processing, the image memory unit 1
As shown in FIG. 19, the print result of the output image of No. 02 can record the image instructed by the host computer at the position designated by the host computer, and the arrow 1906 between the image A and the image B By simply feeding the recording paper to the non-printing area such as a portion, it is possible to skip at high speed. In the figure, 1901 is a sheet, 1902 is an image area, and 1903 is a print head scanner area. As shown in the figure, the laid-out area is set to 400 as in the first embodiment.
When converting from dpi to 50 dpi, round-down calculation and round-up calculation are performed, and a print head scan area is provided in a larger number than the image area.

In addition, the embodiment provides an excellent effect in an ink jet recording head and a recording apparatus which eject ink by utilizing thermal energy among the ink jet recording methods.

Regarding its typical structure and principle, see, for example, US Pat. No. 4,723,129 and US Pat.
What is done using the basic principles disclosed in 740,796 is preferred. This method can be applied to both the so-called on-demand type and continuous type, but in the case of the on-denmed type in particular, it is arranged corresponding to the sheet or liquid path holding the liquid (ink). By applying at least one drive signal to the electrothermal converter, which corresponds to the recorded information and causes a rapid temperature rise exceeding nucleate boiling, thermal energy is generated in the electrothermal converter, and the thermal action of the recording head is generated. It is effective because the film is boiled on the surface, and as a result, bubbles in the liquid (ink) can be formed in one-to-one correspondence with this drive signal. The liquid (ink) is ejected through the ejection openings by the growth and reduction of the bubbles to form at least one droplet. If this drive signal is made into a pulse shape, the growth and reduction of bubbles will be performed immediately and appropriately, so a liquid (ink) with excellent responsiveness will be obtained.
It is more preferable that the discharge can be achieved. As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. If the conditions described in U.S. Pat. No. 4,313,124, which is an invention relating to the rate of temperature rise on the heat acting surface, are adopted, more excellent recording can be performed.

As the constitution of the recording head, in addition to the combination constitution of the ejection port, the liquid passage, and the electrothermal converter (the linear liquid passage or the right-angled liquid passage) as disclosed in the above-mentioned specifications, Actions using US Pat. No. 4,558,333 and US Pat. No. 4,459,600 disclosing a configuration in which a heat acting portion is arranged in a bending region are also included in the present invention. Is. In addition, JP-A-123,670, which discloses a configuration in which a common slit is used as a discharge portion of the electrothermal converter for a plurality of electrothermal converters, and a pressure wave of thermal energy is absorbed. The present invention is also effective as a configuration based on Japanese Patent Laid-Open No. 138,461 of 1984, which discloses a configuration in which an opening corresponds to a discharge portion.

In addition, by being attached to the apparatus main body, it can be electrically connected to the apparatus main body and can be supplied with ink from the apparatus main body of a replaceable chip type recording head or the recording head itself. The present invention is also effective when a cartridge-type recording head that is specially provided is used.

Further, it is preferable to add recovery means for the recording head, preliminary auxiliary means, etc., which are provided as a configuration of the recording apparatus of the present invention, because the effects of the present invention can be further stabilized. Specific examples thereof include capping means, cleaning means, pressurizing or suctioning means, electrothermal converter or other heating element for the recording head, or preheating means for the combination thereof. ,
It is also effective to perform stable recording by performing a preliminary discharge mode in which discharge is performed separately from recording.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but the recording head may be integrally formed or a plurality of combinations may be used. The present invention is also extremely effective for an apparatus provided with at least one of full color by color mixing.

It can be dropped.

In the above description, a liquid ink is used, but the present invention can be applied to an ink that is solid at room temperature or an ink that is in a softened state at room temperature. In the above-mentioned inkjet device, the temperature of the ink itself is generally controlled within a range of 30 ° C. or higher and 70 ° C. or lower to control the temperature of the ink so that the viscosity of the ink is in a stable ejection range. Any liquid may be used as long as the ink is liquid. In addition, the temperature rise due to the thermal energy is positively prevented by using it as the energy of the state change of the ink from the solid state to the liquid state, or the ink that solidifies in the notification state is used to prevent the evaporation of the ink. However, in any case, by applying heat energy such as ink that is liquefied by applying heat energy according to a recording signal and is ejected as an ink liquid or that has already started to solidify when it reaches a recording medium. Ink specifications having the property of liquefying for the first time are also applicable to the present invention. In such a case, the ink is disclosed in JP-A-54
-56847 or Japanese Patent Application Laid-Open No. 60-71260, such as facing the electrothermal converter in the state of being held as a liquid or solid in the recesses or through holes of the porous sheet. It may be in the form. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0090]

As described above, according to the present invention, in an image processing system in which a device for storing a plurality of images and a device for actually recording images are separated, layout printing can be easily performed and recording can be performed. It also becomes possible to perform processing efficiently.

[0091]

[Brief description of drawings]

FIG. 1 is a configuration diagram schematically showing an image processing system in a present embodiment.

FIG. 2 is a diagram showing a print area in the system of FIG.

FIG. 3 is a diagram showing a print head area in ay direction in an example.

FIG. 4 is a diagram showing timing in the x direction according to the embodiment.

FIG. 5 is a schematic block diagram showing an internal configuration of a copying machine 101 according to the embodiment.

FIG. 6 is a diagram illustrating scanning of the line sensor according to the embodiment.

FIG. 7A is a diagram showing details of scanning by the line sensor according to the embodiment.

FIG. 7B is a diagram showing details of scanning of the line sensor according to the embodiment.

FIG. 8 is a timing chart at the time of reading an original according to the embodiment.

FIG. 9 is a diagram showing bit contents of data X according to an embodiment.

FIG. 10 is a block diagram showing a schematic configuration of an image memory unit 102 of the embodiment.

FIG. 11 is a diagram illustrating in detail the image memory 607 according to the embodiment.

FIG. 12 is a timing chart of image data input from the scanner and addresses output from the address generation circuit in the embodiment.

FIG. 13 is a diagram showing a storage state of image data in the image memory when the data X is not supported according to the embodiment.

FIG. 14 is a circuit diagram showing a configuration of an address generation circuit 608 that generates an address of an image memory in the embodiment.

15 is a timing chart in the circuit shown in FIG.

FIG. 16 is a block diagram of a control circuit when accessing the image memory 607 from the DMA and the CPU in the embodiment.

FIG. 17 is a read timing chart when the host computer does not support the data X in the embodiment.

FIG. 18 is an explanatory diagram showing a relationship between print pixels and an image stored in a memory in the embodiment.

FIG. 19 is a diagram showing a print area according to the embodiment.

FIG. 20 is a configuration diagram of a conventional image processing system.

FIG. 21 is a block configuration diagram of a control system of the copying machine in the embodiment.

FIG. 22 is a flow chart for explaining an outline of operation of the copying machine in the embodiment.

FIG. 23 is a block configuration diagram of a control system of the image memory unit in the embodiment.

FIG. 24 is a flowchart for explaining an outline of operation of the image memory unit in the embodiment.

[Explanation of symbols]

101 Copier 102 Image Memory Unit 103 Host Computer 104 Copy Start Key 105 Pressure Plate 107-1, 107-2, 107-3 Cable 110 Multi-valued Interface Cable 117, 118, 119 Interface Cable 114, 115 Selector 116 Communication Control Device 201 Line Sensor 201 A / D converter 204 Shading correction circuit 205, 215 Black character processing circuit 206 Magnification circuit 207 Switch unit 208 Data X decoding circuit 209 LOG conversion circuit 210 Masking circuit 211 Edge processing circuit 213 γ table 214 Binarization circuit 216 Printing Head 601 Input masking circuit 602 Smoothing circuit 603 Synthesis circuit 604 γ table 605, 606 FIFO 607 Image memo Re 608 Address counter 609 OSC circuit 610 γ table 611 Enlargement circuit 612 CPU 613 Area signal generation circuit 614 Video / CPU interface 615 I / O 901, 907, 910, 913, 915, 916 Register 902, 918, 919 Selector 903, 911 Counter 904, 905, 908 Flip-flop 906, 909, 912 Comparator 917, 914 Adder circuit 1201, 1202 Selector 1203, 1205, 1209 Adder circuit 1204, 1208 Register 1206 Start address 1207 Flip-flop 1210 Rate multiplier 1801 Digital color copier 1802 Dedicated image memory 1803 Host computer 1804 Film scanner

Claims (1)

[Claims] 1. An image processing system comprising a first device for storing a plurality of images and a second device for recording as a visible image on a predetermined recording medium, the image processing system being stored in the first device. When recording a plurality of images with the second image, the individual images to be printed stored in the first device are merged, transferred to the second device as one image, and recorded. An image processing system, wherein a predetermined command is generated between images to be recorded and the second device simply conveys the recording medium.