JPH05136929A - Picture processing unit and picture processing system having said picture processing unit - Google Patents

Abstract

PURPOSE:To attain the communication between a digital color copying machine and an external operation device even when a power supply for an exclusive memory device connecting to the digital color copying machine and the external operation device and sending/receiving data between the both is interrupted. CONSTITUTION:The picture processing system is configured by connecting a digital color copying machine 101 having a reader printer function and an external operation device 109 to a picture memory unit 102 respectively through a cable and the picture memory unit 102 uses selectors 114, 115 to connect a communication controller 116 to the digital color copying machine 101 and the external operation device 109 electrically at application of power and connects the digital color copying machine 101 and the external operation device 109 not through the communication controller 116 electrically at interruption of power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for storing an image in a read image memory and editing an image using a host computer to obtain an output image, and an image processing system having the apparatus.

[0002]

2. Description of the Related Art In recent years, digital color copying machines have come into widespread use in which an original is digitally color-separated and read, and color recording is performed based on the read digital color image signal. As shown in FIG. 21, this type of copying machine 1801 can be further connected to a dedicated memory device 1802 and a host computer 1803. The read image is stored in the dedicated memory device 1802, and the host computer 1803 is stored. Image editing processing can be performed using. Further, by connecting the film scanner 1804, the functions of the digital color copying machine can be diversified.

[0003]

However, in the above-mentioned conventional example, the communication between the film scanner 1804 and the digital color copying machine 1801 is performed by the dedicated memory device 180.
It can be configured so that the two are intervening, and both parties are not directly exchanging data. In this case, the film scanner 1804 cannot be used when the power of the dedicated memory device 1802 is OFF. Therefore, in order to use the film scanner 1804, it is necessary to turn on the power of the dedicated memory device or directly connect the external operation device to the digital color copying machine 1801 without using the dedicated memory device. There was a drawback.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to be connected to a digital color copying machine and an external device and to exchange data between them. Power to the dedicated memory device is off
An object is to provide an image processing apparatus that enables communication between a digital color copying machine and an external apparatus even in this state, and an image processing system having the apparatus.

[0005]

[Means for Solving the Problems]
In order to achieve the object, an image processing device according to the present invention is an image processing device having a communication control means for storing and communicating data among a plurality of devices, and when the power is turned on, the communication control means is operated by the plurality of devices. And a second connecting means for electrically connecting at least two of the plurality of devices without the communication control means when the power is off. ..

The image processing system according to the present invention further comprises an input means for inputting image data, a storage means for storing the image data input by the input means, and an output processing based on the image data stored by the storage means. In the image processing system having an output means for performing the above, and a control means for controlling the input means, the storage means, and the output means, the storage means includes the communication control means and at least two of the plurality of devices. First connecting means for electrically connecting the first and second connecting means for electrically connecting at least two of the plurality of devices without the communication control means, and the first connecting means when the power is turned on. And a second switching means for switching to the second connecting means when the power is turned off.

[0007]

According to this structure, in the image processing apparatus,
Alternatively, in the image processing system, the first connecting means is
When the power is turned on, the communication control means is electrically connected to at least two of the plurality of devices, and the second connecting means electrically connects at least two of the plurality of devices without the communication control means when the power is turned off. Connect to each other.

[0008]

Embodiments of the image processing apparatus of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1 is a block diagram schematically showing an image processing system according to a first embodiment of the present invention.

This system, as shown in FIG. 1, includes a digital color copying machine 101, a host computer 103,
The external operation device 109 is connected by a cable extending from the image memory unit 102. 107-1 is a cable connecting the image memory unit 102 and the digital color copying machine 101, and 107-2 is the image memory unit 102 and the host computer 103.
Reference numeral 107-3 denotes a cable connecting the image memory unit 102 and the external operation device 109, respectively.

Here, the above configuration will be specifically described. In the figure, 101 is a digital color copying machine (hereinafter referred to as "copying machine") equipped with a color scanner and an inkjet printer. The copying machine 101 can obtain a color copy image independently by placing a document under the pressure plate 105 and pressing the copy start key 104. Further, the image read by the color scanner of the copying machine 101 can be simultaneously sent as digital data to the image memory unit 102 via the cable 107. The sent image data is sent to the host computer 103 via a general-purpose I / F 107-2 such as GP-IB.
Sent to, enabling various image editing processes. The processed image data is sent to the scanner printer 101 via the image memory unit 102, and the edited image can be reproduced. Further, by connecting the external operation device 109, it is possible to operate the copying machine 101 from the outside with more functions.

FIG. 2 is a circuit diagram showing interface communication switching means in the system of FIG.

The image memory unit 10 will be described with reference to FIG.
The internal configuration of No. 2 will be described. In the figure, 110 is a multi-valued interface cable, 117, 118, 119 are interface cables, and multi-valued data can be exchanged. 114 and 115 are selectors, 116 is a communication control device that controls communication with an external device connected to the image memory unit 102 and stores data during communication by a memory (not shown), and α and β are data cables, respectively. ing.

In the above structure, the image memory unit 1
02, the signal from the copying machine 101 enters the selector 115 through the interface cable 117.

When the power supply of the image memory unit 102 is OFF, the terminal a is selected by the switching switch c in each of the selectors 114 and 115. That is, the power source O
At the time of FF, the copying machine 1 does not go through the communication control device 116.
01 and the external operation device 109 are electrically connected to each other so as to be through.

By this operation, the signal from one copying machine 101 is sent to the external operating device 109 via the interface cable 117, the selector 115 and the interface cable 118.

On the other hand, the signal from the external operating device 109 is
It is sent to the copying machine 101 via the interface cable 119, the selector 114, and the multilevel interface cable 110.

Next, the image memory unit 102 turns on the power source O.
In the case of N, the selectors 114 and 115 select the terminal b by the switching switch c.

In this case, the image memory unit 102 obtains the signal of the copying machine 101 by monitoring the interface cable 117 with the data cable α. Then, the communication control device 116 transmits a data signal to the external operation device 109 via the interface cable 118. Further, the image memory unit 102 detects what kind of external device is connected by monitoring the multi-value interface cable 119 with the data cable β.

Further, in the image memory unit 102,
The communication control device 116 transmits a data signal to the copying machine 101 via the interface cable 110 based on the signal monitored by the data cable β.

As described above, the image memory unit 102
When the power is turned off, the copying machine and the external operating device are electrically brought into a through state, and communication between them is possible even when the power of the image memory unit 102 is turned off. Further, in FIG. 2, each interface cable 11
The details of 0, 117, 118, and 119 are shown in FIG.
Shown in. As shown in A, the data line of the eight bits in each cable, control gains for outputting the control signal of 8 bits, power E _X V _C for the external device
_C and ground line GND are provided.

Each control line has a line dedicated to each signal shown in FIG. Reference numeral 118 denotes a power supply device, which connects the commercial power supply provided from the commercial power supply line for the image memory unit 102 to the communication control device 116.
Etc. to generate internal power INT-V _CC for driving etc.
Further, each selector 114, 115 is a communication control device 116.
Unlike, operated by the power source E _X V _CC for the foregoing external device. Further, the commercial power supply is input to the copying machine 101, the copying machine power supply from such commercial power foregoing external device E _X
Generate V _CC . Also, the external operating device 109 operated by a power source E _X V _CC for an external device provided via the image memory unit 102 described above.

FIG. 3 is a timing chart showing the timing of external device recognition when the power of the image memory unit is turned on in the first embodiment.

Here, BUSY indicates that the copying machine 101 is being used (High Active), and REQ is sent to the copying machine 101.
Indicates 8-byte signal (High Active), ACK is copy machine 1
Shows the signal (High Active) returning from 01, and PR
SEL indicates a selector switching switch c, and SRDY indicates PowerO sent from the image memory unit 102 to the copying machine 101.
N signal, RRDY is Pow sent from the copying machine 101.
er ON signal is shown.

Next, the operation of the first embodiment will be described.

FIG. 4 is a flow chart for explaining the operation of the image memory unit according to the first embodiment when the power is turned on.

In this embodiment, there are roughly three steps 1,
The operation is performed in step and step3.

In step 1, the image memory unit 10
If the power of the second copying machine is ON and the power of the copying machine 101 is not ON, the power is ON. If the power is ON, it is checked whether the copying machine 101 is in use or not, and the operation is awaited. If it is not in use, when the 8-byte communication signal is not transmitted / received, the selector SW of each of the selectors 114 and 115 in FIG.
Prepare to monitor the information of external equipment from 9.

That is, in S1-1, PRDY
The power supply of the copying machine 101 is confirmed by "High (= 1)", the usability of the copying machine 101 is confirmed by BUSY "High" in S1-2, and the copying machine 101 is confirmed in S1-3.
REQ and ACK each confirm "Low (= 0)" to confirm the availability of the transmission / reception path of the copying machine 101, and in S1-4, the switching switch c "H" of the selectors 114 and 115.
The switch to the terminal b is made by "ig".

At the next step 2, in S2-1,
The external operating device is recognized, and in S2-2, the Power ON signal (SRDY) of the memory unit is set to "Low" after the recognition is completed. This is an operation performed to set PRDY to "Low" at the next step3.

Then, in step 3, S in step 2
Following the RDY signal, the power ON signal PRDY of the copying machine 101 becomes PRDY or "Low". In S3-1, waiting for this PRDY to become "Low", S3-
In 2, the PRSEL is set to “L” after it becomes “Low”.
ow ", the selector 11 of FIG.
The switching switches c of 4, 115 are switched to the terminal a side. This allows the copying machine 101 to monitor the information of the external operating device.

Further, in S3-3, the copying machine 101
Recognizes the external device, and after recognition is completed, PRDY is set to "H".
Then, the process is terminated.

As described above, the external device is recognized in the order of the image memory unit and the copying machine. The power source of the external operation device 109 depends on the power source ON / OFF of the copying machine 101.

FIG. 5 is a schematic block diagram showing the internal structure of the copying machine 101 according to the first embodiment, and FIG. 6 is a diagram for explaining the scanning of the line sensor according to the first embodiment.

In FIG. 5, 201 is a CCD line sensor (hereinafter referred to as "line sensor"), and 203 is an enlarged view thereof. As shown in FIG. 5, R, G, B,
R, G, B, ... and sensors of each color are arranged side by side.
One set of B is one pixel. Reference numeral 202 is an A / D converter, 204 is a shading correction circuit, and 205 and 215.
Is a black character processing circuit, 206 is a scaling circuit, 207 is a switch unit, 208 is a data X decoding circuit, 209 is a LOG conversion circuit, 210 is a masking circuit, 211 is an edge processing circuit, 212 is a head shading circuit, 2
13 is a γ table, 214 is a binarization circuit, and 216 is a print head.

The line sensor 201, as shown in FIG.
CCD main scanning in the horizontal direction with respect to the original and CCD in the vertical direction
Sub-scanning is sequentially performed to scan the entire document with BVE and V
According to a synchronization signal such as E, the first scan, the second scan ... The line sensor 201 is driven by, for example, a pulse motor, and can scan an arbitrary area under the control of a CPU (not shown). The difference between the scanning method when the data read here is sent to the printer and when it is sent to the image memory unit 102 will be described.

FIG. 7 is a diagram for explaining the details of the scanning of the line sensor according to the first embodiment.

FIG. 3A is an explanatory view for explaining a scanner method for printing with a printer. In the first scan, the CCD reading width is the total pixel width of the CCD,
132 pixels of pixels 1 to 132 are read. However, 128 pixels of pixels 2 to 129 are printed as the printer print width, and other pixels are discarded. This is because the copying machine employs a binarization method such as an error diffusion method that binarizes the peripheral data of the print data when printing the data. In the second scan, the area for four pixels (129 to 132 pixels) scanned in the first scan is read again, and 2
It is used as a connection process for digitization and as print data. In this way, when printing on the printer, several pixels are overread for each scan.

FIG. 7B shows the image memory unit 10.
FIG. 6 is an explanatory diagram illustrating a scanning method when sending read data to No. 2; As shown in the same drawing, the overlapping portion between the first scanning and the second scanning is eliminated, and the CCD reading width is 132 pixels in full. This is the image memory unit 1
This is because only the data is transferred to 02 and the binarization processing is not performed. As a result, the number of scans can be reduced when reading the same area as when printing, which is effective for speeding up.

As described above, in the first embodiment, the scan mode is changed when printing and when transferring to the image memory unit 102.

The image signal read by the line sensor 201 is converted into a digital signal by the A / D converter 202, and is subsequently processed as a digital signal.

FIG. 8 is a timing chart at the time of reading an original according to the first embodiment.

At the timing of reading the above-mentioned document, BVE in FIG. 8A indicates the start point of the CCD main scanning with respect to the document, and VE determines the timing of the CCD scanning. The CCD reads an image for each VE while moving in the main scanning direction. When one VE is enlarged as shown in FIG. 8B, each pixel has a video clock VC.
The data is transferred in a dot-sequential manner with R, G, and B as one pixel in synchronization with LK.

The image signal is then input to the shading correction circuit 204, and white correction / black correction is performed according to the characteristics of the CCD. The signal output from the shading correction circuit 204 is input to the black character processing circuit 205.
Here, black characters in the original are detected, processing is performed to eliminate color bleeding during printing, and to sharpen black characters. The data input to the black character processing circuit 205 is added with data X for determining the processing for each pixel after the detection of the black character. This is shown in FIG. 8 (C).

FIG. 9 is a diagram showing the bit contents of the data X according to the first embodiment. For black character processing, the presence or absence of the processing is added to bit 0. Further, as shown in the figure, other image processing is also added.

The image data to which the data X has been added is scaled (enlarged or reduced) to a desired size by the scaling circuit 206, and the image memory unit 1 is switched by the switch unit 207.
02 via the cable 107-1. In addition, the switch unit 207 selects the magnification change circuit 206 when the image memory unit 102 is not connected.
It is also possible to directly transfer the image data from the decoding circuit 208. As a result, the copying machine 101 can be independently operated as a color copying machine. The image memory unit 102 has a capacity capable of storing image data for 3 bands.

The image signal output from the image memory unit 102 via the scaling circuit 206 or the cable 107-1 is input to the data X decoding circuit 208 via the switch unit 207. The data X decoding circuit 208 decodes the content of the added data X and outputs the control signal whose content is shown in FIG. 9 to each processing block. Each processing block performs processing based on the control signal.

The image data is subjected to density conversion in the LOG conversion circuit 209 and masking circuit 210 and masking calculation processing according to the ink characteristics, and then the image is sharpened in the edge processing circuit 211, and the head is processed. It is input to the shading circuit 212. Here, the print head 2
Since the ink discharge amount, the direction, and the like are not constant among the pixels due to 16 variations, these corrections are performed by signal processing. The γ table 213 is a conversion table that determines the print density, and can be adjusted to a desired density.
In the binarization circuit 214, the control signals MIXDATA, NE
Based on GA and PHOTO, multivalued image data is converted into binary image data. The black character processing circuit 215 performs black character processing under the control based on the control signal KB, and the inkjet print head 216 performs printing. The operation timing of the print head 216 also follows the synchronization signals of BVE, VE, etc., like the line sensor 203 described above.

FIG. 10 is a block diagram showing a schematic structure of the image memory unit 102 of the first embodiment. From the figure, the flow of image data in the image memory unit 102 can be roughly grasped. In the figure, 601 is an input masking circuit, 602 is a smoothing circuit,
3 is a synthesis circuit, 604 is a γ table, 605 and 606 are FIFOs, 607 is an image memory, 608 is an address counter, 609 is a crystal oscillation circuit (hereinafter referred to as “OSC circuit”), 610 is a γ table, 611 is an expansion circuit, 612
Is a CPU, 613 is a region signal generating circuit, 614 is a video / CPU interface, and 615 is an I / O.

The image data transferred from the copying machine 101 is input to the input masking circuit 6 via the cable 107-1.
01 is input. Image data sent is CCD
Since the characteristics of the color separation filter of No. 3 remain unchanged, the calculation is performed here because the characteristics are adapted to the characteristics of general standards, for example, the NTSC standard. By the above calculation, the host computer 103
It is possible to standardize the handling of color data in and to standardize the color reproduction during printing. At this time, the data X is not calculated and is passed through.

The image data after the input masking is input to the smoothing circuit 602 and the synthesizing circuit 603. The composition circuit 603 will be described later. Smoothing circuit 6
In 02, smoothing processing is performed to prevent image deterioration due to moire. At this time, the matrix used for smoothing can be selected in three stages of 2 × 1, 2 × 2, 3 × 3, and although not shown, it can be selected by a data set from the CPU 612. Also at this time, no calculation is performed on the data X.

The γ table circuit 604 modulates the scanner input image into an image which has a desired gradation characteristic. This is also configured so that a free table can be set from the CPU as in the above. Both of the smoothing circuit 602 and the γ table circuit 604 can be freely selected by the user via the CPU 612 by a command from the host computer 103.

The image data corrected by the γ table circuit 604 is sent to the image memory 60 via the FIFO 605.
7 is stored in the address designated by the address generation circuit 608 which generates the address. Image memory 60
7 and the address counter 608 do not control by the image synchronization clock VCLK from the copying machine 101, but the OSC circuit 60 in the image memory unit 102.
Control is performed by a clock IVCLK obtained from the control unit 9, for example, timing control of memory refresh is performed.
In order to perform this clock conversion, FIFOs 605 and 606 are provided for input and output of image data. Therefore, even if the copying machine 101 has an abnormality and the clock VCLK is stopped, it is possible to recover without losing the contents of the memory.

FIG. 11 shows the image memory 6 according to the first embodiment.
It is a figure explaining 07 in detail. In the figure, the memory address is a linear address in the BVE direction when viewed from the CPU 612. Since the format of the image data used in the scanner and printer of the copying machine 101 is different, in the input / output mode to the copying machine 101 (hereinafter referred to as video mode), the address calculation becomes more complicated. On the other hand, when data is transferred from the host to the image memory under the control of the CPU 612 via the I / O 615 (hereinafter, referred to as CPU mode), the image file format of the host is often line-sequential line by line in the horizontal direction. Is easy and effective.

(Data Writing from Scanner to Image Memory) FIG. 12 is a timing chart of the image data input from the scanner and the address output from the address generating circuit 608 in the first embodiment, and FIG. FIG. 3 is a diagram illustrating an image memory when data X is not supported according to the first embodiment.

Image data is sequentially written in the FIFO 605 in synchronization with the clock CLK by the timing control of BVE and VE. After a while, the address counter 608 outputs the FIFORE, and the FIFO
Image data is sequentially read from 605 in synchronization with the clock IVCLK. At the same time, the address counter 608 also sequentially counts up or performs calculation, and the data is written in the address designated by the address (FIG. 12).

Here, when the application software of the host computer 103 does not support the data X, it can be dealt with only by changing the address calculation means. In other words, if the addresses shown in FIG. 12 (FIG. 12) are sequentially output, the storage area for the data X is filled and other data is stored in the image memory 607, so that it can be dealt with. After the second line of VE, R is again applied to the address (3, n + 3, ...) At which the data X is stored.
Since the data is written, as shown in FIG.
Will eventually disappear (not be stored) from the memory 607. As a result, when the host computer does not support the data X, the image memory 60
You can use 7 effectively. In this embodiment, when the data X is not supported, data for 4 bands can be stored.

FIG. 14 is a circuit diagram showing a configuration of an address generation circuit 608 for generating an address of the image memory in the first embodiment, and FIG. 15 is a timing chart in the circuit shown in FIG.

In FIG. 14, 901, 907 and 91
0, 913, 915, 916 are registers, 902, 91
8, 919 are selectors, 903, 911 are counters, 9
Reference numerals 04, 905 and 908 are flip-flops, and 906 and 9
Reference numerals 09 and 912 denote comparators, and reference numerals 917 and 914 denote addition circuits.

As shown in FIG. 15, when the copying machine 101 is started to read an image, the BVE
Signal SET controlled by CPU 612 while is Low
Accordingly, the selector 919 selects the read start address set in the register 901 in advance.
When the HS signal generated by the OSC circuit 609 based on the VE signal becomes Low during this period, the start address is selected by the selector 902 and the clock IVCLK is selected.
Accordingly, the start address is loaded into the counter 903 (time t ₁ ). At this time, the flip-flop 904
Also the start address is set. BVE is High
At the same time as h, the image request signal REQ also becomes Low (time t ₂ ).

Generation of the line enable signal LE for defining the data read period of one line will be described. H
The output of the counter 905 reset by the S signal is compared with the line enable start value input to the comparator 906 and set in the register 907 in advance, and when the values match, a match pulse is output to the flip-flop 908 ( Time t ₃ ). Similarly, when the comparator 909 matches the line enable end value set in the register 910, it outputs a match pulse to the flip-flop 908. Flip flop 9
Reference numeral 08 denotes a JK flip-flop, which is the period of these two coincidence pulses, that is, the register 907 and the register 9
The line enable signal LE can be output for a period determined by the value set to 10. This line enable signal LE
Becomes a read enable for the counters 911 and 903 and the FIFO 605, and the sequentially-produced data is stored at the designated address.

The counter 911 for counting the clock IVCLK and the set value of the register 913 are compared by the comparator 9
12 compares the clock IVCLK to 4
Every second, the comparator 912 generates a load signal LD. The generated load signal LD becomes the load signal of the counter 903, and the value obtained by adding the output address of the counter 903 and the value set in the register 915 in the adder circuit 914 is added to the counter 903 via the selector 902. To load. Taking the example of FIG. 11, the value set in the register 915 becomes “m” (see FIG. 12).
(See the address of FIG. 12), and in the case of FIG. 13, it is “n” (see the address of FIG. 12).

When the count advances and the next HS is input, the value set in the flip-flop 904 and the value set in the register 916 are added together by the adder circuit 9.
It is added at 17, passed through the selectors 918, 919, and 902, and loaded into the counter 903 as the head address of the next line. The value set in the register 916 is changed depending on whether or not the data X is supported, as described above. In the case of FIG. 11, it is “4” (see the address of FIG. 12), and in the case of FIG. 12, it is “3” (see the address of FIG. 12).
Becomes As described above, the address output from the counter 903 is given to the image memory 607 via the selector 1201, and the read image is stored in the memory 607. Note that the selector 1201
Will be described later in detail.

(Reading Data from Image Memory to Host) The image data stored in the image memory 607 is CP
It is sent to the I / O 615 by DMA transfer under the control of U612 and transferred to the host computer 103 via the cable 107-2. The means will be described below.

FIG. 16 is a block diagram of a control circuit for accessing the image memory 607 from the DMA and the CPU in the first embodiment. In the figure, 1201,1
Reference numeral 202 is a selector, 1203, 1205 and 1209 are addition circuits, 1204 and 1208 are registers, 1206 is a start address, 1207 is a flip-flop, and 121.
0 indicates a rate multiplier, respectively.

The image memory 607 transfers image data to and from the copying machine 101 (hereinafter, referred to as Video mode) and transfers data to and from the CPU 612 or the host computer 103 (hereinafter, CPU.
This is different from the DMA mode) in that the address generation means is different. This is because in the video mode, the transfer rate is high and the same access means as in the CPU mode cannot be taken.

The selector 1201 is a selector for switching between the Video mode and the CPU / DMA mode, and can be selected by the CPU 612 according to the desired mode. The selector 1202 can select a mode in which the CPU 612 can directly access (hereinafter, referred to as CPU mode) and a mode in which DMA transfer is performed (hereinafter, referred to as DMA mode). For example, when the CPU mode is selected, the CPU 61
An address obtained by adding the address output from 2 and the value set in the register 1204 in the adder circuit 1203 is output. This is because, in this embodiment, when the data X is supported, the image data is stored for only three bands, but the image memory is still large in capacity and therefore deviates from the space accessible by the CPU. Therefore, the accessible memory space is expanded by adding data.

In the DMA mode, the register 1206 for setting the DMA start address and the read signal IO
The data obtained by adding the outputs of the flip-flop 1207 using the RD or the write signal IOWR as a clock is output as an address. The flip-flop 1207 is
The output of the adder circuit 1209 is latched for each pulse of the signal IORD / IOWR, and the output is returned to the adder circuit 1209 which adds the set value of the register 1208. Thereby, for example, when the setting of the register 1208 is "3", a multiple of 3 is obtained, and when the setting of the register 1208 is "4", a multiple of 4 is obtained as the output of the flip-flop 1207. The resulting output address is the signal IORD / IOWR at the start address.
It is an address obtained by adding a certain integer multiple for each pulse of. This is because, as shown in FIG. 8, the image data is stored as dot-sequential in the linear address direction, so for example, in the case of line-sequential transfer in which only R data is desired, the start address “0” is a multiple of 4 This is because it is necessary to generate an address to which is added. Further, the flip-flop 1207 is reset when the start address is set.

Also, the IOWR pulse is input to the rate multiplier 1201 and the IOWR pulse itself is thinned out by this output, whereby the host computer 10
Reduction transfer is also possible at the time of image data transfer from No. 3. This is possible because the address is not updated by thinning out the IOWR pulse.

By the means described above, as shown in FIG. 3, the image data stored in the memory 607 each time the scanning is completed,
It is being transferred to the host computer 103. The above description is for the case where data is transferred from the scanner to the host computer 103.

(Data Writing from Host Computer to Image Memory) Next, the operation from the host to the printer will be described by returning to FIG. The image data edited by the host computer 103 is sequentially transferred to the I / O 615 via the cable 107-2. The transferred image data is
In the image memory unit 102, it is stored in the image memory 607 by DMA transfer. At this time, as described above, the addresses are sequentially generated from the start address set in the start register 1206 of FIG. 16 by the signal IORD. For example, in the case of line sequential, the register 1208 is used to generate an address for each "3" or "4".
Set the value of. Here, if the host computer 103 supports the data X, the set value is set to "4" so that the data is stored as shown in FIG. 8, and if the data X is not supported, the set value is set to "3". ", The data X is not stored as shown in FIG.

(Reading Data from Image Memory to Printer) When the data transfer from the host is completed, the counter 903 is selected by the selector 1201 shown in FIG.
Place the address bus in Video mode. The image reading in the video mode is similar to the writing, from the start address set in the register 901 of FIG. 14 to the BV.
Addresses are sequentially calculated by timing control of E, VE, and IVCLK, and reading is performed according to these addresses.

FIG. 17 shows a read timing chart when the host computer does not support the data X as shown in FIG. The LE signal becomes Low (time t ₁₁ ).
At the same time, the counters 903 and 911 in FIG. 14 start counting and generate an address. At this time, as shown in the timing chart, the extra data R is always read. At the same time, the 2-bit counter 920 is also operated and 2
A bit signal γSEL is generated. The signal γSEL is
By inputting to the γ table 610 of FIG. 10, the function as the γ table can be made for each color. When γSEL is 0, it is the R table, when it is 1, it is G, and when it is 2, it is B.
When γSEL is 3, the data X generation table is selected, and if the host computer 13 supports the data X, data through is set, and if it is not supported, it is constant for any input data. The data is set to be output as data X. Therefore, FIG.
As shown in 7, extra R is always read out and converted into data X.

When the data transfer for the first scan is completed, the addresses are calculated as described above, and the addresses are sequentially read and printing is performed. When the printing for the first scan is completed, the data transfer for the second scan is performed next, and by repeating the above,
Get a printout of the i-image.

At this time, a joining process as shown in FIG. 10A is also necessary, and the process will be described below.

FIG. 18 is an explanatory diagram showing the relationship between the print pixels and the image stored in the memory in the first embodiment.

When the data transfer of the first transfer image is completed from the host computer 103 to the image memory 607 of the image memory unit 102, 132 pixels are read from the image memory 607 in the VE direction. Of these, the print head 216 prints 128 pixels from pixel 2 to pixel 129. As described with reference to FIG. 10A, the other pixels are processed as the connecting process and are not printed.

The read start address of the data read from the image memory 607 at the time of the second scan of the print head 216 corresponds to the pixel 129 at the time of the first scan.
From the host computer 103 to the image memory 607
Since the data transfer has been completed, the data transfer start address of the second transfer image is set to 132 pixels after the pixel 133, and the data is transferred to the empty area of the memory where printing is completed. As described above, by sequentially performing the transfer processing from the host computer 103 to the image memory 607, the memory can be used efficiently and effectively,
The number of transfers can also be reduced.

The γ table 610 shown in FIG. 10 is added to the image data read from the image memory 607 as described above.
After being enlarged to a desired size through the enlargement circuit 611,
It is input to the FIFO 606. Here, the clock is converted and input to the synthesis circuit 612. At this time,
At the same time, when data is read from the scanner of the copying machine 101, a memory image and a scanner image output can be obtained by the synthesizing circuit 603. This combining timing is performed based on the SELECT signal generated by the area signal generating circuit 613, and the combining can be performed at a desired position.

As described above, according to the first embodiment, it is possible to communicate between the copying machine and the external operating device even when the image memory unit is powered off. <Second Embodiment> Next, a second embodiment will be described.

FIG. 19 is a circuit diagram showing a switching means for interface communication according to the second embodiment.

Also in this embodiment, as in the first embodiment, the system has the same configuration as in FIG.

In FIG. 19, 1612 is a copying machine and 16
Reference numeral 11 is an image memory unit, and 1613 is an external operation device. In the image memory unit 1611, 1614 and 1615 are selectors, 1616 is a communication control device, 1617, 1618 and 1619 are interface cables, multilevel interface cables,
α'and β'indicate data cables, respectively.

A signal from the copying machine 1612 enters the selector 1615 via the interface cable 1617. When the image memory unit 1611 is powered off or not being processed, the terminal a is selected by the switching switch c,
The signal from the copying machine 1612 is sent to the external operation device 1613 via the interface cable 1617, the selector 1615, and the interface cable 1618.

On the other hand, a signal from the multi-part operating device 1613 is sent from the interface cable 1619 to the selector 1
Enter 614. Also in this case, the image memory unit 161
1 is the power is OFF, the terminal a is selected by the switching switch c, and the multi-value interface cable 16
10 is returned to the copying machine 1612.

Next, when the image memory unit 102 is being processed, the terminal b is selected by the switching switch c of the selectors 1614 and 1615.

In this case, the image memory unit 1611 obtains the signal of the copying machine 1612 by monitoring the interface cable 1617 with the data cable α '. Then, a data signal is transmitted from the communication control device 1616 to the external operation device 1613 by the interface cable 1
Via 618. In addition, the image memory unit 16
The 11 can detect what kind of external device is connected by monitoring the interface cable 1619 with the data cable β ′.

Further, the image memory unit 1611 is
Based on the signal monitored by the data cable β ′, the communication control device 1616 transmits a signal to the copying machine via the interface cable 1610.

FIG. 20 is a diagram showing the timing of communication switching when the image memory unit performs processing in the second embodiment.

In the figure, the process starts at (a), that is, the switching switch c of the selectors 1614 and 1615 in FIG.
The terminal a is switched to the terminal b.
In addition, the processing ends in (b), and the selector 161 in the figure
Switching from the terminal b to the terminal a is performed by the switching switch c of 4,1615.

As described above, the image memory unit 1611
The image memory unit 1611 communicates with the copying machine 1612 only during the process (1), and otherwise the copying machine 1612 and the external operation device 1613 are electrically set to the through state.

As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained.

Now, the present invention relates to an ink jet recording head and a recording apparatus for ejecting ink by utilizing thermal energy, especially in the ink jet recording system.
It has an excellent effect.

With regard to its typical structure and principle, see, for example, US Pat. No. 4,723,129 and US Pat.
What is done using the basic principles disclosed in 740,796 is preferred. This method can be applied to both the so-called on-demand type and the continuous type, but especially in the case of the on-demand type, it is arranged corresponding to the sheet or liquid path holding the liquid (ink). By applying at least one drive signal to the electrothermal converter, which corresponds to the recorded information and causes a rapid temperature rise exceeding nucleate boiling, heat energy is generated in the electrothermal converter, and the heat of the recording head is generated. This is effective because the film is boiled on the working surface, and as a result, bubbles can be formed in the liquid (ink) in a one-to-one correspondence with this drive signal. The liquid (ink) is ejected through the ejection openings by the growth and reduction of the bubbles to form at least one droplet. If this drive signal is made into a pulse shape, the growth and reduction of bubbles will be performed immediately and appropriately, so that the liquid (ink) with excellent responsiveness will be used.
It is more preferable that the discharge can be achieved. As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. If the conditions described in U.S. Pat. No. 4,313,124 of the invention relating to the rate of temperature rise on the heat acting surface are adopted, more excellent recording can be performed.

As the constitution of the recording head, in addition to the combination constitution of the discharge port, the liquid passage, and the electrothermal converter (the linear liquid passage or the right-angled liquid passage) as disclosed in the above-mentioned specifications, Actions using US Pat. No. 4,558,333 and US Pat. No. 4,459,600 disclosing a configuration in which a heat acting portion is arranged in a bending region are also included in the present invention. Is. In addition, JP-A-123,670, which discloses a configuration in which a common slit is used as a discharge portion of the electrothermal converter for a plurality of electrothermal converters, and a pressure wave of thermal energy is absorbed. The present invention is also effective as a configuration based on Japanese Patent Laid-Open No. 138,461 of 1984, which discloses a configuration in which an opening corresponds to a discharge portion.

In addition, by being attached to the apparatus main body, it can be electrically connected to the apparatus main body and can be supplied with ink from the apparatus main body by a replaceable chip type recording head or the recording head itself. The present invention is also effective when a cartridge-type recording head that is specially provided is used.

Further, it is preferable to add recovery means for the recording head, preliminary auxiliary means, etc., which are provided as the constitution of the recording apparatus of the present invention, because the effects of the present invention can be further stabilized. Specific examples thereof include capping means, cleaning means, pressurizing or suctioning means, electrothermal converters or heating elements other than these, or preheating means for the recording head. ,
It is also effective to perform stable recording by performing a preliminary discharge mode in which discharge different from recording is performed.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but the recording head may be integrally formed or a plurality of combinations may be used. The present invention is also extremely effective for a device provided with at least one of full color by color mixing.

Although liquid ink is used in the above description, the present invention can be applied to both an ink which is solid at room temperature and an ink which is softened at room temperature. In the above-mentioned inkjet device, the temperature of the ink itself is generally adjusted within the range of 30 ° C. or higher and 70 ° C. or lower to control the temperature of the ink so that the viscosity of the ink is within the stable ejection range. Any liquid may be used as long as the ink is liquid. In addition, it is possible to prevent the temperature rise due to thermal energy from being positively used as the energy of the state change of the ink from the solid state to the liquid state, or to use the ink that solidifies in the standing state for the purpose of preventing the evaporation of the ink. However, in any case, by applying heat energy such as ink that is liquefied by applying heat energy according to a recording signal and ejected as an ink liquid, or that already begins to solidify when it reaches the recording medium. The use of ink having a property of liquefying for the first time is also applicable to the present invention. In such a case, the ink is disclosed in JP-A-54
-56847 or Japanese Patent Application Laid-Open No. 60-71260, such as facing the electrothermal converter in the state of being held as a liquid or solid in the recesses or through holes of the porous sheet. It may be in the form. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. The external device of the present invention may be an external operation device, a film scanner, or a video input device.

[0100]

As described above, according to the present invention, the copying machine and the external device are connected even when the power of the memory device connected to the copying machine and exchanging data between them is turned off. Communication with the device is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram schematically showing an image processing system according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing interface communication switching means in the system of FIG.

FIG. 3 is a timing chart showing the timing of external device recognition when the image memory unit is powered on in the first embodiment.

FIG. 4 Po of the image memory unit according to the first embodiment
It is a flow chart explaining operation at the time of wer ON.

FIG. 5 is a schematic block diagram showing an internal configuration of a copying machine 101 according to the first embodiment.

FIG. 6 is a diagram for explaining scanning by the line sensor according to the first embodiment.

FIG. 7 is a diagram illustrating the details of scanning by the line sensor according to the first embodiment.

FIG. 8 is a timing chart at the time of reading a document according to the first embodiment.

FIG. 9 is a diagram showing bit contents of data X according to the first embodiment.

FIG. 10 is a block diagram showing a schematic configuration of the image memory unit 102 of the first embodiment.

FIG. 11 is a diagram illustrating in detail the image memory 607 according to the first embodiment.

FIG. 12 is a timing chart of the image data input from the scanner and the address output from the address generation circuit 608 in the first embodiment.

FIG. 13 is a diagram illustrating an image memory when data X is not supported according to the first embodiment.

FIG. 14 is a circuit diagram showing a configuration of an address generation circuit 608 that generates an address of an image memory in the first embodiment.

15 is a timing chart in the circuit shown in FIG.

FIG. 16 is a block diagram of a control circuit when the image memory 607 is accessed from the DMA and the CPU in the first embodiment.

FIG. 17 is a read timing chart when the host computer does not support the data X in the first embodiment.

FIG. 18 is an explanatory diagram showing a relationship between print pixels and an image stored in a memory in the first embodiment.

FIG. 19 is a circuit diagram showing switching means for interface communication according to the second embodiment.

FIG. 20 is a diagram showing a timing of communication switching when the image memory unit performs processing in the second embodiment.

FIG. 21 is a diagram showing an image processing system according to a conventional example.

[Explanation of symbols]

101 Copier 102 Image Memory Unit 103 Host Computer 104 Copy Start Key 105 Pressure Plate 107-1, 107-2, 107-3 Cable 110 Multi-level Interface Cable 117, 118, 119 Interface Cable 114, 115 Selector 116 Communication Control Device 201 Line Sensor 202 A / D converter 204 Shading correction circuit 205, 215 Black character processing circuit 206 Variable magnification circuit 207 Switch unit 208 Data X decoding circuit 209 LOG conversion circuit 210 Masking circuit 211 Edge processing circuit 212 Head shaded circuit 213 γ table 214 Binarization circuit 216 Printing head 601 Input masking circuit 602 Smoothing circuit 603 Synthesis circuit 604 γ table 605 606 FIFO 607 Image memory 608 Address counter 609 OSC circuit 610 γ table 611 Enlargement circuit 612 CPU 613 Area signal generation circuit 614 Video / CPU interface 615 I / O 901, 907, 910, 913, 915, 916 Register 902, 918, 919 Selector 903,911 Counter 904,905,908 Flip-flop 906,909,912 Comparator 917,914 Adder circuit 1201,1202 Selector 1203,1205,1209 Adder circuit 1204,1208 Register 1206 Start address 1207 Flip-flop 1210 Rate multiplier 1801 Digital color copier 1802 Dedicated image memory 1803 Host computer 1804 Films Canna

Claims (3)

[Claims] 1. An image processing apparatus having a communication control means for storing and communicating data between a plurality of devices, wherein the communication control means is electrically connected to at least two of the plurality of devices when the power is turned on. An image processing apparatus comprising: a first connecting unit; and a second connecting unit that electrically connects at least two of the plurality of devices without passing through the communication control unit when the power is turned off. 2. An image processing apparatus having a communication control means for storing and communicating data between a plurality of devices, the first connection means electrically connecting the communication control means to at least two of the plurality of devices. A second connection means for electrically connecting at least two of the plurality of devices without going through the communication control means; and a first switching for switching to the first connection means when the power is turned on. An image processing apparatus comprising: a means and a second switching means for switching to the second connecting means when the power is turned off. 3. Input means for inputting image data, storage means for storing the image data input by the input means, output means for performing an output process based on the image data stored by the storage means, and the input. In the image processing system, including a storage unit, the storage unit, and a control unit that controls the output unit, the storage unit electrically connects the communication control unit to at least two of the plurality of devices. Means, a second connecting means for electrically connecting at least two of the plurality of devices without going through the communication control means, and a first connecting means for switching to the first connecting means when the power is turned on. An image processing system comprising: a switching unit; and a second switching unit that switches to the second connecting unit when the power is turned off.