JPH06260528A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH06260528A JPH06260528A JP5044265A JP4426593A JPH06260528A JP H06260528 A JPH06260528 A JP H06260528A JP 5044265 A JP5044265 A JP 5044265A JP 4426593 A JP4426593 A JP 4426593A JP H06260528 A JPH06260528 A JP H06260528A
- Authority
- JP
- Japan
- Prior art keywords
- metal pad
- wire bonding
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にワイヤボンディング用メタルパッドに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a metal pad for wire bonding.
【０００２】[0002]
【従来の技術】従来、この種のワイヤボンディングメタ
ルパッドの構成は、図３（ａ），（ｂ）に示すように、
正方形のワイヤボンディング用メタルパッド１０２と、
上層に形成した保護絶縁膜１０３を、メタルパッド１０
２の内側部分を正方形形状に除去して作った保護絶縁膜
開口部１０１からなっており、この、保護絶縁膜開口部
１０１に、図３（ｃ），（ｄ）のようにワイヤボンディ
ングを行っていた。2. Description of the Related Art Conventionally, the structure of this type of wire bonding metal pad is as shown in FIGS. 3 (a) and 3 (b).
A square wire bonding metal pad 102,
The protective insulating film 103 formed on the upper layer is replaced with the metal pad 10
2 includes a protective insulating film opening portion 101 formed by removing the inner portion of the protective film 2 into a square shape, and wire bonding is performed to the protective insulating film opening portion 101 as shown in FIGS. 3C and 3D. Was there.
【発明が解決しようとする課題】モールドパッケージの
樹脂封止の組立では、気密性が悪く、耐湿性が弱いた
め、図３（ｃ）のワイヤボンディング用メタルパッド１
０２のワイヤボンディング接合部分１０５と保護絶縁膜
１０３との間のメタルパッド露出部分１０７が酸化され
て最悪の場合は、断線して、不良品となってしまうとい
う欠点があった。In the resin package assembly of the mold package, since the airtightness is poor and the moisture resistance is weak, the wire bonding metal pad 1 of FIG. 3C is used.
In the worst case, the metal pad exposed portion 107 between the wire bonding joint portion 105 of No. 02 and the protective insulating film 103 is oxidized, and in the worst case, there is a defect that the wire is broken and becomes a defective product.
【０００３】本発明の目的は、上述の欠点を解決し、モ
ールドパッケージでの耐湿性を向上させることの出来る
半導体集積回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device which can solve the above-mentioned drawbacks and can improve the moisture resistance of a mold package.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体集積回路
装置は、ワイヤボンディング用メタルパッドの上層保護
絶縁膜が、ワイヤボンディング時のボンディング接合部
分と同じ大きさの円形の開口部を有している。In a semiconductor integrated circuit device according to the present invention, an upper protective insulating film of a metal pad for wire bonding has a circular opening having the same size as a bonding joint portion at the time of wire bonding. There is.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の一実施例の半導体集積回路装置の
側面図および上面図で、分図（ａ）は素子の側面図，分
図（ｂ）は上面図，分図（ｃ）はワイヤボンディングを
行ったときの素子の側面図，分図（ｄ）はその上面図で
ある。The present invention will be described below with reference to the drawings. 1A and 1B are a side view and a top view of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 1A is a side view of an element, FIG. 1B is a top view, and FIG. 1C is a wire. A side view of the element when bonding is performed, and a partial view (d) is a top view thereof.
【０００６】分図（ａ），（ｂ）のように正方形のワイ
ヤボンディング用メタルパッド１０２の上層に形成され
た保護絶縁膜開口部１０１が、分図（ｃ）のようにワイ
ヤボンディング接合部１０５と同じ大きさの円形で形づ
くられている。その保護絶縁膜開口部１０１にワイヤボ
ンディングを行ったのが、分図（ｃ），（ｄ）でありこ
れによりボンディング用メタルパッドの露出部分が無く
なり、よって、メタルパッドの酸化が無くなり耐湿性が
向上する。The protective insulating film opening 101 formed in the upper layer of the square wire-bonding metal pad 102 as shown in the drawings (a) and (b) has a wire bonding joint portion 105 as shown in the drawings (c). It is shaped like a circle with the same size as. Wire-bonding was performed to the protective insulating film opening 101 as shown in FIGS. 3C and 3D. As a result, the exposed portion of the metal pad for bonding was eliminated, so that oxidation of the metal pad was eliminated and moisture resistance was improved. improves.
【０００７】次に第２の実施例について説明する。図２
は本発明の他の実施例の半導体集積回路装置の側面図お
よび平面図で、分図（ａ）は半導体集積回路装置の側面
図，分図（ｂ）はその上面図，分図（ｃ）はワイヤボン
ディングを行ったときの側面図，分図（ｄ）はその平面
図である。分図（ａ），（ｂ）は、円形のワイヤボンデ
ィング用メタルパッド１０２に円形の保護絶縁膜開口部
１０１を有している場合で、このときも分図（ｃ），
（ｄ）のようにワイヤボンディングを行ったときも、第
１の実施例と同じようにボンディング用メタルパッドの
露出部分が無くなる。よって、メタルパッドの酸化が無
くなり耐湿性が向上する。したがってモールドパッケー
ジでの耐湿性による断線不良な無くなる。この第２の実
施例ではワイヤボンディング用メタルパッドが円形のた
め保護絶縁膜開口部近傍の歪を少なくすることができ、
かつボンディングパットの面積を縮小することができる
特徴がある。Next, a second embodiment will be described. Figure 2
Is a side view and a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, where (a) is a side view of the semiconductor integrated circuit device, (b) is a top view thereof and (c) is a side view thereof. Is a side view when wire bonding is performed, and FIG. The diagrams (a) and (b) show the case where the circular wire bonding metal pad 102 has the circular protective insulating film opening 101.
When wire bonding is performed as shown in (d), the exposed portion of the bonding metal pad is eliminated as in the first embodiment. Therefore, the oxidation of the metal pad is eliminated and the moisture resistance is improved. Therefore, disconnection failure due to moisture resistance in the mold package is eliminated. In the second embodiment, since the wire bonding metal pad is circular, distortion in the vicinity of the protective insulating film opening can be reduced,
Moreover, there is a feature that the area of the bonding pad can be reduced.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、ワイヤボ
ンディング用メタルパッドの上層の保護絶縁膜が、ワイ
ヤボンディグ時のボンディング接合部分と同じ大きさ
の、円形の開口部を有している。これにより、ワイヤボ
ンディング時のメタルパッドの露出部分が無くなり、酸
化によるメタルパッドの断線が無くなる。またモールド
パッケージでの耐湿性をパッケージの変更をすることな
く、向上させることが出来る。As described above, according to the present invention, the protective insulating film in the upper layer of the wire bonding metal pad has a circular opening having the same size as the bonding joint portion at the time of wire bonding. . As a result, the exposed portion of the metal pad during wire bonding is eliminated, and disconnection of the metal pad due to oxidation is eliminated. Further, the moisture resistance of the mold package can be improved without changing the package.
【図１】本発明の一実施例の半導体集積回路装置の側面
図およびその上面図であり、分図（ａ）は半導体集積回
路装置の側面図，分図（ｂ）はその上面図，分図（ｃ）
はワイヤボンディングを行ったときの側面図，分図
（ｄ）はその上面図である。1A and 1B are a side view and a top view of a semiconductor integrated circuit device according to an embodiment of the present invention, where FIG. 1A is a side view of the semiconductor integrated circuit device, and FIG. Figure (c)
Is a side view when wire bonding is performed, and FIG.
【図２】本発明の他の実施例の半導体集積回路装置の側
面図およびその上面図で、分図（ａ）は半導体集積回路
装置の側面図，分図（ｂ）はその上面図，分図（ｃ）は
ワイヤボンディングを行ったときの側面図，分図（ｄ）
はその上面図である。2A and 2B are a side view and a top view of a semiconductor integrated circuit device according to another embodiment of the present invention, where FIG. 2A is a side view of the semiconductor integrated circuit device, and FIG. 2B is a top view of the same. Figure (c) is a side view of wire bonding, and a partial view (d).
Is a top view thereof.
【図３】従来の半導体集積回路装置の一例の側面図およ
びその上面図で、分図（ａ）は半導体集積回路の側面
図，分図（ｂ）はその上面図，分図（ｃ）はワイヤボン
ディングを行ったときの側面図，分図（ｄ）はその上面
図である。3A and 3B are a side view and a top view of an example of a conventional semiconductor integrated circuit device, in which FIG. 3A is a side view of the semiconductor integrated circuit, FIG. 3B is a top view thereof, and FIG. A side view when wire bonding is performed, and a partial view (d) is a top view thereof.
１０１ 保護絶縁膜開口部 １０２ ワイヤボンディング用メタルパッド １０３ 保護絶縁膜 １０４ シリコン基板 １０５ ワイヤボンディング接合部分 １０６ ボンディングワイヤ １０７ メタルパッド露出部分 101 Protective Insulating Film Opening 102 Wire Bonding Metal Pad 103 Protective Insulating Film 104 Silicon Substrate 105 Wire Bonding Joint 106 Bonding Wire 107 Metal Pad Exposed
Claims (2)
層の保護絶縁膜が、ワイヤボンディング時のボンディン
グ接合部分と同じ大きさの、円形の開口部を有すること
を特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device characterized in that a protective insulating film on an upper layer of a metal pad for wire bonding has a circular opening having the same size as a bonding joint portion at the time of wire bonding.
形に形成されていることを特徴とする請求項１記載の半
導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the wire bonding metal pad is formed in a circular shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5044265A JPH06260528A (en) | 1993-03-05 | 1993-03-05 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5044265A JPH06260528A (en) | 1993-03-05 | 1993-03-05 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06260528A true JPH06260528A (en) | 1994-09-16 |
Family
ID=12686684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5044265A Pending JPH06260528A (en) | 1993-03-05 | 1993-03-05 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06260528A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8482002B2 (en) | 2009-01-20 | 2013-07-09 | Samsung Electronics Co., Ltd. | Semiconductor device including bonding pads and semiconductor package including the semiconductor device |
-
1993
- 1993-03-05 JP JP5044265A patent/JPH06260528A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8482002B2 (en) | 2009-01-20 | 2013-07-09 | Samsung Electronics Co., Ltd. | Semiconductor device including bonding pads and semiconductor package including the semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990302 |