JPH06259957A - Memory device - Google Patents

Abstract

PURPOSE:To attain a low power consumption, a high density, and a high speed by providing a line/column driving circuit driving a memory matrix according to line/column information and erasing information by an erasing circuit. CONSTITUTION:The write-in electrode 15 of a memory cell 10 is connected to a driving wire 21, and an electrode 16 is connected to a driving wire 31 at each intersection of matrices consisting of three line driving wires 21 and three column driving wires 31. And, a line write-in switch 22 is connected to the line driving wire 21, a write-in power supply 23 is connected to one terminal of the switch 22 to constitute a line driving circuit 2. Also, a column write-in switch 32 is connected to a column driving wire 31, and one terminal of the switch 32 is grounded to constitute a column driving circuit 3. An erasing cell 41 is connected to a driving wire 31, one terminal of the cell 41 is connected to an erasing power supply 43 through a line erasing switch 42. Further, a column erasing switch 44 is connected to the driving wire 31 to constitute an erasing circuit 4. Hereuopn, when erasing the information of the circuits 2 and 3 by the circuit 4, a low power consumption, a high density, and a high speed can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for storing information, and more particularly to a flash EEPROM (batch erasing type electrically erasable and writable read-only memory) which is easier to use and has a higher density. For technology.

[0002]

2. Description of the Related Art Memory plays an extremely important role in electronic computers. In particular, the Neumann-type computer currently put into practical use has a program built-in system, and therefore the performance of the main memory for storing operation instructions and data determines the performance itself of the computer. On the other hand, in the external storage other than the main storage, since the unit price per bit is a problem rather than the performance, it is the mainstream to use a magnetic memory such as a hard disk or a floppy disk.

However, recently, there is a tendency to use a flash EEPROM for this external storage because of its power consumption being 1/10 of that of a magnetic memory, good earthquake resistance, and light weight.

FIG. 8 shows a flash E which has been conventionally used.
It is a figure which shows the typical structure of EPROM. This flash EEPROM 100 basically has a structure having a floating gate 106 between a control gate 102 of a MOS (metal oxide semiconductor) transistor and a silicon substrate 104. The floating gate 106 is surrounded by the SiO ₂ film 108 and is completely insulated from the outside. Therefore, the charges injected into the floating gate 106 in the writing operation described later do not escape to the outside even after the power is turned off, and serve as a nonvolatile memory.

That is, the signal writing operation is performed by the drain 11
The phenomenon that hot electrons generated by applying a high voltage between 0 and the source 112 are injected into the floating gate 106 over the barrier of the SiO ₂ film 108 is used. Whether or not charges are injected into the floating gate 106 is detected by observing a current (channel current) between the drain 110 and the source 112 which is modulated by the electric field. Furthermore, when erasing a signal, the floating gate 106 and the erase gate 11
By applying a high voltage during the period 4, electric charges are extracted from the floating gate 106 by field emission.

As another modification, hot electrons are not used for signal writing, and charges are directly injected from the silicon wafer 104 into the floating gate 106 by the Fowler-Nordheim (FN) tunnel phenomenon, or as the signal erasing method, the erasing gate 114 is used. Drain 11 directly from floating gate 106 without using
There is one in which the electric charge is drawn out by field emission.

[0007]

As described above, in the conventional flash EEPROM, hot electron or Fowler-Nordheim (FN) current is used in the signal writing and erasing operations.

However, in order to generate hot electrons, it is necessary to flow a large amount of current through the channel of the MOS transistor. Therefore, power consumption increases and usage conditions are limited. In addition, since a large amount of heat is generated, the densification of the device is limited, and in addition, a large number of cells cannot be written at the same time, which slows the signal writing speed.

On the other hand, when the FN current is used, a high voltage such as 10 to 20 V is required as an operating voltage. Therefore, a voltage other than the TTL level (5 V) is externally supplied or a booster circuit is provided in the chip. It is necessary to provide. Therefore, there arises a problem that the circuit is complicated or the usage is complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a memory device used as a flash EEPROM which realizes low power consumption, high density, high speed, and low voltage. To aim.

[0011]

In order to achieve the above object, a memory device according to the present invention includes a ferroelectric capacitor 11 (see (A) and (B) of FIG. 1, The same shall apply hereinafter), a load capacitor 12 composed of a dielectric material connected in series to the ferroelectric capacitor 11, a resistance element 13 connected in parallel to the load capacitor 12, and the ferroelectric capacitor 11 or the load capacitor 12 described above. Conduction is controlled by the voltage of the ferroelectric capacitor 11 or the load capacitor 1
Switching element 1 for reading information stored in 2
A memory cell matrix 1 configured by arranging a plurality of memory cells 10 each composed of 4 in a matrix form, a row drive circuit 2 for driving the memory matrix 1 based on row information, and the memory matrix 1 based on column information. A column driving circuit 3 for driving and an erasing circuit 4 for erasing the information stored in the memory matrix 1 are provided.

[0012]

That is, according to the memory device of the present invention, as shown in FIG. 1A, the memory cell matrix 1, the row driving circuit 2, the column driving circuit 3, and the erasing circuit 4 are classified into four groups.
A flash EEPROM consisting of three blocks is provided. Each memory cell 10 forming the memory cell matrix 1 is conceptually shown as in FIG. That is, a ferroelectric capacitor 11 having a structure in which a ferroelectric substance is sandwiched between two electrodes and a load capacitor 12 having a structure in which a paraelectric substance is sandwiched between two electrodes are connected in series, and a resistor is connected in parallel with the load capacitor 12. It comprises a memory circuit to which the element 13 is connected, and a read transistor 14 whose conduction state is controlled by applying the voltage of the ferroelectric capacitor 11 to the gate.

When a rectangular voltage pulse is applied between the first write electrode 15 and the second write electrode 16 of the memory circuit, only the spontaneous polarization remains in the ferroelectric capacitor 11. Since it does not discharge for a long time, it can be used as non-volatile memory information. Regarding the polarization mechanism, Japanese Patent Application No.
Since it has already been filed as 324449, it will not be mentioned here.

Whether or not information is stored in the memory circuit, that is, whether or not a voltage is generated in the ferroelectric capacitor 11, the first read electrode 17 and the first read electrode 17 of the read transistor 14 whose conduction state is controlled by the voltage. It is determined by observing the conductivity between the two readout electrodes 18.

At the time of writing, a write voltage based on column information is applied from the column drive circuit 3 to the first write electrode 15 provided in each memory cell 10 of the memory cell matrix 1, and row drive circuit 2 outputs row information. Based on the writing voltage, the second writing electrode 16 is applied. Further, at the time of reading, the read voltage based on the column information is applied from the column drive circuit 3 to the first read electrode 17, and the read voltage based on the row information from the row drive circuit 2 is applied to the second read electrode 18.
Apply to. Further, at the time of erasing, the erasing circuit 4 stores the voltage between the first writing electrode 15 and the second writing electrode 16 of each memory cell 10 by applying a voltage having a polarity opposite to that of the writing operation. Erase information.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (First embodiment)

FIG. 2 is a diagram showing a circuit configuration of the first embodiment of the present invention. Memory cell 10 for storing information
Has the structure shown in FIG. 1B, but is omitted in this figure for simplification of the figure. In this embodiment, this memory cell 10 is used to make a 3 × 3 type memory matrix 1
Are configured.

That is, the first write electrode 15 of the memory cell 10 is connected to the row drive line 21 at each intersection of the matrix composed of the three row drive lines 21 and the three column drive lines 31.
The second write electrode 16 is connected to the column drive line 31. A row write switch 22 is connected to each row drive line 21, and a write power supply 23 is connected to one terminal of the row write switch 22 to form the row drive circuit 2. Similarly, each column drive line 3
A column write switch 32 is connected to 1 and one terminal of the column write switch 32 is grounded to form a column drive circuit 3. An erase cell 41 is connected to each column drive line 31, and one terminal of the erase cell 41 is connected to an erase power supply 43 via a row erase switch 42. In addition, each column drive line 31 is connected to a column. The erase switch 44 is connected, and the column erase switch 4 is further connected.
The erasing circuit 4 is configured by grounding one terminal of the four. Here, in order to simplify the drawing, the drive line for reading information is omitted. Further, the column write switch 32 and the column erase switch 44 may be used together with the same switch element.

In such a configuration, each memory cell 10
When writing information to the column, the row write switch 22 is opened / closed based on the row information, and the column write switch 32 is opened / closed based on the column information. At this time, the non-selected memory cell 10
Is applied with a maximum of 1/2 of the write voltage applied to the selected memory cell 10. However, at this time, due to the non-linear response of the ferroelectric capacitor 11, writing of information to the non-selected memory cell, that is, crosstalk does not occur.

On the other hand, when erasing the written information, the column erasing switch 44 is opened / closed based on the column erasing information,
At the same time, the row erase switch 42 is closed. As a result, the same voltage as that of the erase power source 43 is applied to the selected erase cell 41, and the same column drive line 31 as that of the selected erase cell 41 is applied.
1/2 of the voltage is applied to the memory cell 10 connected to
Is applied. This means that the row erasing switch 42 and the column erasing switch 44 are not limited to the erasing cell 41, but the row driving line 21,
Since the memory cell 10 and the column drive line 31 are connected to each other, the so-called crosstalk principle is applied. Therefore, if the voltage of the erase power supply 43 is set to be twice that of the write power supply 23 and the polarity of the voltage applied to the memory cell 10 at the time of erase is set to be opposite to the polarity at the time of write, The written information can be collectively erased in column units. The current required to erase the information in each memory cell 10 is only used for discharging the ferroelectric capacitor 11 and is extremely small. Therefore,
It is also possible to close all the column erase switches 44 to erase the information in all the memory cells 10 at the same time.

Although the erase cell 41 is shown as a capacitor in FIG. 2, this is not the only memory cell 1.
A circuit equivalent to 0, a resistance element, or a reactance element can be substituted. As described above, according to the present embodiment, it is possible to suppress the power consumption and the heat generation amount when collectively erasing memory information at a very low level. (Second embodiment)

FIG. 3 is a diagram showing the circuit configuration of the second embodiment of the present invention. The memory cell 50 for storing information has a structure as shown in FIGS. 4 and 5, but is omitted for simplification of the drawing.

FIG. 4 shows a built-in structure of the memory cell 50. Basically, the gate insulating film of the MOS transistor is composed of a laminated body of the ferroelectric substance 51 and the polysilicon 52. However, the ferroelectric 51 and the silicon wafer 5
In order to prevent the switching voltage of the transistor from shifting due to the formation of an interface layer at the interface with the transistor 3, that is, the channel portion of the transistor, an oxide film 54 made of SiO2 is provided between the ferroelectric substance 51 and the silicon wafer 53. Has been formed.

FIG. 5 is a rewriting of the structure of FIG. 4 into an electrically equivalent circuit. The polysilicon 52 is considered to be a parallel connection of the load capacitor 55 and the resistance element 56, and the ferroelectric capacitor 57 is connected in series to the polysilicon 52, and the other terminal of the ferroelectric capacitor 57 is connected to the gate portion of the memory transistor 58. Has been done.

In order to store information in the memory cell 50 having such a structure, a voltage is applied between the drain 59 and the source 60 to make the channel of the memory transistor 58 conductive, and to apply a voltage to the gate 61. Apply. As a result, the load capacitor 55, the resistance element 5
A voltage can be applied to the memory circuit comprising 6 and the ferroelectric capacitor 57. As a result, as in the case of the memory cell 10 ((B) of FIG. 1), only the spontaneous polarization can remain in the ferroelectric capacitor 57. Whether or not information is stored in the memory circuit, that is, whether or not a voltage is generated in the ferroelectric capacitor 57 is determined between the drain 59 and the source 60 of the memory cell transistor 58 whose conduction state is controlled by the voltage. It is determined by observing the conductivity of.

In the second embodiment, such a memory cell 50 is used to form a 3 × 3 type memory matrix. That is, as shown in FIG. 3, three row drive lines 21 and 3 are provided.
At each intersection of the matrix of column drive lines 31 of the book, the drain 57 of the memory cell 50 is connected to the row drive line 21,
Further, the gate 59 is connected to the column drive line 31. Further, in all the memory cells 50, the source 58 is grounded. A row control switch 24 is connected to each row drive line 21, and a row control power supply 25 is connected to one terminal of the row control switch 24 to configure the row drive circuit 2. Similarly, a column control switch 33 is connected to each column drive line 31, and one terminal of the column control switch 33 is connected to a column control power supply 34 to form the column drive circuit 3. All the column drive lines 31 are connected to the erase switch 45, and one terminal of the erase switch 45 is connected to the erase power source 43,
The erase circuit 4 is configured by connecting one terminal of the erase power source 43 to the substrate.

In such a configuration, each memory cell 5
When writing information to 0, the row control switch 24 is opened / closed based on the row information, and the column control switch 33 is opened / closed based on the column information. At this time, since only the channel of the memory transistor 58 of the memory cell 50 at the intersection of the selected row drive line 21 and the selected column drive line 31 becomes conductive, information writing to the non-selected memory cell 50, That is, crosstalk does not occur.

On the other hand, when erasing the written information, the erasing switch 45 is closed. As a result, the voltage of the erase power supply 43 is applied between the gate 61 and the substrate in all the memory cells 50. When the polarity of the erase power supply 43 is set such that the voltage applied to the ferroelectric capacitor 57 during the write operation and the voltage applied during the erase operation are opposite to each other, the ferroelectric capacitor The polarization charge written in 57 is extracted through the substrate and erased.

The current required to erase the information in each memory cell 50 is only used for discharging the ferroelectric capacitor 57, and is very small. Therefore, by closing one erase switch 45, all memory cells 5
It is possible to erase 0 information at the same time.

Further, according to the present embodiment, as shown in FIG. 4, the memory circuit portion composed of the ferroelectric substance 51 and the polysilicon 52 is formed on the channel portion of the memory transistor 58. Therefore, the area occupied by the element is extremely small. In addition, the row drive line 21 and the column drive line 31 are
Since it is shared during the writing of information and the reading of information, it is possible to reduce the number of address lines, which also causes a further increase in density. (Third embodiment)

FIG. 6 is a diagram showing the circuit configuration of the third embodiment of the present invention. A memory cell 50 for storing information constitutes a 3 × 3 type memory matrix 1. Here, the memory cell 50 is the same as that of the second embodiment described above.
It has a structure as shown in FIGS.

The gates 61 of the memory cells 50 arranged in the same row are commonly connected and are also connected to the row control switch 24. One contact of all row control switches 24 is connected to the first row control power supply 25A, and the other contact is connected to the second row control power supply 25B, thereby configuring the row drive circuit 2. . Further, the memory cells 50 arranged in the same column have their sources 60 and drains 59 connected to each other. Memory cell 50 at the top of each column
59 is connected to the column control switch 33. One contact of all the column control switches 33 is connected to the column control power supply 34, and the other contacts are grounded via the first erasing switch 45A to form the column drive circuit 3. Further, all the gates 61 are connected to the erasing power source 43 via the second erasing switch 45B, and the other terminal of the erasing power source 43 is connected to the substrate to form the erasing circuit 4. The source 60 of the memory cell 50 at the bottom of each column is the third erase switch 4
It is grounded via 5C.

In such a configuration, each memory cell 5
When writing information to 0, only the column control switch 33 of the selected column is tilted to the column control power supply 34 side, the other column control switches 33 are tilted to the first erase switch 45A side, and the first erase switch Keep 45A closed. Further, only the row control switch 24 of the selected row is tilted to the second row control power supply 25B side, and the other row control switches 24 are tilted to the first row control power supply 25A side. Further, the third erasing switch 45C is closed and the second erasing switch 45B is opened. Here, the voltage of the first row control power supply 25A and the voltage of the column control power supply 34 are equal to each other and are set to about ½ of the voltage of the second row control power supply 25B. As a result, in the selected memory cell 50, approximately the second row control power supply 25B is provided between the gate 61 and the channel of the memory transistor 58.
And a voltage of the column control power supply 34 are applied to write information. On the other hand, in the non-selected memory cell 50, no voltage is applied between the gate 61 and the channel of the memory transistor 58, and no information is written.

When erasing the written information, all the column control switches 33 are set to the first erasing switch 45.
It is tilted to the A side, the first erasing switch 45A is opened, and the third erasing switch 45C is opened. That is, the drain 59 of the memory cell 50 in the uppermost row and the source 60 of the memory cell 50 in the lowermost row are left floating and the second erase switch 45B is closed. As a result, the voltage of the erase power supply 43 is applied between the gate 61 and the substrate in all the memory cells 50. At this time, if the erase power source 43 is set so that the polarity of the voltage applied to the ferroelectric capacitor 57 is opposite to the polarity at the time of writing, all the stored information is erased at the same time.

According to the structure of this embodiment, there is no column drive line used in other embodiments, and there is no data input / output contact. As a result, the occupied area per bit is as close as possible to the original occupied area of the memory transistor 58, and the ultimate high density can be achieved. (Fourth embodiment)

FIG. 7 is a diagram showing another built-in structure of the memory circuit portion including the load capacitor 55, the resistance element 56 and the ferroelectric capacitor 57 in the memory cell 50 of FIG.

The ferroelectric composition region 72 and the paraelectric composition region 73 formed on the substrate 71 are manufactured by the same process, but their chemical compositions are changed by changing the manufacturing conditions on the way. .

For example, PZT, which is known as a typical ferroelectric substance, is a solid solution of PbZrO ₃ and PbTiO ₃ , and usually the maximum ferroelectricity is exhibited when the composition of both is around 50:50. On the other hand, if either composition is excessively increased, the ferroelectricity disappears and a paraelectric material having leakage resistance is obtained. This compositional change can be achieved by changing the fabrication conditions during the process. For example, in the commonly used sputtering method, a large composition change occurs by changing the pressure of the sputtering gas, the mixing ratio of the oxygen gas, the high frequency power, or the substrate temperature.

In this embodiment, a memory circuit can be manufactured using a single raw material and by the same process.
Therefore, a significant price reduction can be realized along with the reduction in the number of processes. In addition, the adhesion of dust and the like generated during the process transition can be reduced, and improvement of product fractionation can be expected. The memory circuit manufactured in the fourth embodiment can of course be used in other embodiments, and similar effects can be expected.

[0040]

As described in detail above, according to the present invention,
It is possible to provide a memory device used as a flash EEPROM that realizes low power consumption, high density, high speed, and low voltage.

That is, since the current flowing when writing and erasing information is used only for charging and discharging the ferroelectric capacitor, the power consumption is extremely low. Along with this, the amount of heat generated can be suppressed as much as possible, which facilitates high density. Further, there is an advantage that writing speed is increased by simultaneously writing information in a plurality of memory cells, or that batch erasing is possible.

In addition, since the voltage required to invert the spontaneous polarization in the ferroelectric capacitor is as low as 1 to 3 V, it is not necessary to provide a high voltage power source or a high voltage booster circuit, and the circuit configuration can be improved. It is easy to simplify.

[Brief description of drawings]

1A is a block configuration diagram of a memory device of the present invention, and FIG. 1B is a circuit configuration diagram of a memory cell used in a first embodiment.

FIG. 2 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a built-in structure of a memory cell used in a second embodiment.

FIG. 5 is an electrical equivalent circuit diagram of a memory cell used in the second embodiment.

FIG. 6 is a diagram showing a circuit configuration of a third exemplary embodiment of the present invention.

7 is a load capacitor in the memory cell of FIG.
It is a figure which shows another built-in structure of the memory circuit part which consists of a resistance element and a ferroelectric capacitor.

FIG. 8 is a diagram showing a typical structure of a conventional flash EEPROM.

[Explanation of symbols]

1 ... Memory cell matrix, 2 ... Row drive circuit, 3 ... Column drive circuit, 4 ... Erase circuit, 10,50 ... Memory cell, 1
1, 57 ... Ferroelectric capacitor, 12, 55 ... Load capacitor, 13, 56 ... Resistor element, 14 ... Switching element, 15 ... First write electrode, 16 ... Second write electrode, 17 ... First read electrode, 18 ... second read electrode, 21 ... row drive line, 22 ... row write switch, 23
... write power supply, 24 ... row control switch, 25 ... row control power supply, 25A ... first row control power supply, 25B ... second row control power supply, 31 ... column drive line, 32 ... column write switch, 33
... column control switch, 34 ... column control power supply, 41 ... erase cell, 42 ... row erase switch, 43 ... erase power supply, 44 ... column erase switch, 45 ... erase switch, 45A ... first erase switch, 45B ... second erase Switch, 45C ... Third erase switch, 51 ... Ferroelectric material, 52 ... Polysilicon, 5
3 ... Silicon wafer, 54 ... Oxide film, 58 ... Memory transistor, 59 ... Drain, 60 ... Source, 61 ... Gate, 71 ... Substrate, 72 ... Ferroelectric composition region, 73 ... Paraelectric composition region.

Claims (1)

[Claims] 1. A ferroelectric capacitor composed of a ferroelectric material, a load capacitor composed of a dielectric material connected in series to the ferroelectric capacitor, and a resistance element connected in parallel to the load capacitor. A plurality of memory cells are arranged in a matrix form and each of which is constituted by a switching element for controlling conduction by the voltage of the ferroelectric capacitor or the load capacitor and reading information stored in the ferroelectric capacitor or the load capacitor. A memory cell matrix, a row drive circuit that drives the memory matrix based on row information, a column drive circuit that drives the memory matrix based on column information, and an erase that erases information stored in the memory matrix. A memory device comprising: a circuit.