JPH06259034A - Method for displaying halftone image in display pannel - Google Patents

Abstract

PURPOSE:To prevent a contrast ratio from lowering even in a dark picture with a small APL(average picture level) and to reduce a difference in power consumption when the APL is large or small. CONSTITUTION:In a method of dividing one field display interval for every pixel to sub-field intervals with the number N of bits of display gradation, and weighting to the number of display pulses in respective sub-field intervals and displaying a halftone image, the brightness of the display image is divided into three stages according to the value of the APL, and the number N is switched according to the stage of the brightness of the display image so that the more the display image becomes bright, the more the number of display gradation is increased. When the APL is <10%, a signal for eight bits gradation whose maximum display number of pulse is 512, is level-converted to the signal for six bits gradation whose luminance is large and whose maximum display number of pulse is 896 as shown by conversion pattern (1) in the figure, and when 10%<=APL<25%, the signal for eight bits gradation is level-converted to the signal for seven bits gradation whose maximum display number of pulse is 640 as shown by conversion pattern (2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel such as a plasma display panel (hereinafter simply referred to as PDP) or a liquid crystal display panel (hereinafter simply referred to as LCD) for one pixel display period for each pixel ( For example, one field display period or one frame display period) is time-divided into a display period (for example, a subfield period) having the number of bits N (N is an integer of 2 or more) corresponding to the display gradation, and the display pulse of each divided display period is displayed. The present invention relates to a method of displaying a halftone image of a video signal by weighting a number corresponding to each bit.

[0002]

2. Description of the Related Art Conventionally, in this type of halftone image display method, there are 605 to 6 of JAPAN DISPLAY '92.
By 08, "S16-2 A Full Color
AC Plasma with 256 Gray S
The method described as "calle" was known.

That is, in the case of displaying halftones with 8 bits and 256 gradations, as shown in FIGS. 3A and 3B, one field display period 1F for each pixel (for example, about 16. 6 ms) for 8 subfield periods SF1
To SF8, each subfield period SF1,
..., SF8 is further time-divided into an address period AP and a display period SP, and 1: 2: 4: 8: ...: 1 in this display period SP.
Weigh 28 ratios.

For example, if two display pulses are assigned to the display period SP of the subfield period SF1, eight display pulses are assigned to the display period SP of the subfield periods SF3 and SF8.
(= 2 × 4) and 256 (= 2 × 128) display pulses are assigned. Further, the address period AP is constant (for example, 1.
5 ms) depending on the display panel and consists of steps 1, 2, 3, and 4.

In the period of step 1, in order to eliminate the influence of the immediately preceding display period and bring all the discharge dots into the same state, the dot matrix type PDP X Sustai is used.
An erase pulse is applied to the n-electrode. In the period of step 2, the X Sustain electrode of the PDP and Y1, Y
2, ..., A write pulse is applied between the Y480 Sustain electrodes, and some of the ions are stacked on the surface of the phosphor by the address electrodes maintained at 0V. In the period of step 3, XSus is used to remove the wall charge.
An erase pulse is applied to the tain electrode. In the period of step 4, a scan pulse is applied to the address electrode of the PDP.

[0006]

However, in the above-described conventional halftone image display method, if the number of subfield periods that are time-divided in order to increase the display gradation is increased, the address period AP is increased accordingly. The number increases and the display period SP decreases (the number of display pulses decreases),
The maximum value of display brightness decreases.

For this reason, on a dark screen where the APL (average picture level) of the video signal is small, there is a problem that the contrast ratio is lowered and the display image quality is deteriorated. In the display panel (for example, PDP), APL
There is a problem in that the difference in power consumption between when the power consumption is large and when the power consumption is small is large, and the load on the power source is large.

The present invention has been made in view of the above problems, and it is possible to prevent the contrast ratio from being lowered and improve the display image quality even in a dark screen where the APL of a video signal is small, so that the APL is large. An object of the present invention is to provide a method for displaying a halftone image on a display panel, which can reduce the difference in power consumption between the time and the time when it is small.

[0009]

According to the present invention, one screen display period for each pixel of a display panel is time-divided into a display period having a bit number N (N is an integer of 2 or more) corresponding to a display gradation, In the method of displaying a halftone image of a video signal by weighting the number of display pulses in each divided display period corresponding to each bit, the AP of the video signal
By comparing L (average video level) with the set level, the brightness of the display image is divided into m levels (m is an integer of 2 or more), and the brighter the display image, the greater the number of display gradations. In addition, the number of the division number N is switched according to the brightness level of the display image to display the halftone image.

[0010]

By comparing the APL of the video signal with the set level, the brightness of the displayed image can be m steps (for example, 3 steps).
It is divided into. The number of divisions (for example, the number of subfields) N of one screen display period (for example, one field display period) N is corresponding to the brightness of the divided m-stage display image, the brighter the display image is. For example, N ₁ (for example 6), N ₂ (for example 7), N so that the display gradation increases (for example, the display gradation becomes 64, 128, 256).
_It is switched to ₃ (for example, 8).

Therefore, in a dark screen with a small APL, the number of divisions (for example, the number of subfields) N is switched in the direction of decreasing (for example, from 8 to 6), so that the number of address periods AP is reduced. The display period becomes long (the number of display pulses increases), the maximum value of display brightness does not decrease, and the contrast ratio does not decrease.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a halftone image display method according to the present invention will be described below with reference to FIGS. FIG. 1 shows a schematic structure of a main part of an apparatus for carrying out the method of the present invention. In FIG. 1A, R, G and B signals represent 8-bit gradation (256 gradations) digital signals of red, green and blue as video signals. Reference numeral 10 denotes a γ correction / level conversion circuit. The γ correction / level conversion circuit 10 is configured to perform γ correction and level conversion of R, G, B signals based on a control signal from a control circuit 20 described later. Has been done.

A field memory 12, a PDP driver 14 and a dot matrix type PDP 16 as an example of a display panel are sequentially coupled to the output side of the γ correction / level conversion circuit 10. The Y signal is a luminance signal, and the luminance signal Y is created based on, for example, R, G, B signals. Reference numeral 18 denotes an integrating circuit, which is configured to output an APL (average video level) by integrating the Y signal.

Reference numeral 20 is a control circuit.
By comparing the APL from the integrator circuit 18 with a preset level, the brightness of the display image is roughly divided into three levels, and the corresponding control signals are output to the display timing signal output circuit 22 described later. In addition, each of these three stages is further divided into three stages, and the corresponding control signals l, m, h, l, m, h,
It is configured to output l, m, and h to the γ correction / level conversion circuit 10.

That is, the control circuit 20 controls the APL from the integrating circuit 18 to be low (for example, less than 3.5%), medium (for example, 3.5% or more and less than 7%) within a range of less than 10%, When it is high (for example, 7% or more and less than 10%), the control signals l, m, and h are output, and 10% or more and 2
The control signals l, m, and m are respectively low (for example, 10% or more and less than 15%), medium (for example, 15% or more and less than 20%), and high (for example, 20% or more and less than 25%) within a range of less than 5%. h is output, and low (for example, 25% or more and less than 50%) within a range of 25% or more, medium (for example, 50% or more and 7)
When it is less than 5%) and high (for example, 75% or more), the control signals l, m, and h are output.

Then, the γ correction / level conversion circuit 10
Are control signals l, m, h from the control circuit 20.
Based on the conversion pattern l, m,
As shown in h, R, G, and
The B signal is γ-corrected (correction of non-linearity of brightness), and the level is converted into R, G, and B signals for 6-bit gradation and output.

The gamma correction / level conversion circuit 10 is also provided.
Are control signals l, m, h from the control circuit 20.
Alternatively, based on the control signals l, m, h, the conversion pattern l, m, h or l of FIG.
As shown in m and h, the input R for 8-bit gradation,
G-correction of G and B signals and 7-bit gradation or 8
It is configured to convert the levels of R, G, and B signals for bit gradation and output them.

Reference numeral 22 denotes a display timing signal output circuit. The display timing signal output circuit 22 is mainly composed of a sub-field number counter 24 and a display pulse number counter 26, and a control signal from the control circuit 20 is provided.
On the basis of the above, the display timing pulses are output to the display control circuit 28 at the timings shown in (a), (b) and (c) of FIG.

That is, the sub-field number counter 24 outputs pulses corresponding to the sub-field numbers 6, 7, and 8 based on the control signal from the control circuit 20, and the display pulse number counter 26 outputs the sub-field number counter 26. 6, based on the output signal from the field number counter 24,
The number of display pulses corresponding to 7-bit and 8-bit gray scale is output to the display control circuit 28, and the carry output is output to the subfield number counter 24 as a reset signal.

The display control circuit 28 displays the display timing pulse from the display timing signal output circuit 22,
, The display data to be written in the field memory 12 is controlled to be data of 6, 7, and 8 bit gradation.

The display timing of the display timing pulse is, as shown in FIG. 2A, 1F (one field display period) for six subfield periods SF1 to SF6.
Time-division into each subfield period SF1, SF2, S
Further, F3, ..., SF6 are further added to AP (address period) and SP.
1 (display period 1), AP and SP2, AP and SP3, ...
Time division into AP and SP6, and these display periods SP1 and S
P2, SP3, ..., SP6 to 14, 28, 56, ..., 4
Assigned 48 display pulses, 1: 2: 4: ...: 32
Weight the ratio of. For convenience of explanation, the number of display pulses is set to AP uniquely determined by the PDP 16 and display pulse periods of 1.5 ms and 7.5 μs, respectively.
F is set to 16 ms.

That is, since 1F is time-divided into 6 SFs, the address period in 1F is 9ms (= 1.5m).
s × 6), and the display period in 1F is 7 ms (= 16 m)
s-9 ms). Therefore, when weighting 64 (6 bits) within the display period of 7 ms, the number of display pulses of unit weight is 14 (= 7 × 1000/64/7.
5). Note that the AP includes the periods of steps 1, 2, 3, and 4, as in the conventional example described with reference to FIG.

As for the display timing of the display timing pulse, as shown in FIG. 2B, 1F is time-divided into seven subfield periods SF1 to SF7, and each subfield period SF1, SF2, SF3 ,. 5, 10, 2 in the display periods SP1, SP2, SP3, ..., SP7 of SF7.
Display pulses of 0, ..., 320 are assigned, and 1: 2: 4:
The ratio of 64 is weighted. The number of display pulses is determined as follows.

That is, since 1F is time-divided into 7 SFs, the address period in 1F is 10.5 ms (=
1.5ms x 7), and the display period in 1F is 5.5m
s (= 16 ms-10.5 ms). Therefore, the number of display pulses of unit weight when weighting 128 (7 bits) within this 5.5 ms display period is 5 (=
5.5 × 1000/128 / 7.5).

The display timing of the display timing pulse is, as shown in FIG. 2C (almost the same as FIG. 3A), 1F to 8 subfield periods SF1 to S.
It is time-divided into F8 and each subfield period SF1, SF
2, SF3, ..., SF8 display periods SP1, SP2, S
256 are assigned to P3, ..., SP8, and the ratio of 1: 2: 4: ...: 128 is weighted. The number of display pulses is determined as follows.

That is, since 1F is time-divided into 8 SFs, the address period in 1F is 12 ms (= 1.5).
ms × 8), and the display period in 1F is 4 ms (= 16
ms-12 ms). Therefore, the number of display pulses of unit weight when weighting 256 (8 bits) within this 4 ms display period is 2 (= 4 × 1000/256).
/7.5).

Next, the operation of the above embodiment will be described. (A) The integrating circuit 18 integrates the Y signal to obtain A
PL is output, and the control circuit 20 compares the APL with a preset setting level to control signals l, m, h, l, corresponding to the brightness of the display image.
The m, h, l, m, and h are output to the γ correction / level conversion circuit 10, and the control signals, and are output to the display timing signal output circuit 22.

(B) The γ correction / level conversion circuit 10 controls the control signals l, m, h, l from the control circuit 20.
Input R, based on m, h, l, m, h
The G and B signals are γ-corrected and the brightness level is converted. That is, when the APL is low (for example, less than 3.5%) within the range of less than 10%, medium (for example, 3.5% or more and less than 7%), or high (for example, 7% or more and less than 10%), the
As shown in the conversion patterns l, m, and h in (b), the input R, G, and B signals for 8-bit gradation are γ-corrected and the brightness levels are converted to R, G, and B signals for 6-bit gradation. And output.

APL is low (for example, 10% or more and less than 15%), medium (for example, 15% or more and less than 20%) and high (for example, 20% or more and 25%) within the range of 10% or more and less than 25%.
Less than%), the conversion pattern l of FIG.
As indicated by m and h, the input R, G, B signals for 8-bit gradation are γ-corrected, and the levels are converted into R, G, B signals for 7-bit gradation or 8-bit gradation and output. .

When the APL is low (for example, 25% or more and less than 50%), medium (for example, 50% or more and less than 75%), or high (for example, 75% or more) within the range of 25% or more, FIG. As shown in the conversion patterns l, m, and h of (b), the input R, G, and B signals for 8-bit gradation are γ-corrected and the levels are converted into R, G, and B signals for 8-bit gradation. Output.

(C) On the other hand, the display timing signal output circuit 22 has a display timing as shown in FIGS. 2 (a) (b) (c) based on the control signal from the control circuit 20. The timing pulse is output to the display control circuit 28. That is, when the APL is less than 10%, a display timing pulse having a maximum display pulse number of 896 having a display timing of 6-bit gradation as shown in FIG. 2A is input to the display control circuit 28.

When the APL is 10% or more and less than 25%, the display timing pulse of the maximum display pulse number 640 having the display timing of 7-bit gradation as shown in FIG. Input to the circuit 28. When the APL is 25% or more, the display timing pulse of the maximum display pulse number 512 having the display timing of 8-bit gradation as shown in (c) of FIG. 2 is input to the display control circuit 28.

(D) The display control circuit 28 displays the display timing pulse from the display timing signal output circuit 22.
, The display data to be written in the field memory 12 is controlled to have 6-, 7-, and 8-bit gradation data.

(E) As described above, the field memory 1 is subjected to the γ correction and the level conversion and the gradation conversion.
The display data written in 2 is sent to the PDP 16 via the PDP driver 14. Therefore, the PDP 16 displays with a display characteristic similar to the conversion pattern shown in FIG.

That is, when the APL is low, medium, or high within the range of less than 10% (when the screen is dark), the PDP 16
Is displayed with display characteristics similar to the conversion patterns l, m, and h in FIG. When the APL is low, medium, or high within the range of 10% or more and less than 25%, PDP16
Is displayed with display characteristics similar to the conversion patterns l, m, and h in FIG. When the APL is low, medium, or high within the range of 25% or more, display is performed with display characteristics approximate to the conversion patterns l, m, and h in FIG.

In the above-mentioned embodiment, the APL is divided into three stages and the display gradation is switched to three stages of 6, 7, and 8 bit gradations correspondingly, but the present invention is not limited to this. Instead, the APL is divided into m stages (m is an integer of 2 or more), and the display gradation is switched to m stages of different bit gradations corresponding to this, and the display gradation increases as the brightness of the display image becomes brighter. Anything that can increase the number may be used. For example, the APL may be divided into four stages, and the display gradation may be switched to four stages of 5, 6, 7, and 8 bit gradations correspondingly.

In the above-described embodiment, three types of conversion patterns for γ correction and level conversion of the video signal for each of the brightness of the display image in three stages are set according to the size of the APL in each stage, and adjacent patterns are set. Although the change in the brightness level at the time of switching between the steps is smoothed, the present invention is not limited to this, and the conversion patterns for the γ correction and the level conversion are changed according to the size of the APL in each step. A plurality of types (for example, two types) other than the three types may be provided to smoothly change the luminance level when switching between adjacent stages, or γ
Only one conversion pattern for correction and level conversion may be provided for each stage.

In the above embodiment, the brightness non-linearity is corrected at the same time by performing the γ correction and the level conversion of the video signal for each of the three levels of the brightness of the display image. The present invention is not limited to this, and the present invention can be applied to a case in which γ correction is omitted.

[0039]

As described above, the method for displaying a halftone image on the display panel according to the present invention can be applied to the APL of a video signal.
The brightness of the display image is divided into m steps (m is an integer of 2 or more) by comparing with the set level, and the brightness of the display image increases so that the brightness of the display image becomes brighter. The halftone image is displayed by switching the number of divisions (for example, the number of subfields) N of one screen display period (for example, one field display period) according to the number of stages, so that the number of divisions (for example, subfields) is displayed. The number N is switched to, for example, 6, 7, or 8 such that the brighter the display image is, the larger the number of display gradations is (for example, the number of display gradations is 64, 128, 256).

Therefore, in a dark screen where the APL is small, the number of divisions (for example, the number of subfields) N is switched to a direction in which the number is small (for example, from 8 to 6), and the number of address periods AP is small. Even on the screen, the maximum display brightness does not decrease, and the contrast ratio does not decrease.
That is, the display image quality can be improved as compared with the conventional example. Further, when the APL is large, the number of display gradations is controlled in the direction of decreasing the display luminance, and when the APL is small, the number of display gradations is controlled in the direction of increasing the display luminance. The difference in power consumption when the values are small can be reduced and averaged, and the load on the power source can be reduced.

[Brief description of drawings]

1A and 1B show an embodiment of a halftone image display method for a display panel according to the present invention, wherein FIG. 1A is a schematic configuration diagram of a main part of an apparatus for carrying out the method of the present invention, and FIG. γ
It is a characteristic view explaining an operation of the correction / level conversion circuit.

2A and 2B are explanatory diagrams for explaining the display timing of the display timing pulse output from the display timing signal output circuit of FIG. 1A, in which FIG. 2A shows the display timing of 6-bit gradation, and FIG. The display timing of 7-bit gradation is shown, and (c) shows the display timing of 8-bit gradation.

FIG. 3 is an explanatory diagram illustrating a display timing of a display timing pulse of a conventional example.

[Explanation of symbols]

10 ... γ correction / level conversion circuit, 12 ... Field memory, 14 ... PDP driver, 16 ... PDP, 18 ... Integration circuit, 20 ... Control circuit, 22 ... Display timing signal output circuit, 28 ... Display control circuit, 1F ... 1 Field display period (one screen display period), APL ... average image level, PDP ... Plasma display panel (display panel example), R, G, B ... Digital R, G, B signals (video signal example) , SF1 to SF8 ... Subfield period (an example of divided display period), Y ... Luminance signal.

Claims (3)

[Claims] 1. One for each pixel of a display panel.
The number of bits N (N is 2) corresponding to the display gradation in the screen display period.
In the method of displaying a halftone image of a video signal by time-division into display periods of (the above integer) and weighting the number of display pulses in each divided display period corresponding to each bit, the APL (average) of the video signals The brightness of the display image is divided into m levels (m is an integer of 2 or more) by comparing the video level) with the set level, and the display gradation is increased as the brightness of the display image increases. A halftone image display method for a display panel, wherein the number of divisions N is switched according to the brightness level of the image to display a halftone image. 2. A plurality of types of video signal level conversion patterns for each of m steps of display image brightness depending on the size of the APL in each step in order to smoothly switch between adjacent steps. Claim 1 which is provided
A method for displaying a halftone image on the display panel described. 3. The halftone image on the display panel according to claim 2, wherein the level conversion pattern of the video signal at each of the brightness of the display image of m stages is also used for γ correction for correcting the non-linearity of the brightness. Display method.