JPH06252723A - Load drive circuit - Google Patents

Abstract

PURPOSE:To reduce a radio noise caused when a display device is driven. CONSTITUTION:A control signal inputted to an internal terminal 10 is inputted to a NAND gate 50, a NOR gate 60 and an inverter 20. The control signal inputted to the inverter 20 is inputted to the NAND gate 50 and the NOR gate 60 via a delay element 30 and an inverter 40. Then each of a P-channel MOS transistor (TR) 70 and an N-channel MOS TR 80 being components of a CMOS output stage is driven through its gate based on the logic of the NAND gate 50 and the NOR gate 60 and a potential at an output terminal 90 is controlled to a level 'Hi' of an output drive power supply 110 or a ground level 'Lo'. Thus, a display element is dimmed and both TRs are turned off at the switching of the Level 'Hi' or 'Lo' through the delay operation of the delay element 30 and no through-current is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load driving circuit, and more particularly to a load driving circuit suitable for use as a driving circuit for driving a display such as a fluorescent display tube (VFD tube) or a liquid crystal display.

[0002]

2. Description of the Related Art Generally, in an apparatus having a display unit, the lighting of a display device is driven by duty control to adjust the brightness to a required brightness. Further, in order to efficiently drive a large number of display elements, dynamic control is also performed in which a single drive control output drives a plurality of display elements.

A conventional display element 13 will be described with reference to FIGS. 3 and 4.
The drive control of 0 will be described. The driving IC 100 has an oscillator, a duty ratio control circuit, a CMOS output circuit for driving the display element shown in FIG. 4, and the like, which are not shown, built therein. The driving IC 100 outputs an output driving power source 110 via its output terminal 90. And the display element 130 are repeatedly connected. The connection time here is determined by the duty ratio, and the brightness of the display element 130 is controlled according to the duty ratio. In FIG. 3, 120 is a power supply for driving the IC, and in FIG. 4, 10 is an internal terminal for inputting a control signal from the duty ratio control circuit to the CMOS output circuit, 220 is a logic gate, and 270 and 280 are P respectively. Channel MOS transistor, N-channel MOS
The potential of the output terminal 90 is set to the potential level “Hi” or the ground level “L” of the output driving power source 110 by a transistor.
and a CMOS output stage of "o".

[0004]

However, when the drive control of the display element is performed in the above-mentioned conventional structure, the output from the CMOS output circuit for driving the display element is usually several k.
"Hi" and "Lo" are repeated at a frequency of Hz to several tens of kHz. At this time, in the CMOS output stage of the driving IC,
A through current flows in synchronization with the change points of “Hi” and “Lo”. The frequency of the display drive signal, that is, the frequency of the dimming duty signal on the power supply line and the ground line on the circuit, or the frequency of the dimming duty signal or Noise having a signal frequency in the dynamic control as a fundamental frequency component is superimposed.

As a result, a radio, such as a vehicle,
In a system system equipped with a stereo or the like, there is a problem that unnecessary electromagnetic waves are received, which causes radio noise.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a load driving circuit capable of effectively reducing radio noise caused by harmonic components of noise generated in a power supply. To aim.

[0007]

In order to achieve the above object, the present invention provides a load drive circuit in which a CMOS output connects a load and a power supply, and a P-channel MOS transistor constituting the CMOS and A technical means is adopted in which a control means is provided for turning off the N-channel MOS transistors alternately for a predetermined time when they are turned on and off alternately.

[0008]

Therefore, the P channel M forming the CMOS
At the time of switching such that the OS transistor and the N-channel MOS transistor are alternately turned on and off, there is a predetermined time during which both transistors are turned off by the control means. That is, the CMOS output stage has a CMOS
It is possible to prevent the through current from flowing in synchronization with the change points of the output “Hi” and “Lo”.

[0009]

The present invention will be described below based on the embodiments shown in the drawings. FIG. 1 is a circuit configuration diagram of a CMOS output circuit 1 in a fluorescent display tube drive circuit to which an embodiment of the present invention is applied. The structure of the fluorescent display tube drive circuit is shown in FIG. The CMOS output circuit 1 shown in FIG. 1 is incorporated in the driving IC 100 shown in FIG. 3 as in the above-described conventional technique (FIG. 4). Below, focusing on the differences from the conventional one shown in FIG.
This embodiment will be described.

The control signal from the duty ratio control circuit (not shown) input to the internal terminal 10 is the NAND gate 5
0, input to the NOR gate 60 and the inverter 20. The control signal input to the inverter 20 passes through the delay element 30 and the inverter 40, and then passes through the NAND gate 50.
And NOR gate 60. And NAN
A P-channel MOS forming a CMOS output stage based on the logic of each of the D gate 50 and the NOR gate 60
Transistor 70, N-channel MOS transistor 80
Are gate-driven, and the potential of the output terminal 90 is controlled to the potential level “Hi” or the ground level “Lo” of the output driving power source 110. As a result, dimming of the display element (fluorescent display tube) 130 is performed. The delay element 3
0 can be configured by a known CR circuit. Also, P
The channel MOS transistor 70 and the N-channel MOS transistor 80 are laid out in a large transistor size so that an output current that drives a display element at several MHz can be obtained.

Next, the operation of FIG. 1 will be described with reference to FIG. 2 is a time chart showing signal waveforms at points a to d shown in FIG. When the potential at the point a changes from “Hi” to “Lo”, it changes from “Hi” to “Lo” at the point b with a delay of the delay time t _D of the delay element 30. As a result, the NAND gates 50, N
A phase difference corresponding to the delay time t _D occurs in the input signal to the OR gate 60. Therefore, the "Lo" output of the NAND gate 50 that is the drive element of the P-channel MOS transistor 70 and the "Hi" output of the NOR gate 60 that is the drive element of the N-channel MOS transistor 80 do not overlap for the delay time t _D. . Therefore, the P-channel MOS transistor 70 and the N-channel MOS transistor 80 are controlled so that both the transistors are turned off for the delay time t _D.

As described above, in this embodiment, the P-channel MOS transistor 70 and the N-channel MOS transistor 80 forming the CMOS output stage are alternately turned on and off with the time region in the off state interposed therebetween. To be driven. Therefore, the power supply 11 in the CMOS output stage
The shoot-through current between 0 and ground (GND) can be substantially zero. Therefore, harmonic components are reduced and radio noise is not received.

Further, not only the radio noise is reduced, but also the shoot-through current can be made substantially zero.
Since the power consumption of the power supply can be reduced and the noise on the power supply line can be reduced, the malfunction can be effectively prevented.

[0014]

As described above, according to the present invention, CM
It is possible to prevent a through current from flowing in the OS output stage in synchronization with the change points of “Hi” and “Lo” of the CMOS output, prevent noise superposition on the power supply, and cause harmonic components of noise generated in the power supply. There is an effect that the generated radio noise can be effectively reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a CMOS output circuit in a fluorescent display tube drive circuit to which an embodiment of the present invention is applied.

FIG. 2 is a time chart showing signal waveforms.

FIG. 3 is a circuit configuration diagram of a fluorescent display tube drive circuit.

FIG. 4 is a circuit configuration diagram of a CMOS output circuit in a conventional display element drive circuit.

[Explanation of symbols]

 1 CMOS Output Circuit 10 Internal Terminal 30 Delay Element 50 NAND Gate 60 NOR Gate 70 P-Channel MOS Transistor 80 N-Channel MOS Transistor 90 Output Terminal 100 Driving IC 110 Output Driving Power Supply 130 Display Element

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number for FI Technical indication H03K 19/0175 H05B 37/00 8715-3K 41/24 F 9249-3K

Claims (1)

[Claims] 1. A load drive circuit configured to connect a load and a power supply with a CMOS output, wherein P-channel MOS transistors and N-channel MOS transistors forming the CMOS are alternately turned on,
A load drive circuit comprising control means for turning off both transistors for a predetermined time when turning off.