JP2007208881A - Differential signal control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output phase-aligned differential output signals while completely excluding a through current in a differential signal control circuit. <P>SOLUTION: The differential signal control circuit comprising two push-pull circuits (constituted of NMOS transistors N1, N2 and PMOS transistors P1, P2) for inputting differential input signals (Ai, Bi) and outputting differential output signals (Ao, Bo), respectively includes a first delay circuit 11 for delaying one differential input signal, a second delay circuit 12 for delaying another differential input signal, and a condition determination circuit 10 which inputs outputs of these first and second delay circuits 11, 12 and the differential input signals and outputs a control signal for controlling the push-pull circuits, so that each of the push-pull circuits passes through a high impedance state without fail when inverting output levels of the differential output signals. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention controls transfer of differential signals used in USB (Universal Serial Bus), IEEE 1394 (Institute of Electrical and Electronic Engineers 1394), Rambus (registered trademark), DDR-DRAM (Double Data Rate Dynamic Random Access Memory), and the like. In particular, the present invention relates to a circuit suitable for improving a phase shift between differential input signals and completely eliminating a through current of an output circuit.

  In USB, IEEE 1394, Rambus (registered trademark), DDR-DRAM, etc., signal transfer is performed by a differential method excellent in high-speed signal transfer, low voltage, noise resistance, etc. A differential signal control circuit is used.

  FIG. 4 is a circuit diagram showing a configuration example of a conventional differential signal control circuit. This control circuit is a differential signal drive circuit that outputs differential input signals Ai and Bi as differential output signals Ao and Bo.

  The differential input signal Ai is connected to the inputs of the inverter 13 and the buffer circuit 16. The differential input signal Bi is connected to the inputs of the inverter 15 and the buffer circuit 14.

  The output of the inverter 13 is connected to the gate of the PMOS transistor P1, the output of the buffer circuit 14 is connected to the gate of the NMOS transistor N1, the output of the inverter 15 is connected to the gate of the PMOS transistor P2, and the output of the buffer circuit 16 is connected to the gate of the NMOS transistor N2. Has been.

  The source of the PMOS transistor P1 is connected to the power supply Vdd, the drain is connected to the drain of the NMOS transistor N1, and the source of the NMOS transistor N1 is connected to the ground Vss to constitute a push-pull circuit. The differential output signal Ao is output from the common drain of both transistors. The push-pull circuit that outputs the differential output signal Bo has the same configuration.

  FIG. 5 is an explanatory diagram showing an operation example of the differential signal drive circuit in FIG. 4, and is a timing chart of the differential input signals Ai and Bi, and each transistor (P1, N1, P2,. The on / off state of N2) is entered.

  FIG. 5A shows the case where the phases of the differential input signals Ai and Bi are aligned. In this case, when the level of the differential output signal is inverted, the impedance of the output circuit is lowered and a through current is generated in a very short time.

  FIG. 5B shows a case where the differential input signals Ai and Bi are out of phase. In this case, in the section D1, all the transistors constituting the push-pull circuit are on, and a large through current is generated.

  For example, Patent Document 1 discloses a conventional technique for coping with the through current problem occurring in such a differential signal drive circuit. This technique improves a large through current as described in FIG.

  FIG. 6 is a circuit diagram showing another configuration example of the conventional differential signal control circuit. This differential signal control circuit (“complementary buffer circuit”) includes inverters 61 and 63, delay circuits (denoted as “Delay” in the figure) 62 and 64, NMOS transistors Q1 to Q8, Q11 and Q12, PMOS transistor Q9, Q10.

  The differential input signal Bi is connected to the input of the inverter 61 and the gates of the NMOS transistors Q4 and Q5. The output of the inverter 61 is connected to the input of the delay circuit 62 and the gate of the NMOS transistor Q12. The output of the delay circuit 62 is connected to the gates of the NMOS transistors Q3 and Q6.

  The differential input signal Ai is connected to the input of the inverter 63 and the gates of the NMOS transistors Q1 and Q8. The output of the inverter 63 is connected to the input of the delay circuit 64 and the gate of the NMOS transistor Q11. The output of the delay circuit 64 is connected to the gates of the NMOS transistors Q2 and Q7.

  The NMOS transistors Q1 to Q4 are sequentially connected in series between the power supplies Vdd and Vss. Similarly, NMOS transistors Q5 to Q8 are also connected in series between power supplies Vdd and Vss.

  The NMOS transistors Q1 and Q8 are ON / OFF controlled by the differential input signal Ai, the NMOS transistors Q2 and Q7 are ON / OFF controlled by the output signal of the delay circuit 64, and the NMOS transistors Q4 and Q5 are differential input signals. On / off control is performed by Bi, and NMOS transistors Q3 and Q6 are on / off controlled by the output signal of the delay circuit 62.

  Further, the connection point of the NMOS transistors Q2 and Q3 is connected to the output terminal of the differential output signal Bo, and the connection point of the NMOS transistors Q6 and Q7 is connected to the output terminal of the differential output signal Ao.

  The source of the PMOS transistor Q9 is connected to the power supply Vdd, the drain is connected to the drain of the NMOS transistor Q11, and is connected to the output terminal of the differential output signal Bo. The gate is connected to the drain of the PMOS transistor Q10.

  The source of the PMOS transistor Q10 is connected to the power supply Vdd, the drain is connected to the drain of the NMOS transistor Q12, and is connected to the output terminal of the differential output signal Ao. The gate is connected to the drain of the PMOS transistor Q9.

  The operation of this circuit is to invert the other differential output signal when one signal rises when one rising edge timing of the differential input signal (Ai, Bi) is earlier than the other falling edge timing. I try to let them.

  As a result, it is possible to prevent all the output transistors from being turned on and a large through current from flowing as in the control circuit of FIG.

  However, even in this circuit, the short-time through current generated when the differential output signals (Ao, Bo) are inverted is not improved.

  For example, consider the case where the differential output signal Bo changes from a high level to a low level. When the differential output signal Bo is at a high level, the PMOS transistor Q9 is on and the NMOS transistor Q11 is off.

  When the differential input signal Ai changes from the high level to the low level, the NMOS transistor Q11 is turned on via the inverter 3. The PMOS transistor Q9 is turned off because the differential output signal Bo is lowered and the PMOS transistor is turned off. This is after Q10 is turned on and, as a result, the gate voltage of the PMOS transistor Q9 is raised.

  Therefore, although it is a short time, the NMOS transistor Q11 and the PMOS transistor Q9 are simultaneously turned on. A similar operation occurs between the PMOS transistor Q10 and the NMOS transistor Q12.

JP 2001-274669 A

  The problem to be solved is that the conventional technique cannot eliminate a very short through current generated when the differential output signal is inverted in the differential signal control circuit.

  An object of the present invention is to solve these problems of the prior art, to completely eliminate a through current in a differential signal control circuit, and to output a differential output signal having a uniform phase. .

  In order to achieve the above object, in the present invention, two push-pull circuits (P1, N1, P2) for inputting a differential input signal (Ai, Bi) and outputting each of the differential output signals (Ao, Bo) are provided. In the differential signal control circuit provided with P2, N2), when the output level of the differential output signal is inverted, each push-pull circuit always passes through the high impedance state. Specifically, a first delay circuit (11) that delays one differential input signal, a second delay circuit (12) that delays the other differential input signal, and the first and second delay circuits. The condition determination circuit (10) for inputting the output of the delay circuit (11, 12) and the differential input signal and outputting a control signal for controlling each push-pull circuit is provided. Further, the delay time of the first and second delay circuits is longer than the maximum phase shift time of the differential input signal. In addition, the condition determination circuit (10) includes a case where the differential input signal changes simultaneously, a case where one signal of the differential input signal changes from low level to high level, and the other signal is high level, and When one of the differential input signals changes from a high level to a low level and the other signal is at a low level, the first and second delay circuits ( During the delay time of 11, 12), a control signal for making each push-pull circuit high impedance is output.

  According to the present invention, when the differential output signals (Ao, Bo) are inverted, all the transistors (P1, N1, P2, N2) constituting the output push-pull circuit are connected to the delay circuit (11, Since the signal is turned off for the predetermined time set in 12), a very short through current can be completely eliminated, and even if there is a phase shift in the differential input signals (Ai, Bi), the phases are aligned. The differential output signals (Ao, Bo) can be output.

  The best mode for carrying out the present invention will be described below with reference to the drawings. 1 is a block diagram showing a configuration example of a differential signal control circuit according to the present invention, FIG. 2 is an explanatory diagram showing an operation example of the differential signal control circuit in FIG. 1, and FIG. 3 is a diagram in FIG. It is a timing chart explaining the example of operation of a differential signal control circuit.

  The differential signal control circuit shown in FIG. 1 includes delay circuits 11 and 12 and a condition determination circuit 10 that constitute holding means according to the present invention. Further, inverters 13 and 15 and buffer circuits 14 and 16 are respectively push-pull. This is a differential signal drive circuit comprising PMOS transistors P1, P2 and NMOS transistors N1, N2 constituting the circuit.

  The delay circuits 11 and 12 delay the input of the differential input signals Ai and Bi to the condition determination circuit 10 by a predetermined time. This delay time is set longer than the maximum phase shift time between the differential input signal Ai and the differential input signal Bi.

  The condition determination circuit 10 receives differential input signals Ai and Bi and delay signals Ad and Bd obtained by delaying these signals by a predetermined time, decodes the four input signals, and constitutes a push-pull circuit. A control signal for controlling each of the transistors P1, N1, P2, and N2 is output.

  In the basic operation of decoding, when the differential input signal Ai is at a high level, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. When the differential input signal Ai is at a low level, the PMOS transistor P1 is turned off. The transistor N1 is turned on.

  Similarly, when the differential input signal Bi is high, the PMOS transistor P2 is turned on and the NMOS transistor N2 is turned off. When the differential input signal Bi is low, the PMOS transistor P2 is turned off and the NMOS transistor N2 is turned off. turn on.

  However, when the differential input signal Ai and the differential input signal Bi change simultaneously and when one of the differential input signal Ai and the differential input signal Bi changes from low level to high level, the other signal When one of the differential input signal Ai and the differential input signal Bi changes from a high level to a low level when the other signal is a low level, While the delay time elapses from the time when changes, a control signal for setting all the transistors P1, N1, P2, and N2 constituting each push-pull circuit to high impedance is output. As a result, even a very short through current in the differential signal drive circuit can be completely eliminated, and even if there is a phase shift in the differential input signal (Ai, Bi), the differential output signal (Ao) having the same phase can be obtained. , Bo) can be output.

  FIG. 2 is a truth table in the condition determination circuit 10 in the differential signal drive circuit shown in FIG. The condition determining circuit 10 outputs each output signal (differential input signal Ai, delayed signal Ad, differential input signal Bi, delayed signal Bd) corresponding to the correspondence shown in the truth table for the input of each input signal (differential input signal Ai, delayed signal Ad, differential input signal Bi, delayed signal Bd). It comprises a logic circuit that outputs Do1, Do2, Do3, Do4). This truth table varies depending on the circuit configuration of the differential signal drive circuit. Further, the shaded conditions (No. 0, 5, 10, 15) in this truth table are combinations of conditions that do not occur in normal operation.

  FIG. 3 is an operation timing chart of the differential signal drive circuit in FIG. A shaded portion in the figure is a period in which all the transistors of the push-pull circuit are turned off by the condition determination circuit 10.

  FIG. 3A shows an example in which the differential input signal Ai and the differential input signal Bi are in phase. In the section A1, the differential input signal Ai and the delay signal Ad are at a low level (“0”), and the differential input signal Bi and the delay signal Bd are at a high level (“1”). The output “Do1 = 0”, the output “Do2 = 1”, the output “Do3 = 1”, and the output “Do4 = 0” are output based on the condition of “No. 12” in the truth table shown in FIG. As a result, the PMOS transistor P1 is off, the NMOS transistor N1 is on, the PMOS transistor P2 is on, and the NMOS transistor N2 is off.

  In the section A2, the differential input signal Ai changes to high level and the differential input signal Bi changes to low level, but the delay signals Ad and Bd have not changed yet (the delay signal Ad is low level, the delay signal Bd). Therefore, the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 0”, and “Do3 = 0” based on the condition of “No. 9” in the truth table shown in FIG. The output “Do4 = 0” is output, all the transistors (P1, N1, P2, N2) are turned off, and the push-pull circuit including these transistors (P1, N1, P2, N2) is set to high impedance.

  When the delay time elapses and the period A3 is entered, the differential input signal Ai and the delay signal Ad are at a high level, and the differential input signal Bi and the delay signal Bd are at a low level. The output “Do1 = 1”, the output “Do2 = 0”, the output “Do3 = 0”, and the output “Do4 = 1” are output based on the condition of “No. 3” in the truth table shown in FIG. As a result, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the PMOS transistor P2 is turned off, and the NMOS transistor N2 is turned on.

  Further, in the section A4, the differential input signal Ai changes to low level and the differential input signal Bi changes to high level, but the delay signals Ad and Bd have not changed yet (the delay signal Ad is high level, delayed). Since the signal Bd is low level, the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 0”, “Do3 = 0”, and “Do3 =” based on the condition of “No. 6” in the truth table shown in FIG. 0 ”and output“ Do4 = 0 ”, and in the same way as the section A2, all the transistors (P1, N1, P2, N2) are turned off, and the push-pull composed of these transistors (P1, N1, P2, N2) Make the circuit high impedance.

  The section A5 is the same as the section A1, and the same operation is repeated thereafter.

  FIG. 3B shows an example in which the phase of the differential input signal Ai is ahead of the differential input signal Bi. In the section B1, the differential input signal Ai and the delay signal Ad are at a low level (“0”), and the differential input signal Bi and the delay signal Bd are at a high level (“1”), so the section A1 in FIG. Similarly to the above, the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 1”, “Do3 = 1”, “Do3 = 1”, and “Output” based on the condition of “No. 12” in the truth table shown in FIG. Do4 = 0 "is output, and as a result, the PMOS transistor P1 is off, the NMOS transistor N1 is on, the PMOS transistor P2 is on, and the NMOS transistor N2 is off.

  In the section B2, only the differential input signal Ai changes from the low level to the high level. However, the delay signal Ad and the differential input signal Bi and the delay signal Bd are the same as those in the section B1 (the delay signal Ad is at the low level, the difference). The condition determination circuit 10 outputs “Do1 = 0” and “Do2 = 0” based on the condition of “No. 13” in the truth table shown in FIG. , Output “Do3 = 0”, output “Do4 = 0”, turn off all the transistors (P1, N1, P2, N2), and push-pull comprising these transistors (P1, N1, P2, N2) Make the circuit high impedance.

  In the section B3, the differential input signal Bi becomes low level, but since the delay time of the delay circuits 11 and 12 has not yet elapsed, the differential input signal Ai is high level, the delay signal Ad is low level, and the delay is delayed. The signal Bd remains at the high level, and the condition determination circuit 10 outputs the output “Do1 = 0”, the output “Do2 = 0”, and the output “based on the condition“ No. 9 ”in the truth table shown in FIG. Do3 = 0 "and output" Do4 = 0 "are output. As a result, all the transistors (P1, N1, P2, N2) remain off, and the push-pull circuit composed of these transistors (P1, N1, P2, N2) remains high impedance.

  In section B4, the delay time of the delay circuit 11 elapses, the delay signal Ad changes from low level to high level, the differential input signal Ai is high level, the differential input signal Bi is low level, and the delay signal Bd is high level. Thus, the condition determination circuit 10 outputs “Do1 = 1”, “Do2 = 0”, “Do3 = 0”, and “Do4” based on the condition “No. 11” in the truth table shown in FIG. = 1 "is output. As a result, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the PMOS transistor P2 is turned off, and the NMOS transistor N2 is turned on.

  In the interval B5, the delay time of the delay circuit 12 elapses, the delay signal Bd changes from high level to low level, the differential input signal Ai and the delay signal Ad are high level, and the differential input signal Bi is low level. The condition determination circuit 10 outputs the output “Do1 = 1”, the output “Do2 = 0”, the output “Do3 = 0”, similarly to the section B4, based on the condition of “No. 3” in the truth table shown in FIG. The output “Do4 = 1” is output, and as a result, the PMOS transistor P1 is on, the NMOS transistor N1 is off, the PMOS transistor P2 is off, and the NMOS transistor N2 remains on.

  In section B6, the differential input signal Ai changes from the high level to the low level, the delay signal Ad is at the high level, the differential input signal Bi and the delay signal Bd are at the low level, and the condition determination circuit 10 is shown in FIG. The output “Do1 = 0”, the output “Do2 = 0”, the output “Do3 = 0”, and the output “Do4 = 0” are output based on the condition of “No. 2” in the truth table shown in FIG. N1, P2, N2) are all turned off, and the push-pull circuit composed of these transistors (P1, N1, P2, N2) is set to high impedance.

  In the section B7, the differential input signal Bi changes from the low level to the high level, but since the delay time of the delay circuits 11 and 12 has not yet elapsed, the differential input signal Ai is at the low level and the delay signal Ad is at the high level. The delay signal Bd remains at the low level, and the condition determination circuit 10 outputs “Do1 = 0” and “output” as in the section B6 based on the condition “No. 6” in the truth table shown in FIG. Do2 = 0 ", output" Do3 = 0 ", output" Do4 = 0 ", and all the transistors (P1, N1, P2, N2) remain off, and these transistors (P1, N1, P2, The push-pull circuit consisting of N2) remains high impedance.

  In the section B8, the delay time of the delay circuit 11 elapses, the delay signal Ad changes from high level to low level, the differential input signal Ai is low level, the differential input signal Bi is high level, and the delay signal Bd is Based on the condition of “No. 4” in the truth table shown in FIG. 2, the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 1”, “Do3 = 1”, The output "Do4 = 0" is output, the PMOS transistor P1 is off, the NMOS transistor N1 is on, the PMOS transistor P2 is on, and the NMOS transistor N2 is off.

  In the section B9, the delay time of the delay circuit 12 elapses, the delay signal Bd changes from low level to high level, the differential input signal Ai is low level, the delay signal Ad is low level, and the differential input signal Bi is high level. The condition determination circuit 10 outputs the “Do1 = 0”, the “Do2 = 1”, the “Do2 = 1”, and the “Do3 =” as in the section 8, based on the condition of “No. 12” in the truth table shown in FIG. 1 "and output" Do4 = 0 ", the PMOS transistor P1 is off, the NMOS transistor N1 is on, the PMOS transistor P2 is on, and the NMOS transistor N2 is off. The operation in the section B9 is the same as that in the section B1, and thereafter the same operation is repeated.

  FIG. 3C shows an example in which the phase of the differential input signal Ai is delayed from the differential input signal Bi. In the section C1, the differential input signal Ai and the delayed signal Ad are at a low level, and the differential input signal Bi and the delayed signal Bd are at a high level, as in the sections A1 and B1 in FIGS. The condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 1”, “Do3 = 1”, “Do4 = 1”, and “Do4 = 0” based on the condition of “No. 12” in the truth table shown in FIG. As a result, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, the PMOS transistor P2 is turned on, and the NMOS transistor N2 is turned off.

  In the section C2, the differential input signal Bi changes from the high level to the low level, but the differential input signal Ai is still at the low level, the delay signal Ad is at the low level, and the delay signal Bd is at the high level. 10 outputs the output “Do1 = 0”, the output “Do2 = 0”, the output “Do3 = 0”, and the output “Do4 = 0” based on the condition of “No. 8” in the truth table shown in FIG. Then, all the transistors (P1, N1, P2, N2) are turned off, and the push-pull circuit composed of these transistors (P1, N1, P2, N2) is set to high impedance.

  In the section C3, the differential input signal Ai changes from the low level to the high level, but since the delay time of the delay circuits 11 and 12 has not yet elapsed, the delay signal Ad is at the low level and the differential input signal Bi is at the low level. The delay signal Bd is at the high level, and the condition determination circuit 10 outputs the output “Do1 = 0”, the output “Do2 = 0”, and the output “based on the condition“ No. 9 ”in the truth table shown in FIG. Do3 = 0 "and output" Do4 = 0 ", and as a result, all the transistors (P1, N1, P2, N2) remain off, and from these transistors (P1, N1, P2, N2) This push-pull circuit remains high impedance.

  In section C4, the delay time of the delay circuit 12 elapses, the delay signal Bd changes from high level to low level, the differential input signal Ai is high level, the delay signal Ad is low level, and the differential input signal Bi is low level. The condition determination circuit 10 outputs “Do1 = 1”, “Do2 = 0”, “Do3 = 0”, “Do3 = 0”, and “No” based on the conditions of “No. 1” in the truth table shown in FIG. Do4 = 1 "is output, and as a result, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the PMOS transistor P2 is turned off, and the NMOS transistor N2 is turned on. This state continues until section C5.

  That is, in the section C5, the delay time 11 has elapsed, the delay signal Ad changes from low level to high level, the differential input signal Ai is high level, and the differential input signal Bi and the delay signal Bd are low level. Yes, the condition determination circuit 10 outputs “Do1 = 1”, output “Do2 = 0”, output “Do3 = 0”, and output “Do4” based on the condition of “No. 3” in the truth table shown in FIG. As a result, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the PMOS transistor P2 is turned off, and the NMOS transistor N2 is turned on.

  In the section C6, the differential input signal Bi changes to a high level, but the differential input signal Ai is still at a high level, the delay signal Ad is at a high level, and the delay signal Bd is at a low level. 10 outputs the output “Do1 = 0”, the output “Do2 = 0”, the output “Do3 = 0”, and the output “Do4 = 0” based on the condition of “No. 7” in the truth table shown in FIG. Then, all the transistors (P1, N1, P2, N2) are turned off, and the push-pull circuit composed of these transistors (P1, N1, P2, N2) is set to high impedance.

  In the section C7, the differential input signal Ai is at a low level, but since the delay time of the delay circuits 11 and 12 has not yet elapsed, the delay signal Ad is at a high level, the differential input signal Bi is at a high level, and the delay signal. Bd is at the low level, and the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 0”, and “Do3 = 0” based on the condition of “No. 6” in the truth table shown in FIG. Output "Do4 = 0", and as a result, all the transistors (P1, N1, P2, N2) remain off, and the push-pull circuit comprising these transistors (P1, N1, P2, N2) Remains high impedance.

  In the section C8, when the delay time of the delay circuit 12 elapses and the delay signal Bd changes from low level to high level, the differential input signal Ai is low level, the delay signal Ad is high level, and the differential input signal Bi is Based on the condition of “No. 14” in the truth table shown in FIG. 2, the condition determination circuit 10 outputs “Do1 = 0”, “Do2 = 1”, “Do3 = 1”, The output “Do4 = 0” is output, and as a result, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, the PMOS transistor P2 is turned on, and the NMOS transistor N2 is turned off. This state continues until section C9.

  That is, in the section C9, the delay time 12 has elapsed, the delay signal Ad changes from the high level to the low level, the differential input signal Ai is at the low level, and the differential input signal Bi and the delay signal Bd are at the high level. Yes, the condition determination circuit 10 outputs “Do1 = 0”, output “Do2 = 1”, output “Do3 = 1”, and output “Do4” based on the condition of “No. 12” in the truth table shown in FIG. As a result, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, the PMOS transistor P2 is turned on, and the NMOS transistor N2 is turned off. Since the operation in the section C9 is the same as that in the section C1, the same operation is repeated thereafter.

  As described above with reference to FIGS. 1 to 3, in this example, when the differential output signals Ao and Bo are inverted, all the transistors P1, N1, and P2 that constitute the output push-pull circuit are inverted. , N2 are turned off for a predetermined time set by the delay circuits 11, 12. As a result, even a very short through current can be completely eliminated, and even if the differential input signal Ai and the differential input signal Bi are out of phase, the differential output signal Ao and the differential output signal Bo having the same phase can be obtained. Can be output.

  In addition, this invention is not limited to the example demonstrated using FIGS. 1-3, In the range which does not deviate from the summary, various changes are possible.

It is a block diagram which shows the structural example of the differential signal control circuit (differential signal drive circuit) which concerns on this invention. FIG. 2 is an explanatory diagram illustrating an operation example of a differential signal control circuit (differential signal drive circuit) in FIG. 1. 2 is a timing chart illustrating an operation example of a differential signal control circuit (differential signal drive circuit) in FIG. 1. It is a circuit diagram which shows the structural example of the conventional differential signal control circuit (differential signal drive circuit). FIG. 5 is an explanatory diagram illustrating an operation example of the differential signal control circuit in FIG. 4. It is a circuit diagram which shows the other structural example of the conventional differential signal control circuit (complementary buffer circuit).

Explanation of symbols

  10: Condition determination circuit, 11, 12: Delay circuit (“Delay”), 13, 15: Inverter, 14, 16: Buffer circuit, P1, P2: PMOS transistor, N1, N2: NMOS transistor, Ai, Bi: Difference Dynamic input signal, Ao, Bo: differential output signal, Ad, Bd: delay signal, Do1 to Do4: control signal, N1G, N2G, P1G, P2G: gate signal, Vdd: power supply, Vss: ground, 61, 63: Inverters, 62, 64: delay circuit (“Delay”), Q1 to Q8, Q11, Q12: NMOS transistors, Q9, Q10: PMOS transistors.

Claims (4)

A differential signal control circuit comprising two push-pull circuits that each receive a differential input signal and output a differential output signal,
A differential signal control circuit comprising holding means for temporarily holding each of the push-pull circuits in a high impedance state when the output level of the differential output signal is inverted. The differential signal control circuit according to claim 1,
The holding means is
A first delay circuit for delaying one differential input signal;
A second delay circuit for delaying the other differential input signal;
A condition determination circuit that inputs the differential input signal and the outputs of the first and second delay circuits and generates and outputs a control signal for controlling each of the push-pull circuits; Differential signal control circuit. The differential signal control circuit according to claim 2,
The differential signal control circuit according to claim 1, wherein a delay time of the first and second delay circuits is longer than a maximum phase shift time of the differential input signal. A differential signal control circuit according to any one of claims 2 and 3,
The condition determination circuit includes:
When the differential input signals change simultaneously;
When one signal of the differential input signal changes from low level to high level and the other signal is high level; and
When one signal of the differential input signal changes from high level to low level and the other signal is low level,
Differential signal control characterized by comprising means for generating and outputting a control signal for setting each of the push-pull circuits to high impedance only during the delay time from the time when the level of the one signal changes circuit.

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