JPH06252346A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPH06252346A JPH06252346A JP5033540A JP3354093A JPH06252346A JP H06252346 A JPH06252346 A JP H06252346A JP 5033540 A JP5033540 A JP 5033540A JP 3354093 A JP3354093 A JP 3354093A JP H06252346 A JPH06252346 A JP H06252346A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- srtio
- manufacturing
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体記憶装置、特
にＤＲＡＭにおけるキャパシタ絶縁膜の製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor insulating film in a semiconductor memory device, especially a DRAM.
【０００２】[0002]
【従来技術】ＤＲＡＭ（ダイナミック・ランダム・アク
セス・メモリ）の高集積化に伴って、キャパシタの面積
が減少していき、このキャパシタ面積の減少によるキャ
パシタ容量の低下が問題になりつつある。この問題を解
決するためキャパシタの構造を工夫することに着目し、
例えば、フィン構造や円筒状構造が提案されている。し
かし、このようにキャパシタの構造が複雑になると、プ
ロセスの工程数が増加し、これによって、コストが大幅
に上昇してしまう。2. Description of the Related Art As DRAM (Dynamic Random Access Memory) is highly integrated, the area of the capacitor is decreasing, and the decrease of the capacitor area due to the decrease of the capacitor area is becoming a problem. Focusing on devising the structure of the capacitor to solve this problem,
For example, fin structures and cylindrical structures have been proposed. However, when the structure of the capacitor becomes complicated as described above, the number of process steps increases, which significantly increases the cost.
【０００３】この問題の根本的な原因は、キャパシタの
絶縁膜に用いるＳｉＯ2 、Ｓｉ3 Ｎ4 膜の比誘電率が小
さいことである。このため比誘電率が大きいものを使え
ば、キャパシタ構造の単純化を維持しながら大容量が得
られるため、近年よく研究されている。この研究の結
果、室温で常誘電体である高比誘電率を有するチタン酸
ストロンチウム（ＳｒＴｉＯ3 ）膜が取り扱いやすいた
め、一つの代表的な存在となっている。この膜の形成方
法としては、例えば高周波マグネトロン・スパッタ法を
用いる。The fundamental cause of this problem is that the relative permittivity of the SiO 2 and Si 3 N 4 films used for the insulating film of the capacitor is small. For this reason, if a material having a large relative dielectric constant is used, a large capacity can be obtained while maintaining the simplification of the capacitor structure. As a result of this research, a strontium titanate (SrTiO 3 ) film having a high relative dielectric constant, which is a paraelectric at room temperature, is easy to handle, and thus is one of the representatives. As a method of forming this film, for example, a high frequency magnetron sputtering method is used.
【０００４】[0004]
【発明が解決しようとする課題】上述した高周波マグネ
トロン・スパッタ法によりＳｒＴｉＯ3 膜を形成する場
合、この膜の比誘電率が膜形成時の基板温度に依存し、
基板温度が低くなるにしたがい、比誘電率も小さくな
る。この比誘電率の低下を防止し大きい比誘電率を得る
ためには、高温で膜を形成する必要があり、通常、６０
０℃以上の温度が必要とされている。When a SrTiO 3 film is formed by the above-mentioned high frequency magnetron sputtering method, the relative dielectric constant of this film depends on the substrate temperature at the time of film formation,
The relative permittivity also decreases as the substrate temperature decreases. In order to prevent this decrease in relative permittivity and obtain a large relative permittivity, it is necessary to form a film at a high temperature.
Temperatures above 0 ° C are required.
【０００５】しかしながら、膜の形成を高温で行なうと
色々な問題が生じ、例えば、膜のリ−ク電流の増大や製
造装置の高コスト化などがある。However, when the film is formed at a high temperature, various problems occur, such as an increase in the leak current of the film and an increase in the cost of the manufacturing apparatus.
【０００６】この発明は、上述した膜形成時、基板温度
が低くなることによって生じた比誘電率の低下や、これ
を防ぐための高温化によって生じるリ−ク電流の増加の
問題点を解決し、比誘電率が低下することなく、リ−ク
電流の増加を防止できる半導体記憶装置の製造方法を提
供することを目的とする。The present invention solves the problems of a decrease in the relative permittivity caused by a decrease in the substrate temperature during the above-mentioned film formation and an increase in the leak current caused by a rise in temperature to prevent this. An object of the present invention is to provide a method for manufacturing a semiconductor memory device capable of preventing an increase in leak current without lowering the relative dielectric constant.
【０００７】[0007]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明の半導体記憶装置の製造方法は、半導体基
板を加熱する工程と、半導体基板上にチタン酸ストロン
チウム膜を形成する工程と、半導体基板の温度を１５０
℃／分以上の冷却速度で冷却する工程とを有する。In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention comprises a step of heating a semiconductor substrate, and a step of forming a strontium titanate film on the semiconductor substrate. , The temperature of the semiconductor substrate is 150
And a step of cooling at a cooling rate of not less than ° C / min.
【０００８】[0008]
【作用】上述した本発明の半導体記憶装置の製造方法で
は、膜形成時の基板温度が低くなることによって生じた
比誘電率の低下や、これを防ぐための高温化によって生
じるリ−ク電流の増加がなくなる。In the method of manufacturing a semiconductor memory device according to the present invention described above, a decrease in the relative dielectric constant caused by a decrease in the substrate temperature during film formation and a leakage current caused by a high temperature to prevent this decrease. There will be no increase.
【０００９】[0009]
【実施例】本発明の半導体記憶装置の製造工程を図１を
用いて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a semiconductor memory device of the present invention will be described with reference to FIG.
【００１０】まず、半導体基板温度を２００℃以上に設
定する。First, the semiconductor substrate temperature is set to 200 ° C. or higher.
【００１１】高周波マグネトロン・スパッタ法を用いて
拡散層や下部電極などを有する半導体基板上にチタン酸
ストロンチウム（ＳｒＴｉＯ3 ）膜を形成する。この膜
の形成条件は、高周波パワ−は２０Ｗ以上、スパッタ圧
力は３ｍＴｏｒｒ以上である。A strontium titanate (SrTiO 3 ) film is formed on a semiconductor substrate having a diffusion layer and a lower electrode by using a high frequency magnetron sputtering method. The conditions for forming this film are a high frequency power of 20 W or more and a sputtering pressure of 3 mTorr or more.
【００１２】ＳｒＴｉＯ3 膜の形成後、基板を１５０℃
／分以上の冷却速度で冷却する。After forming the SrTiO 3 film, the substrate was heated to 150 ° C.
Cool at a cooling rate of at least 1 minute.
【００１３】冷却工程が終了後、基板をスパッタ装置か
ら取り出す。After the cooling process is completed, the substrate is taken out of the sputtering device.
【００１４】次に、このようにして形成されたＳｒＴｉ
Ｏ3 膜のリ−ク電流の測定結果を図２に示し、結果の説
明を行なう。なお、従来と比較するためにＳｒＴｉＯ3
膜の形成後、基板を１５０℃／分以下の冷却速度で冷却
したＳｒＴｉＯ3 膜のリ−ク電流の測定結果も併記す
る。Next, the SrTi thus formed
The measurement result of the leak current of the O 3 film is shown in FIG. 2, and the result will be described. Incidentally, in order to compare with the conventional one, SrTiO 3
The measurement results of the leak current of the SrTiO 3 film obtained by cooling the substrate at a cooling rate of 150 ° C./min or less after the film formation are also shown.
【００１５】なお、この比較実験の共通条件としては、
ＳｒＴｉＯ3 膜の形成前、基板を２００℃以上の温度で
加熱したものであり、電極面積が８．８×１０-4cm2 の
試料を使用した。As a common condition of this comparative experiment,
Before forming the SrTiO 3 film, the substrate was heated at a temperature of 200 ° C. or higher, and a sample having an electrode area of 8.8 × 10 −4 cm 2 was used.
【００１６】図２からも明らかなように、従来の方で
は、印加電圧を０〜３Ｖと上げていくと、リ−ク電流密
度は１×１０-7〜５×１０-5Ａ／cm2 と増加していく。
これに対して、本発明の方では、印加電圧を０〜３Ｖと
上がっていくと、リ−ク電流密度は１×１０-9〜１×１
０-7Ａ／cm2 と増加していく。リ−ク電流特性として、
印加電圧が３Ｖの場合、本発明は従来に比して約２桁以
上のリ−ク電流密度の低減ができた。As is apparent from FIG. 2, in the conventional case, when the applied voltage is increased to 0 to 3 V, the leak current density is 1 × 10 −7 to 5 × 10 −5 A / cm 2. And increase.
On the other hand, according to the present invention, when the applied voltage is increased to 0 to 3 V, the leak current density is 1 × 10 −9 to 1 × 1.
It increases to 0 -7 A / cm 2 . As the leak current characteristic,
When the applied voltage is 3V, the present invention can reduce the leak current density by about two digits or more as compared with the conventional case.
【００１７】また、ＳｒＴｉＯ3 膜の表面状態も観察し
てみた。図示していないが、本発明の方法により、形成
したＳｒＴｉＯ3 膜の表面は、従来の方法に比して非常
に良い状態を有していた。The surface condition of the SrTiO 3 film was also observed. Although not shown, the surface of the SrTiO 3 film formed by the method of the present invention had a very good state as compared with the conventional method.
【００１８】さらに、ＳｒＴｉＯ3 膜の比誘電率も測定
してみた。ＳｒＴｉＯ3 膜のバルクの比誘電率が３００
であるのに対して、従来の方法により形成したＳｒＴｉ
Ｏ3膜の比誘電率は約１５０であるが、本発明の方法に
より形成したＳｒＴｉＯ3 膜の比誘電率は約２４０であ
り、比較的高い比誘電率が得られた。Further, the relative permittivity of the SrTiO 3 film was also measured. Bulk dielectric constant of SrTiO 3 film is 300
In contrast, SrTi formed by the conventional method
The relative permittivity of the O 3 film was about 150, but the relative permittivity of the SrTiO 3 film formed by the method of the present invention was about 240, and a relatively high relative permittivity was obtained.
【００１９】上述の通り本発明の方法を用いることによ
って、ＳｒＴｉＯ3 膜の比誘電率の低下及びリ−ク電
流の増加の防止ができるのは、ＳｒＴｉＯ3 膜の形成
後、基板を１５０℃／分以上の冷却速度で冷却するた
め、ＳｒＴｉＯ3 膜表面から酸素が抜けにくくなり、穴
のない良いＳｒＴｉＯ3 膜表面が得られる、良い表面状
態のＳｒＴｉＯ3 膜が得られるためリ−ク電流が少なく
なる。これによって、絶縁特性が良くなると共に、比誘
電率の向上ができたと考える。As described above, by using the method of the present invention, it is possible to prevent the relative permittivity of the SrTiO 3 film from decreasing and the increase of the leak current to be prevented, after forming the SrTiO 3 film at 150 ° C. / Since the cooling is performed at a cooling rate of not less than a minute, it becomes difficult for oxygen to escape from the surface of the SrTiO 3 film, a good SrTiO 3 film surface without holes can be obtained, and a SrTiO 3 film with a good surface state can be obtained, so that the leak current is small. Become. It is considered that this improves the insulation characteristics and improves the relative permittivity.
【００２０】次に、本発明の半導体記憶装置の製造工程
を実施するためのスパッタ装置について図３と図４を用
いて説明する。Next, a sputtering apparatus for carrying out the manufacturing process of the semiconductor memory device of the present invention will be described with reference to FIGS. 3 and 4.
【００２１】図３は、スパッタ装置の略式断面図であ
り、これはｉｎ−ｓｉｔｕ式である。ＳｒＴｉＯ3 膜
２を形成した半導体基板１は、ステ−ジ６上に載置され
ていて、この半導体基板１は基板押え３で押えられてい
る。ステ−ジ６の下部には２００℃以上の加熱手段４、
例えばヒ−タ−と、１５０℃／分以上の冷却手段５、例
えば冷却水を循環する冷却水ラインとを備えている。FIG. 3 is a schematic sectional view of the sputtering apparatus, which is of in-situ type. The semiconductor substrate 1 having the SrTiO 3 film 2 formed thereon is placed on a stage 6, and the semiconductor substrate 1 is held by a substrate holder 3. In the lower part of the stage 6, a heating means 4 of 200 ° C. or higher,
For example, a heater and a cooling means 5 of 150 ° C./min or more, for example, a cooling water line for circulating cooling water are provided.
【００２２】次に、図４は、スパッタ装置の略式平面図
であり、これはｆｌｏｗ式である。この装置は、基板の
加熱ステ−ジと冷却ステ−ジが別々してあり、チャンバ
−内の別のステ−ジから搬送された基板が２００℃以上
の加熱手段を有するスパッタステ−ジ１１に載置され
る。このスパッタステ−ジ１１でＳｒＴｉＯ3 膜が基板
上に形成される。次にＳｒＴｉＯ3 膜が形成された基
板がスパッタステ−ジ１１から直接、冷却ステ−ジ１２
に搬送され、冷却ステ−ジ１２でＳｒＴｉＯ3膜が形成
された基板の温度を１５０℃／分以上の冷却速度で冷却
する。その後、例えば、チャンバ−１３を介して、ある
いは直接、スパッタ装置外へ取り出す。Next, FIG. 4 is a schematic plan view of the sputtering apparatus, which is a flow type. In this apparatus, a substrate heating stage and a cooling stage are separated, and a substrate transferred from another stage in a chamber is placed on a sputtering stage 11 having a heating means of 200 ° C. or higher. Placed. A SrTiO 3 film is formed on the substrate by this sputtering stage 11. Next, the substrate on which the SrTiO 3 film was formed was directly transferred from the sputter stage 11 to the cooling stage 12.
The substrate having the SrTiO 3 film formed thereon is cooled at a cooling rate of 150 ° C./minute or more in the cooling stage 12. After that, for example, it is taken out of the sputtering apparatus through the chamber 13 or directly.
【００２３】[0023]
【発明の効果】以上説明したように、本発明の半導体記
憶装置の製造方法によれば、比較的低温でＳｒＴｉＯ3
膜を形成できるようになり、ＳｒＴｉＯ3 膜の比誘電
率は、高温でＳｒＴｉＯ3 膜を形成した場合と同様の
値を得ることができると共に、良い膜の表面状態を得る
ことができ、さらにリ−ク電流の増加を防止できる。従
って、従来のように大きいキャパシタ容量を得るため、
キャパシタの構造を複雑する必要もなくなるため、プロ
セスの工程数が増加することもない、これによって、コ
ストダウンも図れ、高品質のキャパシタ絶縁膜を有する
半導体記憶装置が得られる。As described above, according to the method of manufacturing a semiconductor memory device of the present invention, SrTiO 3 is produced at a relatively low temperature.
The film can be formed, the relative permittivity of the SrTiO 3 film can be the same value as that when the SrTiO 3 film is formed at a high temperature, and the surface condition of the film can be improved. It is possible to prevent an increase in the electric current. Therefore, in order to obtain a large capacitor capacity as before,
Since it is not necessary to complicate the structure of the capacitor, the number of process steps does not increase, which leads to cost reduction and a semiconductor memory device having a high-quality capacitor insulating film.
【図１】本発明の半導体記憶装置の製造フロ−を説明す
るための図。FIG. 1 is a diagram for explaining a manufacturing flow of a semiconductor memory device of the present invention.
【図２】リ−ク電流特性を示す図。FIG. 2 is a diagram showing a leak current characteristic.
【図３】本発明の半導体記憶装置の製造装置の説明図。FIG. 3 is an explanatory diagram of a semiconductor memory device manufacturing apparatus according to the present invention.
【図４】本発明の半導体記憶装置の製造装置の説明図。FIG. 4 is an explanatory diagram of a semiconductor memory device manufacturing apparatus according to the present invention.
１ 半導体基板 ２ ＳｒＴｉＯ3 膜 ３ 基板押え ４ 加熱手段 ５ 冷却手段 ６ ステ−ジ1 Semiconductor Substrate 2 SrTiO 3 Film 3 Substrate Retainer 4 Heating Means 5 Cooling Means 6 Stage
Claims (3)
る工程と、 前記半導体基板の温度を１５０℃／分以上の冷却速度で
冷却する工程とを有することを特徴とする半導体用キャ
パシタ絶縁膜の製造方法。1. A method comprising the steps of heating a semiconductor substrate, forming a strontium titanate film on the semiconductor substrate, and cooling the temperature of the semiconductor substrate at a cooling rate of 150 ° C./min or more. A method of manufacturing a capacitor insulating film for a semiconductor, comprising:
マグネトロン・スパッタ法により形成することを特徴と
する請求項１記載の半導体記憶装置の製造方法。2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the strontium titanate film is formed by a high frequency magnetron sputtering method.
ことを特徴とする請求項１記載の半導体記憶装置の製造
方法。3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the heating step is performed at 200 ° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03354093A JP3164685B2 (en) | 1993-02-23 | 1993-02-23 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03354093A JP3164685B2 (en) | 1993-02-23 | 1993-02-23 | Method for manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06252346A true JPH06252346A (en) | 1994-09-09 |
| JP3164685B2 JP3164685B2 (en) | 2001-05-08 |
Family
ID=12389402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03354093A Expired - Fee Related JP3164685B2 (en) | 1993-02-23 | 1993-02-23 | Method for manufacturing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3164685B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11236666A (en) * | 1998-02-25 | 1999-08-31 | Murata Mfg Co Ltd | Film forming device and production of dielectric film |
| US7310238B2 (en) | 2005-08-05 | 2007-12-18 | Ibiden Co., Ltd. | Thin-film embedded capacitance, method for manufacturing thereof, and a printed wiring board |
-
1993
- 1993-02-23 JP JP03354093A patent/JP3164685B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11236666A (en) * | 1998-02-25 | 1999-08-31 | Murata Mfg Co Ltd | Film forming device and production of dielectric film |
| US7310238B2 (en) | 2005-08-05 | 2007-12-18 | Ibiden Co., Ltd. | Thin-film embedded capacitance, method for manufacturing thereof, and a printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3164685B2 (en) | 2001-05-08 |
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