JPH06250843A - Arithmetic processing method and arithmetic unit - Google Patents

Abstract

PURPOSE:To speed up processing by changing the constitution of a program itself including a condition branching instruction, fetching both instructions for the success of branching and its failure and selecting either one of the instructions. CONSTITUTION:The constitution of the program itself is changed, a branch instruction is stored in an instruction address N of an instruction memory part 1 and a conditional instruction is stored in the succeeding instruction address N+1. The 1st instruction address supplying part 2-1 generates the address N to read out and fetch a branching instruction from the memory part 1 to the 1st instruction fetching part 3-1. An execution part 5 supplies a branched address A0 to the 1st and 2nd instruction address branching parts 2-1, 2-2 based upon an instruction execution result and supplies a branch generating information X and a branch success information Y to a selection control part 6, which controls an instruction selecting part 4, and when branching succeeds, selects a branched instruction and supplies the selected instruction to the execution part 5. When branching fails, the succeeding instruction is selected and supplied to the execution part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method and an arithmetic processing for effectively improving the performance by effectively utilizing the instruction prefetching effect when a conditional branch instruction is included when executing a program by pipeline control. Regarding the device.

[0002]

2. Description of the Related Art In the field of microprogram control by a processor or the like, pipeline control is performed in order to achieve high-speed processing of programs. In this pipeline control, the instructions are sequentially called from the memory in which the instructions are stored, fetched, decoded, executed, and stored, and the stages are alternately forwarded. That is, the instruction read first is fetched, and the next instruction is fetched at the timing of being decoded next. Then, when the instruction read first is executed, the instruction read next is decoded, and the instruction read next is fetched. Through such processing, efficient use of hardware and high-speed arithmetic processing can be achieved.

When a conditional branch instruction is included in such a program, the execution order of the program changes, but pipeline control in such a case poses a problem. In other words, when a certain operation result is obtained by a certain instruction, if the next operation result satisfies a certain condition, the next instruction is skipped and another branch destination instruction is issued. Processing such as execution is performed. However, the branch destination address designated by such a conditional branch instruction cannot be obtained until the execution of the conditional branch instruction is completed. Thus, in the normal pipeline control, we anticipate in advance which instructions to fetch, can not tell determine may be decoded.

Therefore, conventionally, for example, without waiting for the execution of a conditional branch instruction, the following instruction and the predicted branch destination instruction are uniformly prefetched, and fetched and decoded to perform a different operation from the prediction. When the instruction is to be executed, the instruction that has already been fetched is discarded and the correct instruction is fetched again. Such a method is called branch prediction, and for example, in a program with a very high probability of branch occurrence, the speed can be increased by prefetching the predicted branch destination instruction. As another method, several cycles are allowed from the execution of the conditional branch instruction to the actual execution of the branch destination instruction, and during that time, instructions unrelated to the branch are executed. The cycle from the end of execution of a conditional branch instruction to the start of execution of a branch destination instruction is called a delay slot, and this method is also called a delayed branch.
In addition, the conventional technology as described above is described, for example, in "Information Science Dictionary" (Iwanami Shoten), "Instruction Prefetching" in p.739, "High Performance Computer Architecture" (Maruzen) pp.160-166.
3.5.1 “Conditional branching” and so on.

[0005]

However, there are the following problems in the arithmetic processing of the program including the conventional conditional branch instruction as described above. First, in the method of performing branch prediction in advance and prefetching an instruction, if the branch prediction is missed, the effect of instruction prefetching is lost. Therefore, there is a problem that the number of branches to either one is large, and the performance of programs other than those for which branch prediction is easy to take deteriorates. Moreover, in a processor that executes one instruction in one cycle, such as a RISC computer, the branch destination address is calculated when the execution of the conditional branch instruction is completed, so it is difficult to prefetch one branch destination instruction as it is.

For this reason, a method has been considered in which both the branch destination instruction and the instruction in the case where the branch is not taken are prefetched and the execution result of either one of them is used. In order to obtain the address of the branch destination instruction at the same time as reading the conditional branch instruction, it is necessary to separately prepare an information table or the like that stores the corresponding branch destination address for each branch destination instruction, which complicates the configuration. Become. Also,
The method of executing an instruction unrelated to a branch in the delay slot has a problem that the performance of the processor is deteriorated when there is no instruction unrelated to the branch that can be executed after the conditional branch instruction.

The present invention has been made by paying attention to the above points. By changing the configuration of the program itself including a conditional branch instruction, it is possible to prefetch both instructions when the branch is taken and when the branch is not taken. It is an object of the present invention to provide an arithmetic processing method and an arithmetic processing device in which the processing speed is increased by selecting either one thereafter.

[0008]

According to a first aspect of the present invention, when a program including a conditional branch instruction is executed by pipeline control, a branch destination of the program is designated so as to execute any one of a plurality of instructions. A branch instruction instruction address obtained by executing the branch instruction is preceded by the start of execution of a conditional instruction indicating a branch condition, and a plurality of corresponding pipelines are processed by a pipeline of a plurality of systems. Of the branch destination instructions are read out at the same time, and any one of the plurality of branch destination instructions is selected and executed according to the execution result of the conditional instruction.

A second aspect of the present invention is an instruction memory unit storing a program including a conditional branch instruction, and a first instruction address supply unit and a second instruction address supply unit for supplying different instruction addresses to the instruction memory unit at the same time. And a first instruction fetch unit and a second instruction fetch unit for fetching two types of instructions read simultaneously from the instruction memory unit,
The execution unit that executes the instruction read from the instruction memory unit, the instruction that is fetched by the first instruction fetch unit, and the instruction that is fetched by the second instruction fetch unit are selected and executed. A first instruction address supply unit, a second instruction address supply unit, and a selection control unit that controls the operation of the instruction selection unit, and the first instruction address supply unit and the first instruction address supply unit. When the pipeline composed of one instruction fetch unit is a line of the first system and the pipeline composed of the second instruction address supply unit and the second instruction fetch unit is a line of the second system, In the case where a branch instruction is included in the program, the line of either one of the lines causes the conditional instruction indicating the branch condition to be fetched after fetching the branch instruction indicating the branch destination, and each instruction in that order. The output to the execution unit, the first
The line of the system and the line of the second system fetch the branch destination instruction when the branch is taken and the next instruction when the branch is not taken, and the selection control unit determines which of the two depending on the execution result of the conditional instruction. The present invention relates to an arithmetic processing unit, wherein the instruction selection unit selects an instruction fetched in one line and outputs the instruction to an execution unit.

[0010]

In this method, first, a conditional branch instruction designating a program execution order is executed to obtain a branch destination instruction address, and instructions for a case where a branch is taken and a case where the branch is not taken are prefetched at the same time. The arithmetic processing instruction that determines whether or not the branch is taken is executed immediately after the conditional branch instruction, and the branch destination instruction is selected at a timing without waste. Therefore, the pipeline flow is not disturbed whether the branch is taken or not taken, and no dead time is generated between the fetch of the conditional branch instruction and the fetch of the branch destination instruction.

In order to carry out the above method, two pipelines are prepared in the arithmetic processing unit. When a branch instruction is fetched in the line of one system, a conditional instruction indicating a branch condition is fetched in the execution stage. next,
Using the branch destination instruction address obtained by executing the branch instruction, for example, the next instruction is fetched in the line of one system and the branch destination instruction is simultaneously fetched in the line of the other system in the subsequent stage. Further, depending on the execution result of the conditional instruction executed at that stage, either the next instruction or the branch destination instruction is selected at the next stage and output to the execution unit.
In the meantime, the preceding instruction of the instruction next to each instruction is performed on the lines of both systems, and the line selected by the instruction selection unit subsequently fetches the next instruction and advances the pipeline processing.

[0012]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit of the present invention. The illustrated apparatus includes an instruction memory unit 1 that stores a program including a conditional branch instruction, and an execution unit 5 that executes the read instruction. Moreover, in order to read an instruction from the instruction memory unit 1, a first instruction address supply unit 2-1 and a second instruction address supply unit 2-2 are provided. Furthermore, in order to fetch the read instruction,
First instruction fetch unit 3-1 and second instruction fetch unit 3-
Two are provided.

The outputs of the first instruction fetch unit 3-1 and the second instruction fetch unit 3-2 are both input to the instruction selection unit 4,
Either one of them is selected and input to the execution unit 5. Further, this apparatus is provided with a selection control unit 6 for controlling the operations of the first instruction address supply unit 2-1, the second instruction address supply unit 2-2 and the instruction selection unit 4. From the selection control unit 6, the instruction selection unit 4
To the first instruction address supply unit 2-1 and the second address selection signal S2 to the second instruction address supply unit 2-2. It is configured to do.

On the other hand, the execution unit 5 supplies the branch destination address A0 based on the execution result of the instruction to the first instruction address supply unit 2-.
The branch instruction notification X and the branch taken notification Y are supplied to the selection control section 6. That is, this apparatus is configured such that the first instruction line supply section 2-1 and the first instruction fetch section 3-1 form the first system line, the second instruction address supply section 2-2, and the second instruction fetch section 3-2. 2 has a second system line, and is configured to be able to simultaneously read and fetch arbitrary instructions from the instruction memory unit 1 and supply them to the execution unit 5.

FIG. 2 shows an explanatory diagram of a program example according to the method of the present invention. When the method of the present invention is carried out using the apparatus as described above, first, the program has a configuration different from the conventional one. FIG. 2 shows an example of such a program. When the instruction address of the instruction memory unit 1 shown in FIG. 1 is displayed as N-1, N, N + 1, N + 2 ...
The branch instruction is stored in the instruction address N, and the instruction address N
The conditional instruction is stored in +1 and the next instruction or branch destination instruction is stored in the subsequent instruction address. In this example, the branch destination instruction is stored in the instruction address L.

Generally, a conditional branch instruction is, for example, if K =
If it is 1, the instruction moves to the branch destination address L, and in other cases, an instruction with the content of executing the next instruction is described in one sentence, or if ... If there is a conditional instruction, then A branch instruction indicating the branch destination is described. However, in the present invention, the branch instruction designating the branch destination is first described, and then the conditional instruction indicating the branch condition is described. In the example of FIG. 2, the branch instruction of the instruction address N has a content of branching to the address L if the execution result of the next instruction is true, or executing the next instruction at the address N + 2 otherwise. There is. The condition instruction of the next address N + 1 has the content that the result is true if r0 = r1.

The outline of the operation when the program shown in FIG. 2 is executed by the apparatus shown in FIG. 1 will be described below. FIG. 3 shows a timing chart of the arithmetic processing operation according to the present invention. This timing chart shows that each instruction is processed in synchronism with each cycle C1 to C7 according to the operation clock of the device, as time elapses from left to right in the figure. . For example, the first instruction address supply unit 2-1 shown in FIG.
Generates an instruction address N and reads a branch instruction from the instruction memory unit 1. This instruction is fetched by the first instruction fetch unit 3-1 in FIG.

In each timing chart shown in FIG. 3, F represents a fetch stage, E represents an execution stage, and W represents a write stage. When the fetch stage of the branch instruction is executed in this cycle C1, the branch instruction moves to the execution stage of E in the cycle C2. On the other hand, the conditional instruction of the instruction address N + 1 is fetched in this cycle C2. This instruction address N + 1 is also output from the first instruction address supply unit 2-1 shown in FIG. 1, and the conditional instruction is fetched by the first instruction fetch unit 3-1. At this stage, it is assumed that the instruction selection unit 4 continues to supply the output of the first instruction fetch unit 3-1 to the execution unit 5.

When the branch instruction is executed in cycle C2, the branch destination address indicated by the branch instruction is obtained. The execution unit 5 shown in FIG. 1 supplies the branch destination address A0 to the first instruction address supply unit 2-1 and the second instruction address supply unit 2-2. In the next cycle C3,
The first instruction address supply unit 2-1 generates an instruction address N + 2 to read the next instruction following the conditional instruction.
The next instruction is read from the instruction memory unit 1 and fetched by the first instruction fetch unit 3-1.

On the other hand, when a branch instruction is executed in the cycle C2, a branch occurrence notification X notifying that the instruction is a branch instruction is output to the selection control unit 6. The selection control unit 6 thereby generates the second address selection signal S2 and causes the second instruction address supply unit 2-2 to select the branch destination address A0. The second instruction address supply unit 2-2 supplies the branch destination address A0 to the instruction memory unit 1. As a result, the branch destination instruction at the branch destination address L is read from the instruction memory unit 1 and fetched by the second instruction fetch unit 3-2.

In cycle C3, the branch instruction moves to the write stage and the conditional instruction moves to the execute stage. At this stage, the result of whether the branch condition is satisfied or not is obtained by the conditional instruction. The result is supplied from the execution unit 5 shown in FIG. 1 to the selection control unit 6 as a branch establishment notification Y. When the branch control notification 6 is input to the selection control unit 6, the selection control unit 6 generates an instruction selection signal S0 according to the contents of the notification Y and controls the instruction selection unit 4. Thus, when the branch is taken, the branch destination instruction is selected and supplied to the execution unit 5, and when the branch is not taken, the next instruction is selected and supplied to the execution unit 5.

In the example shown in FIG. 3, a branch is taken and the branch destination instruction is moved to the execution stage in the next cycle C4. When the branch is taken, the read control of the second instruction address supply unit 2-2 is prioritized thereafter, and the instruction at the next instruction address L + 1 read by this is read from the instruction memory unit 1 and It is fetched by the 2-instruction fetch unit 3-2. Therefore, after that, the second instruction address supply unit 2-2 performs the second
Instruction reading is controlled by the method line, and the instruction selecting unit 4 outputs the output of the second instruction fetching unit 3-2 to the executing unit 5.
To continue to supply.

As described above, according to the method of the present invention, FIG.
As shown in, the pipeline control is smoothly performed regardless of whether the branch is taken or not taken. Further, since either one of the instructions read in advance and fetched in advance is always transferred to the execution stage, efficient high-speed arithmetic processing without waste is possible.

FIG. 4 shows a block diagram of a concrete embodiment of the apparatus of the present invention. The device shown in FIG. 1 is specifically realized by the circuit configuration shown in this figure. That is, the first instruction address supply unit 2-1 shown in FIG. 1 includes the first address selector 101 and the first instruction address registers 102, 1
03 and the first adder 104. Further, the second instruction address supply unit 2-2 shown in FIG. 1 includes a second address selector 201 and second instruction address registers 202, 20.
3 and a second adder 204.

First instruction address registers 102, 103
Is composed of a register for holding the instruction address output from the first address selector 101 for the time of one cycle. The first adder 104 is a circuit for adding 1 to the output of the first instruction address register 103, incrementing the instruction address, and supplying it to the first address selector 101. The second instruction address registers 202 and 203 are registers for holding the output of the second address selector 201 for one cycle. The second adder 204 increments the instruction address by adding 1 to the output of the second instruction address register 203
This is a circuit for supplying to the address selector 201.

A branch destination address A0 is supplied to the first address selector 101 and the second address selector 201. In addition, the first address selector 101 and the second
In order to control the selection operation of the address selector 201,
First address selection signal S1 and second address selection signal S
2 is supplied. The output of the instruction memory unit 1 is connected to the first instruction register 105 and the second instruction register 205. The instruction read from the instruction memory unit 1 is fetched into these registers. The output of the first instruction register 105 and the output of the second instruction register 205 are input to the instruction selector 40. This instruction selector 40 is
It is composed of a multiplexer or the like for selecting either one of the input signals and outputting it to the decoding and execution unit 50. For this selection control, the command selection signal S
0 is input to the instruction selector 40. The decode and execute unit 50 is a circuit for decoding and executing an instruction input via the instruction selector 40. In general, the decoding unit and the execution unit are each composed of separate blocks, but particularly in the present invention,
The details are not shown because they need not be described.

FIG. 5 shows a block diagram of a specific example of the selection control unit. The branch occurrence notification X and the branch taken notification Y output from the decoding and execution unit 50 shown in FIG. 4 are accepted, and the first address selection signal S1 is sent to the first address selector 101 and the second address selector 201 shown in FIG. In order to output the second address selection signal S2 and the instruction selection signal S0 to the instruction selector 40 at the same time, the selection control unit is configured as shown in this figure. The selection control unit is composed of a control signal generation circuit 60 composed of a group of logic gates, and registers 61 and 62 provided on the input side and the output side thereof. As shown in this figure, the branch occurrence notification X is directly input to the control signal generation circuit 60, and is also input to the control signal generation circuit 60 after being held for one cycle in the register 61. In addition to this, the branch taken notification Y is also input to the control signal generation circuit 60.

On the other hand, from the control signal generation circuit 60, the first
The address selection signal S1 and the second address selection signal S2 are output. The instruction selection signal S0 is output from the control signal generation circuit 60 via the register 62. The instruction selection signal S0 is configured to be input again to the control signal generation circuit 60 for generating each control signal.
With the above configuration, the register 61 is configured to supply the content of the previous branch occurrence notification X to the control signal generation circuit 60, and the control signal generation circuit 60 sends the next instruction selection signal to the register 62. It is configured to be supplied.

FIG. 6 is a diagram for explaining the operation of the selection control section. The selection control unit as described above includes the control signal generation circuit 60.
The respective logic circuits generate the signals shown in FIG. That is, the branch occurrence notification X shown on the left side of the figure.
When the branch occurrence notification holding signal XB, the branch taken notification Y, and the instruction selection signal S0 output immediately before are input to the control signal generation circuit 60 of FIG. 5, this causes the next instruction selection signal SN and the first address selection. The signal S1 and the second address selection signal S2 are generated. In addition, in this figure,
"0" indicates a low level signal, "1" indicates a high level signal, and "X" indicates an invalid signal. These signals are supplied to each part of the circuit at the timings already described in the arithmetic processing operation of FIG.

FIG. 7 shows an operation timing chart of the device of the present invention. A series of instruction processing operations by the circuits shown in FIGS. 4 and 5 will be specifically described with reference to this timing chart. Note that this operation program is the same as that shown in FIG. Further, in FIG. 9A, the first instruction address stored in the first instruction address register 102 is shown, the second instruction address stored in the second instruction address register 202 is shown in FIG. The first instruction stored in the first instruction register 105, the second instruction stored in the second instruction register 205 in (d), the instruction selection signal supplied to the instruction selector 40 in (e), and (f). Is the executing instruction input to the decode and execute unit 50, (g)
Is the branch occurrence notification X output from the decoding and execution unit 50, and (h) is the branch occurrence notification holding signal X supplied from the register 61 of FIG. 5 to the control signal generation circuit 60.
B, (i) a branch taken notification output from the decoding and execution unit 50, and (j) a first address selection signal S used for selection control of the first address selector 101.
1, (k) is the second address selection signal S2 used for selection control of the second address selector 201, (m) is the branch destination address output from the decoding and execution unit 50, and (n) is the device. The clocks used to control the are shown.

First, in cycle C1,
When the first instruction address N is supplied from the first instruction address register 102 to the instruction memory unit 1 as shown in (a), the first instruction is read from the instruction memory unit 1 as shown in (c) and It is fetched into the 1-instruction register 105. As shown in (f), the decoding and executing unit 50 is executing the instruction at the instruction address N-1 at this stage. Further, it is assumed that the instruction selection signal S0 shown in (e) is at a low level, and the instruction selector 40 supplies the output of the first instruction register 105 to the decoding and execution unit 50. In this cycle C1, the first address selection signal shown in (j) is set to the low level, and the first address selector 101 selects the output signal of the first adder 104 to make the first
It is ready to be output to the instruction address register 103. Therefore, in the next cycle C2, the first adder 104
Address N obtained by adding 1 to the instruction address immediately before
+1 is used as the instruction address.

In cycle C2, the instruction having the first instruction address N + 1 shown in (a) is read from the instruction memory 1 and fetched in the first instruction register 105. Here, as shown in (f), the decoding and execution unit 50 is executing the instruction at the instruction address N. In this example, the instruction at the instruction address N is a branch instruction as shown in FIG. Therefore, as shown in (g), in the latter half of the cycle C2, the decode and execution unit 50 outputs the branch occurrence notification X, and further outputs the branch destination address A0. This becomes L as shown in (m).

Here, according to the logic shown in FIG.
The second address selection signal shown in (k) switches from low level to high level. In this way, the second address selector 201 shown in FIG. 4 selects the branch destination address A0 and outputs it to the second instruction address register 202. In the next cycle C3, the first instruction address register 1
The first instruction address supplied from 02 is N + 2,
The instruction at the address N + 2 is fetched into the first instruction register 105. On the other hand, the second instruction address register 20
The second instruction address L from 2 is supplied to the instruction memory unit 1, and the second instruction at the address L is fetched into the second instruction register 205. In the example shown in FIG. 2, the next instruction is fetched in the first instruction register 105, and the branch destination instruction is fetched in the second instruction register 205. In this cycle C3, the conditional instruction previously fetched in the first instruction register 105 is supplied to the decoding and execution unit 50 through the instruction selector 40 and is executed (FIG. 7 (f)).

As a result, as shown in FIG. 7 (i), it is judged that the branch is taken at the end of the cycle C3, and the decode and execute unit 50 sends a branch taken notification Y to the control signal generating circuit 60 shown in FIG. To enter. At this time, as shown in FIG. 7H, the branch occurrence notification holding signal is at the high level during the cycle C3. Therefore, according to the logic shown in FIG. 6, the instruction selection signal S0 shown in FIG. 7E switches from the low level to the high level at the next timing.

The instruction selector 40 shown in FIG. 4 operates to select the instruction fetched in the second instruction register 205 and output it to the decoding and execution unit 50.
As a result, in the next cycle C4, the branch target instruction at the branch target address L is executed, and the next instruction fetched at the same time is abandoned. This cycle C4
In, the second instruction address L + 1 stored in the second instruction address register 202 is output to the instruction memory unit 1 and the instruction at that address is fetched into the second instruction register 205. Thus, after this, the second time
The output of the instruction register 205 is continuously selected and provided to the decode and execute unit 50.

In the cycle C3, when the result that the conditional branch is not taken is obtained, the instruction selector 40 selects the output of the first instruction register 105 as before and directs it to the decoding and execution unit 50. Supply. Therefore, with the above-described configuration, when a branch instruction occurs, the pipelines of two systems can always read ahead the instruction to be executed next at the same time and proceed with processing without waste.

The present invention is not limited to the above embodiments. In the above embodiment, the pipeline has two systems,
For example, if the program is such that the branch destination is divided into three or more depending on the conditional branch instruction, three or more pipelines may be provided.

[0038]

According to the arithmetic processing method and the arithmetic processing apparatus of the present invention described above, the execution start of the branch instruction designating the branch destination is preceded by the execution start of the conditional instruction indicating the branch condition, and the branch instruction is executed. During this time, the branch destination instruction address is used to select a plurality of branch destination instructions prefetched by the pipelines of multiple systems according to the execution result of the conditional instruction. In a processor that executes instructions, both instructions at the branch destination can be preempted and pipeline processing can be executed without waste. Further, by providing a plurality of pipelines as described above, it is possible to select any one of them and always take advantage of the instruction prefetching, and it is possible to speed up the arithmetic processing and increase the efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit of the present invention.

FIG. 2 is a diagram illustrating a program example according to the method of the present invention.

FIG. 3 is a timing chart of a calculation processing operation according to the present invention.

FIG. 4 is a block diagram of a specific embodiment of the device of the present invention.

FIG. 5 is a block diagram of a specific example of a selection control unit.

FIG. 6 is an operation explanatory diagram of a selection control unit.

FIG. 7 is an operation timing chart of the device of the present invention.

[Explanation of symbols]

 1 Instruction Memory Unit 2-1 First Instruction Address Supply Unit 2-2 Second Instruction Address Supply Unit 3-1 First Instruction Fetch Unit 3-2 Second Instruction Fetch Unit 4 Instruction Selection Unit 5 Execution Unit 6 Selection Control Unit

Claims (2)

[Claims] 1. When a program including a conditional branch instruction is executed under pipeline control, execution of a branch instruction that specifies a branch destination of the program so as to execute any one of a plurality of instructions is indicated by a branch condition. Prior to the start of execution of the conditional instruction, the branch destination instruction address obtained by executing the branch instruction is used to prefetch and read a corresponding plurality of branch destination instructions at the same time by a pipeline of a plurality of systems, An arithmetic processing method, wherein any one of the plurality of branch destination instructions is selected and executed according to the execution result of the conditional instruction. 2. An instruction memory unit storing a program including a conditional branch instruction, a first instruction address supply unit and a second instruction address supply unit for simultaneously supplying different instruction addresses to the instruction memory unit, A first instruction fetch unit and a second instruction fetch unit for fetching two types of instructions read simultaneously from the instruction memory unit; an execution unit that executes the instructions read from the instruction memory unit; An instruction selection unit that selects one of the instruction fetched by the first instruction fetch unit and the instruction fetched by the second instruction fetch unit and outputs the selected instruction to the execution unit; the first instruction address supply unit; A two-instruction address supply unit and a selection control unit that controls the operation of the instruction selection unit, and a pipeline configured by the first instruction address supply unit and the first instruction fetch unit. The in is the line of the first system,
When the pipeline composed of the second instruction address supply unit and the second instruction fetch unit is a second system line, one of the system lines includes a branch instruction in the program. In this case, after fetching a branch instruction indicating a branch destination, a conditional instruction indicating a branch condition is fetched, and each instruction is output to the execution unit in that order, and the first system line and the second system line are respectively The branch destination instruction when the branch is taken and the next instruction when the branch is not taken are fetched, and the selection control unit selects the instruction fetched in one of the lines depending on the execution result of the conditional instruction. An arithmetic processing device characterized by causing a section to select and outputting to an execution section.