JPH0624857A - Multilayer ceramic board - Google Patents

Multilayer ceramic board

Info

Publication number
JPH0624857A
JPH0624857A JP17959992A JP17959992A JPH0624857A JP H0624857 A JPH0624857 A JP H0624857A JP 17959992 A JP17959992 A JP 17959992A JP 17959992 A JP17959992 A JP 17959992A JP H0624857 A JPH0624857 A JP H0624857A
Authority
JP
Japan
Prior art keywords
ceramic
layer
protective layer
internal electrode
composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17959992A
Other languages
Japanese (ja)
Inventor
Hiroharu Nishimura
弘治 西村
Hiromi Tokunaga
裕美 徳永
Shoji Kuroda
正二 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17959992A priority Critical patent/JPH0624857A/en
Publication of JPH0624857A publication Critical patent/JPH0624857A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Porous Artificial Stone Or Porous Ceramic Products (AREA)

Abstract

PURPOSE:To provide a multilayer ceramic board good for multilayer wiring on which an electronic circuit of conductors, resistors, etc., are formed in multiple layers. CONSTITUTION:This multilayer ceramic board contains an internal electrode 1, a ceramic layer 2 contg. the internal electrode has a structure different from that of a ceramic protective layer 3, and the ceramic layer 2 has a composition different from that of the ceramic protective layer 3. Consequently, the board can be sintered at 750-950 deg.C, Au, Ag, Ag-Pd, Cu, etc., are used for the internal electrode, the volume resistivity, permittivity, dielectric loss tangent, dielectric breakdown strength, flexural strength, etc., as the characteristics of a multilayer wiring board on which the electronic circuit of conductors, resistors, etc., are formed in multiple layers are satisfied, and further the TCC is easily adjusted to + or -0-100ppm/ deg.C.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、導体、抵抗体等の電子
回路を多層に形成する多層配線に用いられる多層セラミ
ック基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer ceramic substrate used for multi-layer wiring for forming electronic circuits such as conductors and resistors in multi-layers.

【0002】[0002]

【従来の技術】現在、多層に回路を形成する電子部品と
しては、焼成したアルミナ基板上に回路、絶縁層を交互
に印刷し、これを焼成することによって製造する第1の
方法と、未焼成のセラミック基板に回路を印刷し、互い
に回路が接触しないようにこれを積層し、プレスした
後、焼成して製造する第2の方法がある。第1の方法の
ものは、回路の影響によってその上に形成する絶縁層に
凹凸が生じ、それは上層ほど大きくなる。この凹凸が大
きくなると、この上に次の回路を印刷することは難しく
なり、通常10層前後が限度とされている。これに対
し、第2の方法のものは、回路の印刷は常に平面に近い
状態の基板に対して行うために、積層数の多いものを製
造することができ、高密度の集積回路形成が行える。こ
の高密度集積回路用として使用される多層セラミック基
板は、内部電極層間が100μm以下であるために、内
部電極が介在するセラミック層、そのセラミック層を取
り巻くセラミック保護層の性状が、直接回路への入出力
信号へ影響を及ぼす。この第2の方法の基板に使用する
セラミック基板組成物としては、Al23粉末と15w
t%以下のガラス粉末を無機バインダ−で固定したもの
や、Al23−SiO2系にP bやBを混入させ低温で
焼成したものがある。
2. Description of the Related Art At present, as an electronic component for forming a circuit in multiple layers, a first method of manufacturing a circuit by alternately printing a circuit and an insulating layer on a fired alumina substrate, and baking the circuit, and a non-fired method. There is a second method in which the circuit is printed on the ceramic substrate, the circuits are laminated so that the circuits do not come into contact with each other, and the circuit is pressed and then fired. In the case of the first method, the insulating layer formed thereon has irregularities due to the influence of the circuit, and the unevenness becomes larger in the upper layer. When this unevenness becomes large, it becomes difficult to print the next circuit on it, and the limit is usually around 10 layers. On the other hand, in the second method, since the circuit printing is always performed on the substrate in a state close to a plane, it is possible to manufacture one having a large number of stacked layers and form a high-density integrated circuit. . Since the multilayer ceramic substrate used for this high-density integrated circuit has an internal electrode layer of 100 μm or less, the properties of the ceramic layer in which the internal electrode is interposed and the ceramic protective layer surrounding the ceramic layer are directly related to the circuit. Affects I / O signals. The ceramic substrate composition used for the substrate of the second method includes Al 2 O 3 powder and 15w.
There are those in which glass powder of t% or less is fixed with an inorganic binder, and those in which Pb and B are mixed in an Al 2 O 3 —SiO 2 system and fired at a low temperature.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来の第2の方法のAl23粉末と15wt%以下のガラ
ス粉末を無機バインダ−で固定したものは、焼成温度が
1450〜1600℃と極めて高いので、回路を構成す
る材料もこの焼成温度で劣化しないMo、W等の高価な
ものを使用し、又、還元雰囲気で焼成する必要があるの
で作業性が劣った。Al23−SiO2系にPbやBを
10wt%程度混入させ低温で焼成したものは、セラミ
ック層の内部ポア、すなわち空孔率が比較的大きく、よ
って内部電極が介在しているセラミック層の表面粗さが
大きくなり、誘電正接が悪化する傾向がある。セラミッ
ク層の内部ポア、すなわち空孔率を小さくするために
は、PbやBを20wt%以上混入させる必要があるた
めに、焼成収縮率が大きくなり、セラミック層と、内部
電極との焼成収縮挙動が異なり、層間に剥離が生じる。
又、温度変化に対する静電容量の変化率(以下、TCC
と記す)が大きくなるという問題点があった。
However, the Al 2 O 3 powder of the second conventional method and the glass powder of 15 wt% or less fixed by an inorganic binder have an extremely high firing temperature of 1450 to 1600 ° C. Since the cost is high, expensive materials such as Mo and W, which do not deteriorate at this firing temperature, are used as the material for forming the circuit, and the workability is poor because firing is required in a reducing atmosphere. What is mixed with Pb or B in an Al 2 O 3 —SiO 2 system at about 10 wt% and fired at a low temperature has a ceramic layer in which internal pores, that is, porosity is relatively large, and thus an internal electrode is interposed. Surface roughness is increased, and the dielectric loss tangent tends to be deteriorated. In order to reduce the internal pores of the ceramic layer, that is, the porosity, it is necessary to mix Pb and B in an amount of 20 wt% or more, so that the firing shrinkage rate becomes large, and the firing shrinkage behavior between the ceramic layer and the internal electrode. However, peeling occurs between the layers.
In addition, the rate of change of capacitance with respect to temperature change (hereinafter TCC
However, there is a problem that it becomes large.

【0004】本発明は、上記従来の問題点を解決するも
ので、極めて低い温度、すなわち750〜950℃で焼
成でき、Au、Ag、Ag−Pd、Cu等ペ−ストを内
部電極として使用することが可能な、しかも体積固有抵
抗率、誘電率、誘電正接、絶縁破壊強度、曲げ強度等、
導体、抵抗体等の電子回路を多層に形成する多層配線基
板としての諸特性を充足し、さらに、TCCが±0pp
m/℃〜100ppm/℃と調整可能な多層セラミック
基板を提供するものである。
The present invention solves the above-mentioned conventional problems. It can be fired at an extremely low temperature, that is, 750 to 950 ° C., and a paste such as Au, Ag, Ag-Pd, Cu is used as an internal electrode. It is possible to achieve volume resistivity, dielectric constant, dielectric loss tangent, dielectric breakdown strength, bending strength, etc.
Satisfies various characteristics as a multilayer wiring board for forming electronic circuits such as conductors and resistors in multiple layers, and has a TCC of ± 0 pp
The present invention provides a multilayer ceramic substrate that can be adjusted to m / ° C to 100 ppm / ° C.

【0005】[0005]

【課題を解決するための手段】この課題を解決するため
の本発明の多層セラミック基板は、内部電極を有する多
層セラミック基板の、内部電極が介在するセラミック層
の構造が、セラミック保護層の構造と異なる多層セラミ
ック基板である。具体的には、内部電極が介在するセラ
ミック層の、内部電極から5μm〜100μmの範囲に
おける構造が、セラミック保護層の構造と異なり、内部
電極が介在するセラミック層の空孔率が5.00%以
下、セラミック保護層の空孔率が5.00〜10.00
%の範囲である。さらに内部電極を有する多層セラミッ
ク基板の、内部電極が介在するセラミック層のセラミッ
ク組成が、セラミック保護層のセラミック組成と異なる
多層セラミック基板であり、内部電極が介在するセラミ
ック層のセラミック組成が、Al23−SiO2−Ca
O−ZnO−TiO2−B23 −MgO系、又は、Al
23−SiO2−CaO−SrO−ZrO2−BaO−B
23−TiO2系、セラミック保護層のセラミック組成
が、Al23−SiO2−PbO−B23 −CaO−M
gO−Na2O−K2O−TiO2系、又は、Al23
SiO2−SrO−ZrO2−BaO−B23−TiO2
系、と異なる多層セラミック基板である。
To solve this problem, a multilayer ceramic substrate of the present invention is a multilayer ceramic substrate having internal electrodes, wherein the structure of the ceramic layer in which the internal electrodes are interposed is the same as the structure of the ceramic protective layer. Different multilayer ceramic substrates. Specifically, the structure of the ceramic layer in which the internal electrode is interposed in the range of 5 μm to 100 μm from the internal electrode is different from the structure of the ceramic protective layer, and the porosity of the ceramic layer in which the internal electrode is interposed is 5.00%. Hereinafter, the porosity of the ceramic protective layer is 5.00 to 10.00.
% Range. Further, in the multilayer ceramic substrate having internal electrodes, the ceramic composition of the ceramic layer in which the internal electrodes are interposed is different from the ceramic composition of the ceramic protective layer, and the ceramic composition of the ceramic layer in which the internal electrodes are interposed is Al 2 O 3 -SiO 2 -Ca
O-ZnO-TiO 2 -B 2 O 3 -MgO based, or, Al
2 O 3 -SiO 2 -CaO-SrO -ZrO 2 -BaO-B
2 O 3 -TiO 2 system, ceramic composition of the ceramic protective layer, Al 2 O 3 -SiO 2 -PbO -B 2 O 3 -CaO-M
gO-Na 2 O-K 2 O-TiO 2 system, or, Al 2 O 3 -
SiO 2 -SrO-ZrO 2 -BaO- B 2 O 3 -TiO 2
It is a multi-layer ceramic substrate different from that of the system.

【0006】各項目の限定理由を以下に述べる。内部電
極が介在する5μm以下のセラミック層は、約6μm前
後のシ−ト作製、積層化が困難であるために、多層セラ
ミック基板自体の構成が不可能である。内部電極が介在
するセラミック層の構造と、内部電極から100μm以
上の層間を有する、内部電極が介在するセラミック層の
構造と異なる構造を持つセラミック保護層からなる多層
セラミック基板の構造は、それぞれのセラミック層の焼
成収縮挙動が異なるために焼成時に層間の剥離が生じ、
好ましくない。
The reasons for limiting each item will be described below. It is difficult to form a multilayer ceramic substrate itself because it is difficult to manufacture and laminate a sheet having a thickness of about 6 μm or less with a ceramic layer of 5 μm or less with an internal electrode interposed. The structure of the ceramic layer in which the internal electrode is interposed and the structure of the multilayer ceramic substrate including the ceramic protective layer having a layer having a thickness of 100 μm or more from the internal electrode and different from the structure of the ceramic layer in which the internal electrode is interposed are Due to the different firing shrinkage behavior of layers, peeling between layers occurs during firing,
Not preferable.

【0007】内部電極が介在するセラミック層の空孔率
は、5.00%以下が望ましい。5.00%以上の空孔
率では、セラミック層の内部ポアが比較的多い為、内部
電極が介在しているセラミック層の表面粗さが大きくな
り、誘電正接が悪化し、直接回路への入出力信号へ悪影
響を及ぼす。
The porosity of the ceramic layer in which the internal electrodes are interposed is preferably 5.00% or less. When the porosity is 5.00% or more, the internal pores of the ceramic layer are relatively large, so that the surface roughness of the ceramic layer in which the internal electrodes are interposed becomes large, the dielectric loss tangent deteriorates, and the direct entry into the circuit is prevented. It adversely affects the output signal.

【0008】セラミック保護層の空孔率は、内部電極が
介在するセラミック層、及びセラミック保護層の焼成収
縮挙動を安定化させるために、5.00%以上が望まし
い。空孔率が10.00%以上であると多層セラミック
基板の機械的強度が低下するために好ましくない。
The porosity of the ceramic protective layer is preferably 5.00% or more in order to stabilize the firing shrinkage behavior of the ceramic layer in which the internal electrodes are interposed and the ceramic protective layer. A porosity of 10.00% or more is not preferable because the mechanical strength of the multilayer ceramic substrate decreases.

【0009】内部電極が介在するセラミック層のセラミ
ック組成は、極めて低い温度、すなわち750〜950
℃で焼成でき、空孔率の制御、及びTCCの調整が容易
なAl23−SiO2−CaO−ZnO−TiO2−B2
3−MgO系、又は、Al23−SiO2−CaO−S
rO−ZrO2−BaO−B23−TiO2系のセラミッ
ク組成が望ましい。
The ceramic composition of the ceramic layer interposing the internal electrodes has an extremely low temperature, that is, 750 to 950.
Al 2 O 3 —SiO 2 —CaO—ZnO—TiO 2 —B 2 which can be fired at ℃, and whose porosity can be controlled and TCC can be easily adjusted.
O 3 -MgO based, or, Al 2 O 3 -SiO 2 -CaO -S
rO-ZrO 2 -BaO-B 2 O 3 -TiO 2 based ceramic composition is desirable.

【0010】セラミック保護層のセラミック組成は、極
めて低い温度、すなわち750〜950℃で焼成でき、
空孔率が5.00〜10.00%と制御可能な、さらに
多層セラミック基板の主構成材料となる、比較的機械的
強度の大きく、TCCの調整が容易な、Al23−Si
2−PbO−B23−CaO−MgO−Na2O−K 2
O−TiO2系、又は、Al23−SiO2−SrO−Z
rO2 −BaO−B2 3−TiO2 系のセラミック組成
が望ましい。
The ceramic composition of the ceramic protective layer is extremely
Can be fired at a very low temperature, that is, 750 to 950 ° C,
Porosity can be controlled to 5.00 to 10.00%, and
Relatively mechanical, the main constituent material of multilayer ceramic substrates
Al with high strength and easy TCC adjustment2O3-Si
O2-PbO-B2O3-CaO-MgO-Na2OK 2
O-TiO2System or Al2O3-SiO2-SrO-Z
rO2 -BaO-B2O 3-TiO2 System ceramic composition
Is desirable.

【0011】[0011]

【作用】この構成によって、従来に比べ極めて低い温
度、すなわち750〜950℃で焼成でき、厚膜技術で
広く使用されているAu、Ag、Ag−Pd、Cu等の
ペ−ストの内部電極としての適用を可能とし、又、その
多層セラミック基板は、機械的強度が大きく、熱伝導率
に優れ、誘電率が比較的小さく、絶縁抵抗が大きく、耐
湿性に優れており、特に内部電極が介在しているセラミ
ック層の空孔率が小さいので、セラミック層の表面粗さ
が小さくなるために誘電正接を小さくすることができ
る。さらに、セラミック組成の比率の調整により、TC
Cの制御を容易にすることができる。
With this structure, it can be fired at a temperature extremely lower than the conventional one, that is, at 750 to 950 ° C., and it can be used as an internal electrode of a paste such as Au, Ag, Ag-Pd, Cu which is widely used in thick film technology. In addition, the multilayer ceramic substrate has high mechanical strength, excellent thermal conductivity, relatively low dielectric constant, large insulation resistance, and excellent moisture resistance. Since the porosity of the ceramic layer is small, the surface roughness of the ceramic layer is small, so that the dielectric loss tangent can be small. Furthermore, by adjusting the ratio of the ceramic composition, TC
The control of C can be facilitated.

【0012】[0012]

【実施例】以下本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.

【0013】まず内部電極が介在するセラミック層を作
製する原料のガラスフリットは、wt%で、Al23
45、SiO2 27、ZnO 8.1、TiO2 8.
1、CaO 8.0、B23 2.5、MgO 1.
3、の組成になるように、通常の方法により各原料を調
合し、1400〜1500℃の温度にて撹拌しながら溶
融し、溶融後、水砕又はフレ−ク状とし、ガラスフリッ
トを製造した。
First, the glass frit, which is a raw material for forming the ceramic layer with the internal electrodes interposed, is Al 2 O 3 in wt%.
45, SiO 2 27, ZnO 8.1, TiO 2 8.
1, CaO 8.0, B 2 O 3 2.5, MgO 1.
Each raw material was prepared by a usual method so as to have the composition of 3, and melted with stirring at a temperature of 1400 to 1500 ° C, and after melting, granulated or flaked to prepare a glass frit. .

【0014】次に、このガラスフリットとチタン酸塩の
CaTiO3 が、それぞれ85wt%、15wt%にな
るように秤量し、ボ−ルミルにて粉砕、混合し本発明の
組成物を得た。この粉砕混合した組成物に、バインダ−
を10wt%添加し造粒、成形後、950℃にて15分
焼成した。この焼成体の相対密度を測定したところ、9
9.98%であったので、直径30mm、厚み0.35
mmに加工後、Ag電極を焼き付け、TCCを測定した
ところ、−25℃〜+85℃にて±0ppm/℃であっ
た。そこで、この粉砕混合した組成物に種々のバインダ
−や可塑剤、溶剤を添加、混練して粘度10ps〜30
psのペ−ストを作製した。このペ−ストを常法のドク
タ−法により、厚み0.05mmのグリ−ンシ−トとし
た。
Next, the glass frit and CaTiO 3 of titanate were weighed so as to be 85 wt% and 15 wt%, respectively, and pulverized and mixed with a ball mill to obtain a composition of the present invention. A binder was added to the pulverized and mixed composition.
Was added for 10 minutes by weight, granulated and molded, and then fired at 950 ° C. for 15 minutes. The relative density of this fired body was measured and found to be 9
Since it was 9.98%, the diameter is 30 mm and the thickness is 0.35.
After processing to mm, the Ag electrode was baked and the TCC was measured. As a result, it was ± 0 ppm / ° C at -25 ° C to + 85 ° C. Therefore, various binders, plasticizers, and solvents are added to this pulverized and mixed composition and kneaded to obtain a viscosity of 10 ps to 30
A ps paste was made. This paste was made into a green sheet having a thickness of 0.05 mm by a conventional doctor method.

【0015】次に、セラミック保護層を作製する原料の
ガラスフリットは、wt%で、SiO2 22.0、P
bO 8.1、B23 2.7、CaO 3.6、Mg
O1.35、Na2O 1.35、K2O 0.9、Ti
2 5.0 の組成になるように、通常の方法により
各原料を調合し、1400〜1500℃の温度にて撹拌
しながら溶融し、溶融後、水砕又はフレ−ク状とし、A
2355wt%を添加し、ガラスフリットを製造し
た。
Next, the glass frit as a raw material for producing the ceramic protective layer is SiO 2 22.0, P in wt%.
bO 8.1, B 2 O 3 2.7, CaO 3.6, Mg
O1.35, Na 2 O 1.35, K 2 O 0.9, Ti
Each raw material was blended by a usual method so as to have a composition of O 2 5.0, melted with stirring at a temperature of 1400 to 1500 ° C., and after melting, granulated or flaked, and A
A glass frit was manufactured by adding 55 wt% of 1 2 O 3 .

【0016】次に、このガラスフリットとチタン酸塩の
CaTiO3が、それぞれ85wt%、15wt%にな
るように秤量し、ボ−ルミルにて粉砕、混合し本発明の
組成物を得た。この粉砕混合した組成物に、バインダ−
を10wt%添加し造粒、成形後、950℃にて15分
焼成した。この焼成体の相対密度を測定したところ、9
9.98%であったので、直径30mm、厚み0.35
mmに加工後、Ag電極を焼き付け、TCCを測定した
ところ、−25℃〜+85℃にて±0ppm/℃であっ
た。そこで、この粉砕混合した組成物に種々のバインダ
−や可塑剤、溶剤を添加、混練して粘度10ps〜30
psのペ−ストを作製した。このペ−ストを常法のドク
タ−法により、厚み0.05mmのグリ−ンシ−トとし
た。 次に、内部電極が介在するセラミック層となるグ
リ−ンシ−トに、スクリ−ン印刷法にてAgペ−ストを
約10μm印刷し、セラミック保護層となるグリ−ンシ
−トと回路が構成されるようにそれぞれのシ−トを積層
し、その後、35℃にて約50トンの圧力にて熱圧着さ
せ、950℃で15分焼成した。
Next, the glass frit and CaTiO 3 of titanate were weighed so as to be 85 wt% and 15 wt%, respectively, and pulverized and mixed with a ball mill to obtain a composition of the present invention. A binder was added to the pulverized and mixed composition.
Was added for 10 minutes by weight, granulated and molded, and then fired at 950 ° C. for 15 minutes. The relative density of this fired body was measured and found to be 9
Since it was 9.98%, the diameter is 30 mm and the thickness is 0.35.
After processing to mm, the Ag electrode was baked and the TCC was measured. As a result, it was ± 0 ppm / ° C at -25 ° C to + 85 ° C. Therefore, various binders, plasticizers, and solvents are added to this pulverized and mixed composition and kneaded to obtain a viscosity of 10 ps to 30
A ps paste was made. This paste was made into a green sheet having a thickness of 0.05 mm by a conventional doctor method. Then, an Ag paste is printed by about 10 μm on the green sheet which becomes the ceramic layer in which the internal electrodes are interposed by a screen printing method to form a green sheet which becomes the ceramic protective layer and a circuit. Each sheet was laminated as described above, and then thermocompression-bonded at 35 ° C. under a pressure of about 50 tons, and baked at 950 ° C. for 15 minutes.

【0017】焼成した基板の各種特性を測定したとこ
ろ、体積固有抵抗率101416Ω、誘電率10〜15、
誘電正接≦5×10-4、絶縁破壊強度700〜900k
V/cm、曲げ強度1500〜2000kg/cm2
TCC(−25℃〜+85℃)±0ppm/℃であっ
た。即ち、導体、抵抗体等の電子回路を多層に形成する
多層配線基板としての特性を満足する結果を得た。図1
に本発明の実施例における多層セラミック基板の断面図
を示す。
When various characteristics of the fired substrate were measured, the volume resistivity was 10 14 to 16 Ω, the dielectric constant was 10 to 15,
Dielectric loss tangent ≤ 5 × 10 -4 , dielectric breakdown strength 700-900k
V / cm, bending strength 1500-2000 kg / cm 2 ,
It was TCC (-25 degreeC- + 85 degreeC) +/- 0 ppm / degreeC. That is, results were obtained that satisfied the characteristics as a multilayer wiring board in which electronic circuits such as conductors and resistors were formed in multiple layers. Figure 1
A cross-sectional view of the multilayer ceramic substrate in the embodiment of the present invention is shown in FIG.

【0018】図1において、1は、内部電極、2は、内
部電極が介在するセラミック層、3は、セラミック保護
層である。4は、5〜10μmの内部ポアである。この
内部電極が介在するセラミック層、セラミック保護層の
空孔率をそれぞれ測定したところ、3.5%、8.0%
と空孔率が異なり、内部電極が介在するセラミック層
と、セラミック保護層の層間は、約43μmと満足する
結果を得た。
In FIG. 1, 1 is an internal electrode, 2 is a ceramic layer in which the internal electrode is interposed, and 3 is a ceramic protective layer. 4 is an internal pore of 5 to 10 μm. The porosities of the ceramic layer and the ceramic protective layer in which the internal electrodes are interposed were measured to be 3.5% and 8.0%, respectively.
The porosity is different from the above, and the space between the ceramic layer in which the internal electrode is interposed and the ceramic protective layer is about 43 μm, which is a satisfactory result.

【0019】さらに、内部電極が介在するセラミック層
を作製する原料のガラスフリットがwt%で、Al23
8.5、SiO2 27.0、CaO 8.5、Sr
O12.0、ZrO2 25.0、BaO 11.0、
TiO2 3.0、B235.0、の組成になるように
各原料を調合し、上記方法と同様にしてガラスフリット
を製造した。次に、このガラスフリットとチタン酸塩の
CaTiO3が、それぞれ90wt%、10wt%にな
るように秤量し、ボ−ルミルにて粉砕、混合し本発明の
組成物を得た。この粉砕混合した組成物に、バインダ−
を10wt%添加し造粒、成形後、900℃にて15分
焼成した。この焼成体の相対密度を測定したところ、9
9.98%であったので、直径30mm、厚み0.35
mmに加工後、Ag電極を焼き付け、TCCを測定した
ところ、−25℃〜+85℃にて+30ppm/℃であ
った。そこで、この粉砕混合した組成物に種々のバイン
ダ−や可塑剤、溶剤を添加、混練して粘度10ps〜3
0psのペ−ストを作製した。このペ−ストを常法のド
クタ−法により、厚み0.05mmのグリ−ンシ−トと
した。
Further, the glass frit as a raw material for producing the ceramic layer in which the internal electrodes are interposed is wt%, and Al 2 O 3 is used.
8.5, SiO 2 27.0, CaO 8.5, Sr
O12.0, ZrO 2 25.0, BaO 11.0,
The respective raw materials were blended so as to have a composition of TiO 2 3.0 and B 2 O 3 5.0, and a glass frit was manufactured in the same manner as the above method. Next, the glass frit and CaTiO 3 of titanate were weighed so as to be 90 wt% and 10 wt%, respectively, and pulverized and mixed with a ball mill to obtain a composition of the present invention. A binder was added to the pulverized and mixed composition.
Was added at 10 wt%, granulated, molded, and then fired at 900 ° C. for 15 minutes. The relative density of this fired body was measured and found to be 9
Since it was 9.98%, the diameter is 30 mm and the thickness is 0.35.
After processing into mm, the Ag electrode was baked and the TCC was measured. As a result, it was +30 ppm / ° C at -25 ° C to + 85 ° C. Therefore, various binders, plasticizers and solvents are added to the pulverized and mixed composition and kneaded to obtain a viscosity of 10 ps to 3
A 0 ps paste was made. This paste was made into a green sheet having a thickness of 0.05 mm by a conventional doctor method.

【0020】セラミック保護層を作製する原料のガラス
フリットは、wt%で、Al238.5、SiO2
7.0、SrO 12.0、ZrO2 29.0、Ba
O12.5、TiO2 3.0、B23 8.0、の組
成になるように各原料を調合し、上記方法と同様にして
ガラスフリットを製造した。
The glass frit as a raw material for producing the ceramic protective layer was made of Al 2 O 3 8.5 and SiO 2 2 in wt%.
7.0, SrO 12.0, ZrO 2 29.0, Ba
The respective raw materials were blended so as to have a composition of O12.5, TiO 2 3.0 and B 2 O 3 8.0, and a glass frit was manufactured in the same manner as the above method.

【0021】次に、このガラスフリットとチタン酸塩の
SrTiO3 が、それぞれ90wt%、10wt%にな
るように秤量し、ボ−ルミルにて粉砕、混合し本発明の
組成物を得た。この粉砕混合した組成物に、バインダ−
を10wt%添加し造粒、成形後、900℃にて、15
分焼成した。この焼成体の相対密度を測定したところ、
99.98%であったので、直径30mm、厚み0.3
5mmに加工後、Ag電極を焼き付け、TCCを測定し
たところ、−25℃〜+85℃にて+30ppm/℃で
あった。そこで、この粉砕混合した組成物に種々のバイ
ンダ−や可塑剤、溶剤を添加、混練して粘度10ps〜
30psのペ−ストを作製した。このペ−ストを常法の
ドクタ−法により、厚み0.05mmのグリ−ンシ−ト
とした。
Next, the glass frit and SrTiO 3 of titanate were weighed so as to be 90 wt% and 10 wt%, respectively, and pulverized by a ball mill and mixed to obtain a composition of the present invention. A binder was added to the pulverized and mixed composition.
Was added at 10 wt%, granulated and molded, then at 900 ° C for 15
Minutes were fired. When the relative density of this fired body was measured,
Since it was 99.98%, the diameter is 30 mm and the thickness is 0.3.
After processing to 5 mm, the Ag electrode was baked and the TCC was measured. As a result, it was +30 ppm / ° C at -25 ° C to + 85 ° C. Therefore, various binders, plasticizers and solvents are added to the pulverized and mixed composition and kneaded to obtain a viscosity of 10 ps to
A 30 ps paste was made. This paste was made into a green sheet having a thickness of 0.05 mm by a conventional doctor method.

【0022】次に、上記方法と同様に内部電極が介在す
るセラミック層となるグリ−ンシ−トに、スクリ−ン印
刷法にてAgペ−ストを約10μm印刷し、セラミック
保護層となるグリ−ンシ−トと回路が構成されるように
それぞれのシ−トを積層し、その後、35℃にて約50
トンの圧力にて熱圧着させ、900℃で15分焼成し
た。
Next, in the same manner as in the above method, a green sheet which becomes a ceramic layer with an internal electrode interposed is printed with an Ag paste to a thickness of about 10 μm by a screen printing method to form a ceramic protective layer. -The sheets are laminated so that the sheet and the circuit are configured, and then at 50C at about 50 ° C.
It was thermocompression bonded at a pressure of ton and baked at 900 ° C. for 15 minutes.

【0023】焼成した基板の各種特性を測定したとこ
ろ、体積固有抵抗率101416Ω、誘電率10〜15、
誘電正接≦5×10-4、絶縁破壊強度700〜900k
V/cm、曲げ強度1500〜2000kg/cm2
TCC(−25℃〜+85℃)+35ppm/℃であっ
た。即ち、導体、抵抗体等の電子回路を多層に形成する
多層配線基板としての特性を満足する結果を得た。
When various characteristics of the fired substrate were measured, the volume resistivity was 10 14 to 16 Ω, the dielectric constant was 10 to 15,
Dielectric loss tangent ≤ 5 × 10 -4 , dielectric breakdown strength 700-900k
V / cm, bending strength 1500-2000 kg / cm 2 ,
It was TCC (-25 degreeC- + 85 degreeC) +35 ppm / degreeC. That is, results were obtained that satisfied the characteristics as a multilayer wiring board in which electronic circuits such as conductors and resistors were formed in multiple layers.

【0024】この内部電極が介在するセラミック層、セ
ラミック保護層の空孔率をそれぞれ測定したところ、
3.0%、7.0%と空孔率が異なり、内部電極が介在
するセラミック層と、セラミック保護層の層間は、約4
3μmと満足する結果を得た。
When the porosities of the ceramic layer and the ceramic protective layer with which the internal electrodes are interposed were measured,
The porosity is different from 3.0% to 7.0%, and there is about 4 between the ceramic layer with the internal electrode and the ceramic protective layer.
A satisfactory result of 3 μm was obtained.

【0025】内部電極が介在するセラミック層を作製す
る原料のガラスフリットが、wt%で、Al23
5、SiO2 27、ZnO 8.1、TiO2 8.
1、CaO 8.0、B23 2.5、MgO 1.
3、の組成において、このガラスフリットとチタン酸塩
のCaTiO3が、それぞれ92wt%、8wt%の場
合の組成、セラミック保護層を作製する原料のガラスフ
リットが、wt%で、Al23 8.5、SiO2
7.0、SrO 12.0、ZrO2 29.0、Ba
O 12.5、TiO2 3.0、B23 8.0、の
組成、及びこのガラスフリットとチタン酸塩のSrTi
3が、それぞれ92wt%、8wt%の組成物で上記
方法と同様にシ−トを作製し、Agペ−ストを印刷、回
路が構成されるようにそれぞれのシ−トを積層、850
℃で15分焼成した。焼成した基板の各種特性を測定し
たところ、体積固有抵抗率、誘電率、誘電正接、絶縁破
壊強度、曲げ強度は、上記と同様の値を得た。TCC
(−25℃〜+85℃)は、+65ppm/℃であっ
た。この内部電極が介在するセラミック層、セラミック
保護層の空孔率をそれぞれ測定したところ、3.5%、
7.0%と空孔率が異なり、内部電極が介在するセラミ
ック層と、セラミック保護層の層間は、約43μmと満
足する結果を得た。 内部電極が介在するセラミック層
を作製する原料のガラスフリットが、 wt%で、Al
23 8.5、SiO2 27.0、CaO 8.5、
SrO12.0、ZrO2 25.0、BaO 11.
0、TiO2 3.0、B23 5.0の組成におい
て、このガラスフリットとチタン酸塩のCaTiO
3が、それぞれ95wt%、5wt%の場合の組成、セ
ラミック保護層を作製す る原料のガラスフリットが、
wt%で、Al23 55.0、SiO2 22. 0、
PbO 8.1、CaO 3.6、MgO 1.35、
Na2O 1.35、K2O 0.9、B23 2.7、
TiO2 5.0の組成、及びこのガラスフリットとチ
タン酸塩のCaTiO3が、それぞれ95wt%、5w
t%の組成物で 上記方法と同様にシ−トを作製し、A
gペ−ストを印刷、回路が構成されるようにそれぞれの
シ−トを積層、800℃で15分焼成した。焼成した基
板の各種特性を測定したところ、体積固有抵抗率、誘電
率、誘電正接、絶縁破壊強度、曲げ強度は、上記と同様
の値を得た。TCC(−25℃〜+85℃)は、+80
ppm/℃であった。
The glass frit, which is a raw material for forming the ceramic layer with the internal electrodes interposed, is Al 2 O 3 4 in wt%.
5, SiO 2 27, ZnO 8.1, TiO 2 8.
1, CaO 8.0, B 2 O 3 2.5, MgO 1.
In the composition of 3, the composition when the glass frit and the CaTiO 3 of the titanate are 92 wt% and 8 wt%, respectively, and the glass frit of the raw material for producing the ceramic protective layer is Al 2 O 3 8 wt% .5, SiO 2 2
7.0, SrO 12.0, ZrO 2 29.0, Ba
The composition of O 12.5, TiO 2 3.0, B 2 O 3 8.0, and SrTi of this glass frit and titanate.
A sheet was made in the same manner as the above method with a composition of O 3 of 92 wt% and 8 wt% respectively, and Ag paste was printed, and the sheets were laminated so that a circuit was formed, and 850
It was baked at 15 ° C for 15 minutes. When various characteristics of the fired substrate were measured, the same values as above were obtained for the volume resistivity, dielectric constant, dielectric loss tangent, dielectric breakdown strength, and bending strength. TCC
(−25 ° C. to + 85 ° C.) was +65 ppm / ° C. The porosities of the ceramic layer and the ceramic protective layer, in which the internal electrodes are interposed, were measured to be 3.5%,
The porosity is different from 7.0%, and a satisfactory result of about 43 μm was obtained between the ceramic layer in which the internal electrode is interposed and the ceramic protective layer. The glass frit as a raw material for producing the ceramic layer in which the internal electrode is interposed is wt% and is Al.
2 O 3 8.5, SiO 2 27.0, CaO 8.5,
SrO 12.0, ZrO 2 25.0, BaO 11.
0, TiO 2 3.0, B 2 O 3 5.0, the glass frit and the CaTiO 3 titanate.
When 3 is 95 wt% and 5 wt% respectively, the composition and the glass frit of the raw material for producing the ceramic protective layer are
Al 2 O 3 55.0, SiO 2 22. 0,
PbO 8.1, CaO 3.6, MgO 1.35,
Na 2 O 1.35, K 2 O 0.9, B 2 O 3 2.7,
The composition of TiO 2 5.0 and the glass frit and CaTiO 3 of titanate are 95 wt% and 5 w, respectively.
A sheet was prepared with the composition of t% in the same manner as described above, and A
g paste was printed, each sheet was laminated so as to form a circuit, and baked at 800 ° C. for 15 minutes. When various characteristics of the fired substrate were measured, the same values as above were obtained for the volume resistivity, dielectric constant, dielectric loss tangent, dielectric breakdown strength, and bending strength. TCC (-25 ° C to + 85 ° C) is +80
It was ppm / ° C.

【0026】この内部電極が介在するセラミック層、セ
ラミック保護層の空孔率をそれぞれ測定したところ、
3.0%、8.0%と空孔率が異なり、内部電極が介在
するセラミック層と、セラミック保護層の層間は、約4
3μmと満足する結果を得た。
The porosities of the ceramic layer and the ceramic protective layer in which the internal electrodes are interposed were measured.
The porosity is different from 3.0% to 8.0%, and the space between the ceramic layer in which the internal electrodes are interposed and the ceramic protective layer is about 4%.
A satisfactory result of 3 μm was obtained.

【0027】さらに、Au、Ag−Pd、Cu等のペ−
ストを内部電極とし回路を構成した場合にも上記と同様
の結果を得た。
Further, a sheet of Au, Ag-Pd, Cu or the like is used.
The same results as above were obtained when the circuit was constructed using the strike as an internal electrode.

【0028】なお、上記セラミック組成以外では、チタ
ン酸塩がガラスフリットと固溶体を形成するためにTC
Cの調整、制御が困難であった。以上の結果を(表1)
〜(表3)に示す。
In addition to the above ceramic composition, since the titanate forms a solid solution with the glass frit, TC is used.
It was difficult to adjust and control C. The above results (Table 1)
~ (Table 3).

【0029】[0029]

【表1】 [Table 1]

【0030】[0030]

【表2】 [Table 2]

【0031】[0031]

【表3】 [Table 3]

【0032】本発明は(表1)〜(表3)からわかるよ
うに、従来の多層セラミック基板と比較して極めて低い
温度で焼成が実現できるようになり、TCCの調整が容
易である。
According to the present invention, as can be seen from (Table 1) to (Table 3), firing can be realized at an extremely low temperature as compared with the conventional multilayer ceramic substrate, and the TCC can be easily adjusted.

【0033】[0033]

【発明の効果】本発明は、上記従来の問題点を解決する
もので、極めて低い温度、すなわち750〜950℃で
焼成でき、Au、Ag、Ag−Pd、Cu等ペ−ストを
内部電極として使用することが可能な、しかも体積固有
抵抗率、誘電率、誘電正接、絶縁破壊強度、曲げ強度
等、導体、抵抗体等の電子回路を多層に形成する多層配
線基板としての諸特性を満足し、さらに、TCCが±0
ppm/℃〜100ppm/℃と調整が容易な多層セラ
ミック基板を実現できるものである。
The present invention solves the above-mentioned problems of the prior art. It can be fired at an extremely low temperature, that is, 750 to 950 ° C, and a paste such as Au, Ag, Ag-Pd, Cu is used as an internal electrode. It can be used, and satisfies various characteristics such as volume resistivity, dielectric constant, dielectric loss tangent, dielectric breakdown strength, bending strength, etc. as a multilayer wiring board for forming electronic circuits such as conductors and resistors in multiple layers. , Furthermore, TCC is ± 0
It is possible to realize a multilayer ceramic substrate that can be easily adjusted to ppm / ° C. to 100 ppm / ° C.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における多層セラミック基板の
断面図
FIG. 1 is a sectional view of a multilayer ceramic substrate according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 内部電極 2 内部電極が介在するセラミック層 3 セラミック保護層 4 内部ポア 1 Internal Electrode 2 Ceramic Layer with Internal Electrode 3 Ceramic Protective Layer 4 Internal Pore

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/15 9355−4M H01L 23/14 C ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H01L 23/15 9355-4M H01L 23/14 C

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】内部電極を有する多層セラミック基板の、
内部電極が介在するセラミック層の構造が、前記セラミ
ック層近傍に位置するセラミック保護層の構造と異なる
ことを特徴とする多層セラミック基板。
1. A multilayer ceramic substrate having internal electrodes,
A multilayer ceramic substrate, wherein a structure of a ceramic layer in which an internal electrode is interposed is different from a structure of a ceramic protective layer located near the ceramic layer.
【請求項2】内部電極が介在するセラミック層の空孔率
が5.00%以下、セラミック保護層の空孔率が5.0
0〜10.00%の範囲であることを特徴とする請求項
1記載の多層セラミック基板。
2. The porosity of the ceramic layer interposing the internal electrodes is 5.00% or less, and the porosity of the ceramic protective layer is 5.0.
The multilayer ceramic substrate according to claim 1, characterized in that it is in the range of 0 to 10.00%.
【請求項3】内部電極が介在するセラミック層の、内部
電極から5μm〜100μmの範囲における構造が、セ
ラミック保護層の構造と異なることを特徴とする請求項
1記載の多層セラミック基板。
3. The multilayer ceramic substrate according to claim 1, wherein the structure of the ceramic layer in which the internal electrode is interposed is within a range of 5 μm to 100 μm from the internal electrode, which is different from the structure of the ceramic protective layer.
【請求項4】内部電極が介在するセラミック層の、内部
電極から5μm〜100μmの範囲における構造が、セ
ラミック保護層の構造と異なることを特徴とする請求項
2記載の多層セラミック基板。
4. The multilayer ceramic substrate according to claim 2, wherein the structure of the ceramic layer in which the internal electrode is interposed is 5 μm to 100 μm from the internal electrode, which is different from the structure of the ceramic protective layer.
【請求項5】内部電極を有する多層セラミック基板の、
内部電極が介在するセラミック層のセラミック組成が、
セラミック保護層のセラミック組成と異なることを特徴
とする請求項1記載の多層セラミック基板。
5. A multilayer ceramic substrate having internal electrodes,
The ceramic composition of the ceramic layer in which the internal electrodes intervene,
The multilayer ceramic substrate according to claim 1, wherein the ceramic composition of the ceramic protective layer is different from that of the ceramic protective layer.
【請求項6】内部電極を有する多層セラミック基板の、
内部電極が介在するセラミック層のセラミック組成が、
Al23−SiO2−CaO−ZnO−TiO2−B23
−MgO系、又は、Al23 −SiO2−CaO−S
rO−ZrO2−BaO−B23−TiO2 系、セラミ
ック保護層のセラミック組成が、Al23 −SiO2
−PbO−B23−CaO−MgO−Na2O−K2O−
TiO2系、又は、Al23−SiO2−SrO−ZrO
2−BaO−B23−TiO2系、と異なることを特徴と
する請求項5記載の多層セラミック基板。
6. A multilayer ceramic substrate having internal electrodes,
The ceramic composition of the ceramic layer in which the internal electrodes intervene,
Al 2 O 3 -SiO 2 -CaO- ZnO-TiO 2 -B 2 O 3
-MgO system, or, Al 2 O 3 -SiO 2 -CaO -S
rO-ZrO 2 -BaO-B 2 O 3 -TiO 2 system, ceramic composition of the ceramic protective layer, Al 2 O 3 -SiO 2
-PbO-B 2 0 3 -CaO- MgO-Na 2 O-K 2 O-
TiO 2 system, or, Al 2 O 3 -SiO 2 -SrO -ZrO
The multilayer ceramic substrate according to claim 5, which is different from the 2- BaO-B 2 O 3 -TiO 2 system.
【請求項7】内部電極が介在するセラミック層の、内部
電極層から5μm〜100μmの範囲におけるセラミッ
ク組成が、セラミック保護層のセラミック組成と異なる
ことを特徴とする請求項6記載の多層セラミック基板。
7. The multilayer ceramic substrate according to claim 6, wherein the ceramic composition of the ceramic layer in which the internal electrode is interposed is different from the ceramic composition of the ceramic protective layer in the range of 5 μm to 100 μm from the internal electrode layer.
【請求項8】内部電極が介在するセラミック層の空孔率
が5.00%以下、セラミック保護層の空孔率が5.0
0〜10.00%の範囲であることを特徴とする請求項
7記載の多層セラミック基板。
8. The porosity of the ceramic layer in which the internal electrodes are interposed is 5.00% or less, and the porosity of the ceramic protective layer is 5.0.
The multilayer ceramic substrate according to claim 7, which is in a range of 0 to 10.00%.
JP17959992A 1992-07-07 1992-07-07 Multilayer ceramic board Pending JPH0624857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17959992A JPH0624857A (en) 1992-07-07 1992-07-07 Multilayer ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17959992A JPH0624857A (en) 1992-07-07 1992-07-07 Multilayer ceramic board

Publications (1)

Publication Number Publication Date
JPH0624857A true JPH0624857A (en) 1994-02-01

Family

ID=16068560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17959992A Pending JPH0624857A (en) 1992-07-07 1992-07-07 Multilayer ceramic board

Country Status (1)

Country Link
JP (1) JPH0624857A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6582128B2 (en) 2000-11-24 2003-06-24 Nsk Ltd. Ball bearing and bearing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6582128B2 (en) 2000-11-24 2003-06-24 Nsk Ltd. Ball bearing and bearing device

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