JPH06245190A - Encoding and framing device for digital video signal - Google Patents

Abstract

PURPOSE:To improve picture quality with a simple circuit by stuffing the coded output of a first frame whose importance is higher in a fixed section at the time of stuffing the buffering unit of intra-two-frame code output in a sync block. CONSTITUTION:The output of a subtracting circuit 4 is supplied to a DCT circuit 5 and AC components in coefficient data are supplied to a quantization circuit 6 and quantized. A data amount generated by DCT and variable length encoding is buffering-processed so as to make the generated data amount of the buffering unit equal to or less than a target value. The output of the circuit 6 is supplied to a variable encoding circuit 8, Huffman-encoding or the like are performed and code signals from the circuit 8 are supplied to a poststage. In a framing circuit 9, the coded output of the AC components of the first frame is stuffed in the stipulated data section of the sync block starting from low-band components and the coded output of the AC components of a second frame and the overflowing coded output of the AC components of the first frame are stuffed in the blank data section of the sync block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal coding and framing apparatus which is used for compression coding a digital video signal and framing a coded output into a data structure of a predetermined format.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in a digital video signal is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, one frame image is converted into, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable-length coding processing such as run-length coding and Huffman coding. At the time of transmission, in order to facilitate data processing on the reproducing side, a code signal, which is an encoded output, is inserted into the data area of a sync block of a certain length, and a sync signal, I
The sync block to which the D signal is added is framed.

A digital VTR using a magnetic tape,
In a disc recording device or the like using a disc-shaped recording medium, it is usual that one field or one frame of video data is recorded on a plurality of tracks. However, when a variable length output is formed as in the DCT described above, there is a problem that the amount of data in these predetermined periods fluctuates, which makes editing in field or frame units troublesome. For this reason, fixed lengthening processing (referred to as buffering processing) is performed to reduce the amount of data in the predetermined period to the target value or less. The predetermined period may be one field and one frame, but in order to reduce the required memory capacity, the data amount in a shorter period (referred to as a buffering unit) is controlled, resulting in one field and one frame.
The amount of frame data is fixed.

Regarding the standard resolution video signal (referred to as SD-H signal) such as the 525/60 system, the transmission rate of the recording / reproducing data is, for example, 25 MBPS. If this transmission rate could be halved to 12.5 MBPS, the amount of tape consumed could be halved. For example, at a predetermined track pitch, two rotary heads alternately form tracks, whereas the tape speed can be halved and only one rotary head can form tracks.

Further, since the number of pixels in the horizontal direction and the number of horizontal scanning lines of the high resolution video signal (referred to as HD signal) are about twice as large as those of the SD-H signal, the amount of information is high. It is four times that of the SD signal. In order to record / reproduce such an HD signal, it is desirable to perform encoding with a compression rate as high as possible. As one of the methods for increasing the compression rate, 10
Intra-frame coding is performed every ~ 15 frames,
For the remaining frames, a method of coding the frame difference is known. However, in the case of the digital VTR, since it is necessary to edit in a shorter frame, the encoding in units of such many frames is inappropriate. If the intra 2 frames are encoded, editing can be performed in units of 2 frames. In the above-described fixed length of the encoded output data amount, the buffering process is performed for the period of two frames.

[0007]

It is assumed that intra 2 frames are encoded and the resulting encoded output buffering units are packed in a plurality of, for example, 5 sync blocks. Enabled per sync block /
Considering the variable speed reproduction operation that is determined to be invalid, it is efficient that the sync block includes one or more integer macroblocks. A macroblock consists of four luminance signal blocks and two color difference signal blocks occupying the same position, and when the reproduction data of these six blocks can be obtained, the image of this block can be restored. is there.

In the case of arranging a buffering unit, for example, 10 macroblocks including the coded output of the first frame and the coded output of the second frame of the intra 2 frame in 5 sync blocks, each sync A data section for two macroblocks is set in each block. However, between the first and second frames,
The importance of the encoded output is different. That is, since the encoded output of the first frame is the intra-frame encoded output, it is possible to obtain the decoded data from itself, whereas the encoded output of the second frame is only the decoded data of the difference. If not obtained, the decoded data can be obtained only by adding the decoded difference data to the decoded data of the first frame.

As described above, the data amount of the encoded output of the intra 1 frame can be halved for the encoding of the intra 2 frame. Therefore, it is necessary to pack the coded outputs of twice as many macroblocks in the data section of 5 sync blocks. The configuration of the sync block is set in consideration of minimizing the influence of error propagation, but the fact that the section length of the data packed in each block is half that of the intra-one frame reduces the influence of error propagation. It causes problems that are more strongly affected. If the difference in importance is not taken into consideration, this problem occurs equally for both the first frame and the second frame.

Therefore, an object of the present invention is to enable framing that matches the difference in importance of the coded outputs of two frames when the intra 2 frame coding is adopted to achieve a high compression rate. An object is to provide a coding and framing device for a digital video signal.

[0011]

The invention according to claim 1 is
Compression coding the data amount of the input digital video signal,
An encoding and framing device adapted to frame and transmit an encoded output into a predetermined data format, and an orthogonal transformation circuit for transform encoding for each encoding block of a predetermined size, and an orthogonal transformation An adaptive quantization circuit for controlling the data amount of the coded output in the fixed length unit so that the data amount of the encoded output is contained in the data areas of the plurality of sync blocks, and a variable circuit coupled with the adaptive quantization circuit. Long coding circuit, circuit for locally decoding output of adaptive quantization circuit, frame memory for storing locally decoded data, decoded data of first frame from frame memory and first frame The frame difference between the following second frame and the second frame is detected for each coding block, and the first class in which the frame difference is smaller than the threshold value and the frame difference in which the frame difference is smaller than the threshold value are detected. The coding block is classified into a threshold second class, a frame difference is given to the orthogonal transform circuit for the first class coding block, and a second frame is applied for the second class coding block. An encoding control circuit for controlling the data of the above to be given to the orthogonal transformation circuit, and a framing circuit for converting the output of the variable length encoding circuit into transmission data of a plurality of sync blocks. Starting from the low-frequency component, the AC output of the AC frame of the first frame is packed into a predetermined data section of the plurality of sync blocks, and the AC output of the second frame and the overflowed first It is characterized by comprising a framing circuit configured to pack the encoded output of the AC component of one frame into the data section of the margin of a plurality of sync blocks. It is an encoding and framing apparatus in a digital video signal to.

[0012]

The data is compressed by encoding the intra 2 frames. A buffering unit composed of encoded outputs of the first and second frames is packed into the data section of, for example, five sync blocks. In this case, the encoded output of the first frame having higher importance is packed into the data section first. After the coded output of the first frame is packed, the coded output of the second frame is packed into the blank data interval generated in the five sync blocks.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR will be described below with reference to the drawings. FIG. 1 shows the configuration of a video data processing circuit provided on the recording side of a digital VTR. In FIG. 1, a digital video signal is supplied to the input terminal indicated by 1. This digital video signal is supplied to the preprocessing circuit 2, and the output signal of the preprocessing circuit 2 is supplied to the blocking and shuffling circuit 3. The preprocessing circuit 2 is a thinning filter, a line-sequentializing circuit, or the like provided to reduce the data rate. In the blocking and shuffling circuit 3,
If the video data in the interlaced scanning order is (8 ×
8) Blocking processing that is converted into data of the block (DCT block) structure and processing that makes the spatial position of video data different from the original within one frame, that is, shuffling is performed. .

The output of the blocking and shuffling circuit 3 is supplied to the subtracting circuit 4, and the output signal of the subtracting circuit 4 is D.
It is supplied to the CT (cosine transform) circuit 5. From the DCT circuit 5, (8 × 8) coefficient data (that is, the DC component D
C, AC component AC coefficient data) is generated. DC component DC of (8 × 8) coefficient data generated in the DCT circuit 5
Is transmitted to the circuit at the subsequent stage without being compressed, and 63 of the alternating current components are supplied to the adaptive quantization circuit 6.

The coefficient data of the AC component is transmitted in order of zigzag scanning from the AC component having a lower order to the AC component having a higher order. Further, the coefficient data for the alternating current is supplied to the data amount estimating device 7. The quantization number QNo corresponding to the quantization step from the estimator 7 is supplied to the quantization circuit 6 and inserted into the recording data.

In the quantizing circuit 6, the AC component in the coefficient data is quantized. That is, the coefficient data for the alternating current is divided by an appropriate quantization step, and the quotient is converted into an integer.
This quantization step is the quantization number QN from the estimator 7.
determined by o. The amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded. Therefore, a buffering process for reducing the amount of generated data in a buffering unit shorter than one field or one frame period to a target value or less. Is done. The reason for shortening the buffering unit is to simplify the buffering circuit, such as reducing the memory capacity for buffering. In this example, the predetermined period (buffering unit)
The quantization step is controlled so that the data generated in step 5 can be contained within 5 sync blocks.

The output of the quantization circuit 6 is the variable length coding circuit 8
And run-length coding, Huffman coding, etc. are performed. For example, the run length, which is the number of consecutive "0" s of coefficient data, and the value of coefficient data are given to a Huffman table stored in the ROM, and a variable length code (encoded output) is given.
Two-dimensional Huffman coding is used to generate The code signal from the variable length coding circuit 8 is supplied to the subsequent stage. The estimator 7 has the same Huffman table as that referred to by the variable length coding circuit 8. This Huffman table generates bit number data of an output code when variable length coding is performed. The estimator 7 determines the optimum quantization step, and the quantization circuit 6 quantizes the coefficient data at this quantization step.

The DCT circuit 5, the adaptive quantization circuit 6, the estimator 7 and the variable length coding circuit 8 in FIG. 1 have a basic configuration, and a process for distinguishing a DCT transform between a still block and a motion block. , A process of varying the quantization step of coefficient data according to the definition (activity) of the block, a process of varying the quantization step according to the order of the coefficient data, a process of parallelizing the encoding of the HD signal, etc. . The result of motion detection (motion flag) and the activity code for identifying the activity are also recorded.

The data (DC component data, variable length coded output, quantization number QNo, motion flag, activity code) generated by the above-described coding process is supplied to the framing circuit 9 in the subsequent stage. In the framing circuit 9, error correction coding processing, conversion processing of recording data into a frame structure, and track shuffling are performed. Recording data appears at the output terminal of the framing circuit 9. The recording data is supplied to the rotary head via the channel encoding circuit and the recording amplifier and recorded on the magnetic tape.

In the present invention, intra 2 frame coding is performed in order to increase the compression rate. That is, the pair POP of the first frame I and the second frame P that are temporally consecutive is the target of encoding. A pair of a block included in the first frame I and a block included in the second frame P and located at the same position as the block of the frame I is an encoding unit. The block of the first frame I is D as described above.
It is compressed by CT and variable length coding processing. A difference is calculated for each pixel between the locally decoded output regarding the first frame and the video data regarding the second frame, and the absolute value of this difference is integrated for each block. The coding of the block of the second frame P is adaptively controlled according to the magnitude of this integrated value. Usually, there is an image correlation between the first frame and the second frame, and the value of the inter-frame difference is small. When this frame difference is DCT and variable length coded, the data amount of the coded output is smaller than that when the original data is coded and output.

In FIG. 1, an inverse quantization circuit 10 connected to the adaptive quantization circuit 6 and an inverse DCT circuit 11 connected to the inverse quantization circuit 10 form a local decoding circuit. The locally decoded data of the first frame I is stored in the frame memory 12. The video data of the second frame P and the decoded data read from the frame memory 12 and passed through the gate circuit 13 are subtracted by the subtraction circuit 4.

The gate circuit 13 is turned on / off by a control signal generated by the encoding control circuit 14. Both the input video data and the data from the frame memory 12 are supplied to the encoding control circuit 14. The coding control circuit 14 also has a function of controlling the number of bits assigned to the frame I and the number of bits assigned to the frame P in the fixed length unit. The bit allocation information is stored in the memory 15. The bit allocation information generated by the current POP is
It is temporarily stored in the memory 15 and applied to the next POP.

In intra 2 frame encoding, when a scene change occurs, the correlation between the first and second frames disappears, the amount of encoded output data can be reduced, and in some cases the amount of data increases rather. The scene change is detected by the detection circuit 16, and the detection result is supplied to the estimator 7. A frame difference between two temporally consecutive frames of the input video signal is detected, and when the frame difference is large to some extent, it is determined that a scene change has occurred. It is not necessary to detect the frame difference of the entire screen, but the frame difference of several lines may be detected.

An example of the encoding control circuit 14 will be described with reference to FIG. The data of the frame I is supplied to the input terminal 21, and the locally decoded data of the frame P is supplied to the input terminal 22. The subtraction circuit 23 subtracts the data of both frames for each pixel to generate a frame difference. An absolute value conversion circuit 24 is connected to the subtraction circuit 23. The frame difference converted into the absolute value is the integrating circuit 25.
And the absolute value of the frame difference for one block is integrated.

The output Ef of the integrating circuit 25 is supplied to the comparing circuit 26. The threshold values Th1 and Th2 (Th1 <Th2) are also supplied to the comparison circuit 26. Comparison circuit 26
Generates a 2-bit flag (classification information) according to the magnitude relationship between Ef and Th1 and Th2. That is,
Blocks with Ef ≦ Th1 are divided into class NONE,
The block of Th1 <Ef <Th2 is divided into the class PRED, and the block of Ef ≧ Th2 is divided into the class INTRA.

This flag is taken out to the output terminal 27. ON / OFF of the gate circuit 13 of FIG. 1 is controlled by the flag. In the case of class NONE, the gate circuit 13 may be on or off. Class NO
The NE block is a block having a small integrated output Ef, that is, a block having a small frame difference. Typically, in the case of a still image, Ef = 0 except noise. Recording is omitted in the blocks of the frame P belonging to the class NONE. On the reproducing side, the decoded data of the block of the other frame I of the pair POP is used again as the block of the frame P.

In the block of class PRED, the integrated output Ef of the absolute value of the frame difference exists to some extent. In this block, the gate circuit 13 is turned on.
Therefore, the frame difference generated by the subtraction circuit 4 in FIG.
CT, variable length coding. A block of class PRED is a block that receives intra 2 frame processing.
For blocks of class INTRA, gate circuit 1
3 is turned off, and the data itself of the frame P is generated from the subtraction circuit 4. Therefore, frame P of class INTRA
Data is subjected to intra-frame encoding processing. The class INTRA is a class in which the correlation between frames is small and improvement of the compression rate cannot be expected even if the difference data is encoded.

The flag indicating the above classification information is also used to determine the bit allocation within the fixed length unit. This embodiment is for recording / reproducing a standard-definition component video signal.
The data amount is controlled so that the sum of the coded data amount of the macroblock and the coded data amount of the 5 macroblocks of the frame P at the same position as this is equal to or less than a predetermined target bit number. ing. The target number of bits is 5
This is the amount of data that can be inserted into each sync block. Here, the macroblock is a processing unit having a size of 6 blocks, that is, 4 blocks of the Y signal and 2 blocks of the color difference signal when each component of the component video signal is divided into blocks. Therefore, 5 macroblocks are 30 blocks.

FIG. 3 illustrates this process, 5+
The target number of bits of the data amount of 5 = 10 macroblocks (buffering unit) is represented by T. It is controlled how to assign the target number of bits T to the coded data of the 5 macroblocks of the frame I and the coded data of the 5 macroblocks of the frame P. The bit allocation modes are PRE, FIX, and SCH.
There are 3 modes. As shown in FIG. 4, in PRE, TB (bit) is assigned to the frame I and B (bit) is assigned to the frame P. However, TB is (3/4) T or more. FIX
In, the bit allocation for each of the frame I and the frame P is fixed to T × (3/4) and T / 4. In the SCH, the bit allocation for each of the frame I and the frame P is fixed to T / 2 and T / 2.

A mode PRE in which bit allocation is adaptively controlled will be described. In this mode, at least (3/4) T is assigned to the frame I as described above. Therefore, the remaining T / 4 is the number of bits allocated to the frame P. Since the amount of generated data in the frame P is smaller than that in the frame I, the standard of the number of allocated bits is set in this way. Further, the encoding of the frame P, as described above,
There are three classes (NONE, PRED, INTRA), and as a result, the amount of encoded data of 5 macroblocks is not constant. As an extreme example, if all 5 macroblocks are in the NONE class, the amount of generated data is 0.
Is. Therefore, frame P may not require T / 4 even though the bit allocation for frame P is less than that for frame I. In that case, the number of bits of margin generated is added to (3/4) T for frame I. The increase in the number of bits allocated for the frame I is advantageous for improving the image quality of the decoded image of the frame I.

The adaptive allocation control is performed by the coding control circuit 14. As shown in FIG. 2, the flag is supplied to the slice number generation circuit 28, and the number of slices corresponding to the flag indicating the classification information is generated from the circuit 28. A slice is a unit of data amount introduced for adaptive control of bit allocation, and for example, T / 4 is 30
The number of bits equally divided is selected for one slice. The slice number generation circuit 28 has 0 slices for the NONE class, 2 slices for the PRED class, and INTRA.
3 slices are generated for each class. The number of slices is an example determined based on statistical and empirical grounds.

The output signal of the slice number generating circuit 28 is supplied to the integrating circuit 29 and integrated for 5 macroblocks (= 30 blocks). The clipping circuit 30 is connected to the integrating circuit 29. The clipping circuit 30 clips the integrated number of slices by 30 (= T / 4). A data conversion circuit 31 is connected to the clip circuit 30. The data conversion circuit 31 converts the number of slices into the number of bits. Data of the number of bits B allocated to the frame P is generated from the data conversion circuit 31 to the output terminal 32. In the arithmetic circuit 33, the calculation of T-B is performed, and the data of the number of bits T-B allocated to the frame I is generated at the output terminal 34.

The bit allocation data generated in this way is stored in the memory 15 in FIG. The two-frame pair POP includes, for example, 270 buffering units. As described above, 270 pieces of bit allocation information determined for each buffering unit are stored in the memory 1
Stored in 5. The bit allocation data of the memory 15 is read at the time of the next POP encoding process, and the estimation unit 7
Is supplied to. The estimator 7 refers to the bit allocation data of each buffering unit to perform the buffering process. Bit allocation information represented by the number of slices instead of the number of bits may be stored in the memory 15.

The bit allocation information determined by the previous POP data cannot be used in the two frames and the scene change when the encoding is started. Therefore,
The three bit allocation modes shown in FIG. 4 are prepared, and the mode is selected according to the case. Prediction mode (PRE) is
This is the above-mentioned adaptive control mode, which is the normal mode. When encoding is started, the fixed (FIX) mode is selected. In this mode, for frame I (3 /
4) T (bits) are allocated, and (T / 4) is allocated to the frame P.

FIG. 5 is for explaining the bit allocation mode. F1, F2, F3, ... Represent frames, and Fi and Fi + 1 (i = 1, 3, 5, ...). ) And, a two-frame pair POP is formed. The FIX mode is adopted in the frames F1 and F2 in which encoding is started. Scene changes occur in two cases shown in FIGS. 5A and 5B, respectively. In the example of FIG. 5A, PO
A scene change occurs between P frames, and in the example of FIG. 5B, a scene change occurs between the POP and the next POP. In the case of FIG. 5A, the bit allocation mode for the POP in which the scene change has occurred is SCH. This is a mode in which the bit allocation is T / 2 each. In the case of FIG. 5B, this is equivalent to the case of the start of encoding, and therefore the POP mode after the scene change is set to FIX.

The scene change detection circuit 16 detects each of these two scene changes and supplies the detection result to the estimator 7. The estimator 7 has a function of generating bit allocation data of the mode FIX or SCH in response to the detection result and using this bit allocation data instead of the data of adaptive allocation from the memory 15.

By the above encoding, D within one frame
The data rate can be halved to 12.5 Mbps as compared with the case of CT and variable length coding. In the above example, the difference is calculated between blocks at the same location in frames I and P, but it is also possible to calculate the difference after motion compensation. This allows a higher compression rate.

The present invention can be applied to standard resolution color video signals (referred to as SD signals) and high resolution color video signals (referred to as HD signals). Some examples of digital video signals are described below.

First, the format of the SD signal will be described. FIG. 6 shows the format of the SD signal. SD
The signals are defined in two systems (525/60 system and 625 /
50 systems) are known. 525/60 (SD-H60) system (for luminance data) Sampling frequency: 13.5 MHz Number of samples / line: 858 Number of effective samples / line: 720 Number of effective lines / frame: 480

625/50 (SD-H50) system (for luminance data) Sampling frequency: 13.5 MHz Number of samples / line: 864 Number of effective samples / line: 720 Number of effective lines / frame: 576

Macroblocks are defined for processing the component type luminance data Y and color difference data C _R , C _B. In the SD-H60 system, as shown in FIG. 7A, a total of 6 blocks of 4 Y blocks and 2 color difference signal blocks at the same position in one frame constitute one macroblock. Regarding the Y signal, as shown in FIG. 7B, the total number of blocks in one frame is (90 × 60).
= 5400), and as shown in FIG. 7C, the number of blocks of one color difference signal is (22.5 × 60 = 1350), and there are 8100 blocks / frame in total. Therefore, 8100 ÷ 6 = 1350 is the number of macroblocks in one frame. The number of macro blocks is equal to the number of color difference signal blocks.

In the SD-H50 system, as shown in FIG. 7D, a total of 6 blocks of 4 Y blocks and 2 color difference signal blocks at the same position in one frame constitute one macroblock. As for the Y signal, as shown in FIG. 7E, the total number of blocks in one frame is (90 × 72 = 6).
480), and as shown in FIG. 7F, the number of blocks of one color difference signal is (45 × 36 = 1620), and there are 9720 blocks / frame in total. Therefore, 9
720/6 = 1620 is the number of macroblocks in one frame.

In intra two-frame encoding, buffering is performed so that the data amount of two frames (frames I and P) is equal to or less than a predetermined number of bits. 525/6
In the case of the 0 system, 1350 × 2 = 2700 macroblocks are encoded and recorded on 10 tracks on the tape. Here, the number of sync blocks in one track is 1.
Since it is 35, 135 × 10 = 1350 sync blocks are filled with coded data for two frames.

Specifically, since the buffering unit (that is, the unit of fixed length) is packed in 5 sync blocks, (2700/1350) × 5 = 10 macroblocks = 6
0 block (525/60 system) becomes a buffering unit.

Similarly, the 625/50 system records data for 2 frames on 12 tracks, so that (3240/1620) × 5 = 10 macroblocks = 6.
0 block is the buffering unit.

In the intra 2 frame encoding described above, I
When controlling the data amount of the encoded output of each frame of P and P, control is performed so that 5 macroblocks (30 blocks) of each frame have a predetermined data amount (bit number), and the target of 10 macroblocks in total. The number of bits is T. In the above-described adaptive control of bit allocation, the allocated bit numbers T-B and B are determined for each 270 buffering units.

In the case of encoding one intra frame,
Number of tracks in which data for one frame is equal (10 tracks (SD-H60), 12 tracks (SD-H50))
Recorded in. Therefore, the buffering unit is 5 macroblocks. Since the amount of encoded data can be reduced by half in the above-described intra 2 frame encoding, data for 2 frames can be recorded in the above-mentioned number of tracks.

Next, an HD signal format to which the present invention is applied will be described. As shown in FIG.
Known signals are the 1125/60 system (also called a high-definition system) or the 1250/50 system (also called a HD-MAC system). The sampling frequency must be an integral multiple of the horizontal line frequency in order for the sampling positions to be arranged in a two-dimensional grid. As a trade-off between the signal bandwidth and the amount of information after sampling, 44.55 MHz (1125/60 system) and 45.0 MHz (1250/50 system) are selected. This is the case for the Y signal, but for the color signal, half the sampling frequency (22.
275MHz / 22.5MHz).

The color signal is subjected to conversion to a line-sequential signal and 1/2 thinning processing by the preprocessing circuit. After such preprocessing, the portion excluding the blanking interval and the like is compression-coded as an effective area. In the case of the 1125/60 system, the macroblock of FIG. 9A is configured to define the effective area of the luminance signal as shown in FIG. 9B and the effective area of the color difference signal as shown in FIG. 9C. In the case of the 1250/50 system, the macroblock of FIG. 10A is configured, the effective area of the luminance signal as shown in FIG. 10B is defined, and the effective area of the color difference signal as shown in FIG. 10C is defined. The effective areas of the color difference signals in FIGS. 9C and 10C are equal to the number of macroblocks in one frame, respectively.

That is, the number of macroblocks in one frame is 72 × 65 = 4680 (1125/60 system) 75 × 72 = 5400 (1250/50 system).

In intra 2 frame encoding, buffering is performed so that the amount of data of 2 frames is equal to or less than a predetermined number of bits. That is, in the case of the 1125/60 system, 4680 × 2 = 9360 macroblocks are encoded and recorded on 40 tracks on the tape. Here, since the number of sync blocks in one track is 135 (this is equal to the SD-H signal), 135 × 40 =
Encoded data is packed in the 5400 sync block.

Specifically, similar to the processing of the SD-H signal, a buffering unit (that is, a fixed length unit).
Since it is packed in 5 sync blocks, (9360/5400) × 5 × 6 = 52 blocks = 8 macroblocks + 4 blocks (1125/60 system) In the 1250/50 system, data for 2 frames is 48 tracks (135 × 48). = 6480 sync block), similarly, (10800/6480) × 5 × 6 = 50 blocks = 8
The macroblock + 2 blocks are the buffering unit. Further, in a digital VTR for HD, two tracks are simultaneously formed on a magnetic tape by two rotary heads arranged close to each other.

Further, as a format of the digital HD signal, as shown in FIG. 11, a 1250/50 system and a sampling frequency of 54 MHz (13.5) are used.
There are those selected in 4). The number of effective samples and the number of effective lines in this format are as shown in FIG. 11, and one frame is 90 × 90 × as shown in FIG.
72 = 6480 macroblocks are included. This FIG.
The present invention can be applied to the digital VTR for recording / reproducing the HD signal shown in FIG.

Similarly to the above, buffering units (that is, fixed length units) are packed into 5 sync blocks, and data for 2 frames is 48 tracks (135 × 4).
8 = 6480 sync blocks), so (12960/6480) × 5 × 6 = 60 blocks = 1
0 macroblock is the buffering unit.

In the framing circuit 9, one buffering unit is set as recording data contained in five sync blocks, and this recording data is recorded on the magnetic tape. With respect to the SD-H system, the formats of 5 sync blocks including one buffering unit are shown in FIG. 13 arranged in order from the top. Also, for the 1250/50 system, one buffering unit is included 5
Figure 1 shows the sync block formats arranged in order from the top.
4 shows. In the sync block configurations shown in FIGS. 13 and 14, the length of one sync block and the length of the data section are selected to be equal.

In the case of the SD-H signal, 10 macroblocks are included on average in 5 sync blocks. Since the coded output from the first frame (frame I) is 5 macroblocks, as shown in FIG. 13, a section in which the coded output of one macroblock of frame I is arranged is set in each sync block. To be done. That is, four sync signal sections for the AC component and two AC signal sections for the color difference signals are provided in each sync block. The sync block length is 90 bytes, and the length of the data section including the DC component section, the motion flag M and the activity code AT section, and the AC component section is (14 × 4 + 9 × 2 = 7).
4 bytes).

Further, the buffering unit of the 1250/50 system is also 10 macroblocks as described above. Therefore, the format of FIG. 13 can be directly applied to this system.

Explaining the data format,
The block sync signal SYNC (2
Byte), followed by the ID signal. This ID signal is a 2-byte ID signal (ID0, ID1)
And a parity IDP (1 byte) for the ID signal. After this, a 1 for identifying the quantization step
The quantization number QNO of bytes and the auxiliary code AUX are located. Of the remaining bytes, 74 bytes are a data (DC component, motion flag M, activity code AT, variable length code or outer coded parity) section, and the last 8 bytes are the parity of the inner code of the product code. Is.

The 74-byte section is divided into, for example, four sections having a length of 14 bytes and two sections having a length of 9 bytes. D of Y or C at the fixed position of the divided section
A DC component (9 bits) generated in the CT block, a motion flag M and an activity code AT are arranged. In the 14-byte section, the AC component coefficient data generated in the block of the luminance signal is packed in order from the low frequency component, that is, in the order of zigzag scanning. In one of the two 7-byte sections, the coefficient data of the AC component generated in one color difference signal block is packed in order from the low frequency band, and in the other section, the coefficient data of the AC component of the other color difference signal. Are packed in order from the low range.

Further, when all the block data cannot fit in the fixed section of each sync block, the packing at the break of the word is stopped and the data that does not fit are stored in the overflow memory. This operation is Y and C
For each fixed section in which the character is written, perform the block in the buffering unit. Here, it is the encoded output of frame I that is first packed in the above-mentioned data section. And then, the overflowed frame I
Data is sequentially packed in the remaining area of the fixed section.
Further, subsequently, the data of the frame P is sequentially packed in the remaining area.

A sync block format applied to the 1125/60 system shown in FIG. 14 will be described. This is basically the same as FIG. 13, but the buffering unit is 52 blocks (8 macroblocks +
4 blocks), 26 blocks (4
A fixed area of (macro block + 2 blocks) is set. That is, with respect to 4 sync blocks out of 5 sync blocks, each sync block is divided into fixed areas for 1 macroblock (= 6 blocks). The remaining one
The sync block has a fixed area for two blocks, and the rest is set as the ACH section.

The method of packing the encoded output for the format of FIG. 14 is the same as described above. First, for the 26 blocks of frame I, the data of each block is packed into a fixed section in order from the low frequency coefficient. Data that does not fit into the fixed section is temporarily stored in the overflow memory. This operation is sequentially performed for each block. And
Next, the blank area and the ACH area in the fixed section are filled with the data stored in the overflow memory, and subsequently, the data of 26 blocks of the frame P are filled.

In this way, the data generated by the intra 2 frame encoding can be efficiently packed in 2 steps into the data section of the sync block with a simple circuit configuration.

Further, although not shown, the present invention is 12
The 50/50 system can be framed similarly to the 1125/60 system. In this system, since the buffering unit is 50 blocks,
Corresponding to 25 blocks (4 macro blocks + 1 block) of frame I, each sync block of 4 sync blocks among 5 sync blocks is 1 macro block (= 6).
The fixed area is divided into fixed areas for one block, and the remaining one sync block has a format having a fixed area for one block and an ACH section.

[0065]

According to the present invention, when the data generated by the encoding of intra 2 frames is fixed length and the buffering unit is packed in the data section of a plurality of sync blocks, the fixed section in the data section is The coded data of the frame I is packed first, then the overflow data of the frame I is packed in the margin area, and then the coded data of the frame P is packed. Therefore, the coded output of the frame I having a high degree of importance can be packed by the fixed section in which the influence of error propagation is small. Therefore, the quality of the image restored from the reproduced data can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an encoding circuit of a digital VTR.

FIG. 2 is a block diagram of an example of an encoding control circuit.

FIG. 3 is a schematic diagram for explaining adaptive control of bit allocation for encoded outputs of two frames.

FIG. 4 is a schematic diagram used to describe a bit allocation mode.

FIG. 5 is a schematic diagram used to explain selection of a bit allocation mode.

FIG. 6 is a schematic diagram used for explaining a digital video signal (SDH) signal to which the present invention can be applied.

FIG. 7 is a schematic diagram used to describe a macroblock.

FIG. 8 is a schematic diagram used for explaining a digital HD signal to which the present invention can be applied.

FIG. 9 is a schematic diagram used to describe a macroblock.

FIG. 10 is a schematic diagram used to describe a macroblock.

FIG. 11 is a schematic diagram used for explaining another example of a digital HD signal to which the present invention can be applied.

FIG. 12 is a schematic diagram used to describe a macroblock.

FIG. 13 is a schematic diagram showing an example of a data configuration of 5 sync blocks in a buffering unit in the SDH system and the 1250/50 system.

FIG. 14 is a schematic diagram showing an example of a data configuration of 5 sync blocks in a buffering unit in the 1125/60 system.

[Explanation of symbols]

 4 Subtraction circuit 5 DCT circuit 6 Adaptive quantization circuit 7 Estimator 9 Framer circuit 13 Gate circuit 14 Coding control circuit 16 Scene change detection circuit

Claims (4)

[Claims] 1. An encoding and framing device which compresses and encodes the data amount of an input digital video signal and frames the encoded output into a predetermined data format for transmission, and a code of a predetermined size. An orthogonal transform unit for transform coding for each encoded block, and the orthogonal transform unit are combined so as to control the data amount of the encoded output in the fixed length unit so that the data amount falls within the data area of a plurality of sync blocks. An adaptive quantization means for performing, a variable length coding means coupled to the adaptive quantization means, a means for locally decoding the output of the adaptive quantization means, and a means for storing the locally decoded data. The frame difference between the first frame decoded data from the frame memory and the second frame following the first frame. Each coding block is detected, and the coding block is classified into a first class in which the frame difference is smaller than the threshold value and a second class in which the frame difference is larger than the threshold value. For the first class coded block, the frame difference is given to the orthogonal transform means, and for the second class coded block, the data of the second frame is given to the orthogonal transform means. Coding control means for controlling, and framing means for converting the output of the variable length coding means into transmission data having the configuration of the plurality of sync blocks, the code of the AC component of the first frame. Start the low-frequency component from the low-frequency component, stuff it into the predefined data section of the plurality of sync blocks, and then encode the AC component of the second frame. And a framing means adapted to pack the encoded output of the AC component of the overflowed first frame into the blank data section of the plurality of sync blocks. And framing equipment. 2. A digital video signal coding and framing device according to claim 1, wherein the framing means packs the coded output of the first frame into a fixed data section. A coding and framing device for a digital video signal, comprising a number of data sections equal to the number of coding blocks of the first frame in a unit. 3. A coding and framing device for a digital video signal according to claim 1 or 2, wherein the input digital video signal is a standard resolution digital video signal. 4. The encoding and framing device for digital video signals according to claim 1 or 2, wherein the input digital video signal is a high resolution signal.