JPH05308610A - Band compression signal processor - Google Patents

Abstract

PURPOSE:To obtain a satisfactory reproducing image when fast reproduction is performed by forming a trick block by coupling plural blocks to which refresh coding processing is applied, and arranging them among non-trick blocks to which no refresh coding processing is applied. CONSTITUTION:Signals U, V and a luminance signal Y supplied to input terminals 32, 33, and 36 are coupled by a multiplexer 37, and are inputted to a variable length encoder circuit 16. A band compression encoded video code obtained from the variable length encoder circuit 16 is supplied to a code replacement circuit 39, and also, a refresh block control circuit 40 generates the code position signal of a refresh block, and supplies it to the code replacement circuit 39. The satisfactory reproducing image can be obtained by performing re-arrangement between the refresh block and a non-refresh block by the code replacement circuit 39 based on the video code and the code position signal, supplying them to an index insertion circuit 41. and accurately obtaining a signal to which inframe coding processing is applied when the fast reproduction is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intra-frame coding processing and inter-frame coding processing.
The present invention relates to a device which can easily obtain a good reproduced image when the output signal is recorded on, for example, a tape by a helical scan method and transmitted to a recording / reproducing device for reproducing the recorded signal.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method or a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting.
Vol.36 NO.4 DEC 1990 Woo Paik: “Digit
It is a band compression technology as shown in "al compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 35, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantization circuit 15
In the above, the reason why the quantization table is provided is that the amount of information generated and the amount of information transmitted are kept within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded with the number (run length) following the zero coefficient and the non-zero coefficient as one set. The encoder is a variable length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. The variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer at the next stage (not shown). [Control signals, voice data, sync data (SYN
C), multiplex NMP etc. described later] is supplied to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. ..

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intra-frame coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. The quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is supplied to the inverse quantization circuit 19
The signal is restored to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the inter-frame coding process is executed, both the switches 24 and 25 are turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 36 shows a line signal in a state in which the video signal of the high-definition television signal is subjected to the intraframe processing and the interframe processing as described above and sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. FIG. 36 (a) shows the signals of the first line, and FIG. 36 (b) shows the signals of the second and subsequent lines. If this video signal has undergone intra-frame processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information. It means that compression is realized.

Next, the definition of the set of pixels processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: luminance signal in horizontal direction 4
An area consisting of blocks and two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks.

Macroblock: 11 superblocks in the horizontal direction. Also, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. The end of block signal is added at the end. Then, the motion vector of the motion correction performed in units of super blocks is
It is added and transmitted in macroblock units.

With respect to the transmission signal shown in FIG. 36,
Further explanations will be given on particularly relevant matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

Further, as a measure against the user changing the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are referred to as macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS.
As shown in FIGS. 38 (a) to 38 (c), refreshing is performed in units of four macroblocks in each vertical column of superblocks, and all superblocks are refreshed every 11 frame periods. That is, as shown in FIG. 38 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all areas.
Therefore, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intraframe processing is performed at an 11-frame cycle, so that the reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

By the way, the band compression system described above is
It is used as an encoder for band compression of television signals, and the decoder is used on the receiving side. Now, consider recording the above transmission signal in a VTR.
A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, when the transmission signal obtained by the band compression system is used as it is for recording / reproducing on the VTR, the variable length code is used as it is as the code for the intra-frame processing and the inter-frame processing. The position where the code processed in the frame is recorded is not fixed, and a block that is not refreshed may occur during high speed reproduction.

Specifically, FIG. 39 shows a track pattern when the variable-length coded signal as described above is helically recorded on the magnetic tape 26. In track patterns T ₁ through T _11, a portion indicated by a thick line indicates the switching position of the frame F ₁ to F _11. The switching positions of the frames F _{1 to} F ₁₁ are not aligned because the record data is created by the variable length code. In the magnetic tape 26, when normally reproduced by a VTR, all track patterns T _{1 to} T ₁₁ are sequentially scanned by the magnetic head. Therefore, by passing the reproduction output to the decoder, no problem occurs. It is possible to reproduce various video signals. That is, during normal reproduction, it is possible to reproduce all of the intra-frame processed code and the inter-frame processed code recorded on the magnetic tape 26, so that an image can be constructed using all the codes.

However, in the VTR, there are cases where only a limited number of tracks are reproduced, as in the double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if the tracks subjected to the inter-frame coding process are reproduced, only the image by the differential signal is obtained.

FIG. 40 shows trace loci X _{1 to} X ₁₁ of the magnetic head in the case of performing the double speed reproduction. Figure 4
In _No. 0, since the signals subjected to the intra-frame coding processing are dispersed and recorded in the frames F _{1 to} F ₂₄ , the position of the intra-frame processing portion reproduced in the screen is indefinite. The signals processed in the frame that can be reproduced at the double speed reproduction are shown in FIGS. 41 (a) to (h) and FIGS. 42 (a) to (c). And these 1
When one frame is accumulated, as shown in FIG. 42 (d),
There is no code for which intra-frame processing is performed periodically, that is, there is a portion where a refreshed super block does not exist, and a portion that cannot compose a reproduced image occurs.

[0021]

As described above, the helical scan type recording / reproducing apparatus having the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide an extremely good band-compressed signal processing device capable of easily obtaining a good reproduced image at high speed reproduction.

[0023]

A band-compressed signal processing device according to the present invention forms a (a is a positive integer) image area in a video signal of one screen, and a frame is generated for this video signal. Intra-frame encoding processing is performed using the intra-frame encoding signal that is subjected to intra-frame encoding processing using the information in the frame and the inter-frame processing signal that is subjected to inter-frame encoding processing using the difference information between frames. After that, an inter-frame coding process is performed, and a band compression unit that adaptively repeats this signal processing method according to the motion evaluation of the input video signal, and one frame with f frames (f is an integer of f ≧ 2) as a cycle. Refresh encoding processing means for periodically performing intra-frame encoding processing on the signals of b image areas of each a area, and combining a plurality of blocks subjected to the refresh encoding processing. ,bird Forming a click block, in which to arrange between the non-trick block not subjected to refresh coding process.

[0024]

According to the above construction, since the signal subjected to the intra-frame coding processing can be accurately obtained at the time of high speed reproduction, a good reproduced image can be obtained.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, the intraframe coding processing is performed on 2640 areas per screen in 11 frames, so the number of areas in one screen is a = 2640, and the intraframe coding processing period f is 11 frames. Further, here, an example in which the a = 2640 areas do not overlap each other is used, but they may overlap. further,
In order to describe the case where one track is divided into ten and the average video code for one frame is recorded in one track, the number of divisions of one track d = 10, and the number of tracks for recording the average video code for one frame c = 1. Therefore, the number of recording medium areas is d × c × f = 10 × 1 × 11 = 110. The correspondence between the screen area and the recording medium area will be described in the case of equal distribution. It should be noted that in the present invention, it is not always necessary to equally distribute. Therefore, the number of screen areas in one recording medium area e = a / d × c × f = 2640
/ 10 × 1 × 11 = 24, and d = e = 24
The case of associating with × c × f = 110 regions will be described.

In FIG. 1, the same parts as those in FIG. 35 are designated by the same reference numerals, and different parts from the conventional system will be mainly described. Further, FIG. 2 shows the operation timing of this system. Here, this embodiment will be described using a block diagram on the encoder side for simplification of description, but can also be realized on the decoder side for receiving the transmission data shown in FIG. Referring to FIG. The sync signal SYNC of the input video signal is supplied to the input terminal 27. This synchronization signal SYNC is S
It is input to the YNC signal detection circuit 28 and detected. SY
The NC signal detection circuit 28 generates a SYNC pulse synchronized with the synchronization signal SYNC to generate the track formation signal generation circuit 2
9 is being supplied. In the case of being realized by the decoder, the synchronization signal SYN in the transmission data shown in FIG.
C may be detected and input to the SYNC signal detection circuit 28.

FIG. 2A shows an input video signal, Y is a luminance signal, U and V are chrominance signals, and the numbers entered in the frame indicate the frame numbers. Figure 2
(B) is an SY signal obtained from the SYNC signal detection circuit 28.
The NC pulse is generated and is generated in synchronization with the switching point of the frame of the input video signal shown in FIG. FIG. 2C shows the track formation signal obtained from the track formation signal generation circuit 29. A and B added to the track forming signal specify a period in which the A head and the B head alternately form tracks. A
As shown in FIG. 1, the head and the B head are attached at a position opposed to the rotary drum 30 by 180 °. Here, the case where heads are attached one by one facing each other will be described. However, when the code amount that can be recorded in one track is small, p heads (p is a positive integer) are arranged facing each other. Good. In this embodiment, SY shown in FIG.
The generation timing of the NC pulse and the switching timing of the track formation signal shown in FIG. 2C are synchronized. FIG. 2D shows tracks formed by the A head and the B head, and the numbers written in the frame indicate the track numbers.

The track formation signal output from the track formation signal generation circuit 29 is supplied to the track formation control circuit 31. This track formation control circuit 31
Controls the rotation phase of the rotary drum 30, and
The timing of supplying a recording signal to the head and the B head is controlled. In this embodiment, since the average code generation amount of one frame corresponds to one track, the rotary drum 3
A case where the number of revolutions of 0 is 900 rpm will be described. However, the average generated code of one frame may be recorded in c (c is a positive integer) tracks by scanning the magnetic head c times, and the rotational speed of the rotary drum 30 may be set to a different rotational speed such as 1800 rpm.

Next, the code exchange method used in this embodiment in order to enable the high speed reproduction of the VTR will be described. First, a combination of the color signals U and V supplied to the input terminals 32 and 33 through the decimators 34 and 35 and the luminance signal Y supplied to the input terminal 36 by the multiplexer 37 is obtained. It is supplied to the subtraction circuit 12 and the motion evaluation circuit 13 as an input video signal, and the variable-length coding circuit 16 outputs the band compression-coded video code.

Here, in the conventional band compression system shown in FIG. 35, the video signal is variable length coded and transmitted, and as shown in FIG. 2I, the switching point of the frame of the video code is the frame. Depends on Figure 2
The NMP signal shown in (h) indicates the switching point of the frame of this video signal. Conventionally, there are 2640 super blocks in one frame, and these 2640 super blocks are within one frame period shown by the NMP signal in FIG. 2 (h).

Further, conventionally, there are four macro blocks in the horizontal direction on one screen, and these macro blocks are composed of 11 super blocks. Then, one superblock in the microblock per frame is forced to use the intraframe processing. The sequence in which the in-frame processing is forcibly used is included in the system control signal shown in FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block.

That is, as the definition of words, when the intra-frame processing is forcibly performed by one super-block in one frame period of a refresh block: macro block, the super-block subjected to the intra-frame processing is called a refresh block. A macro block consists of 11 super blocks, so 1
In-frame processing is forcibly performed in one frame cycle.

Non-refresh block: A super block other than the above-mentioned refresh block. Within this super block, there are a block subjected to intra-frame processing and a block subjected to inter-frame processing depending on the contents of the image. For example, when a scene change or the like occurs in the input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, 240 refresh blocks (= 2640/11) exist in one frame period. Therefore, conventionally, 240 refresh blocks are present in one frame period shown in FIG. 2H as shown in FIG. Then, the conventional signal is used as it is for VT.
When recording with R, the position of the refresh block is not fixed and high-speed reproduction cannot be performed as described above.

FIGS. 3A and 3B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Then, thereafter, the frame number, during the refresh block number and the non-refresh block number, frame number F _n (n is an integer) the refresh block number G _n frames, the non-refresh block number and H _n.

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is different.

In this embodiment, one track is divided into ten and recorded. When one track is divided into 10, high-speed reproduction can be performed up to 10 times speed. During high-speed reproduction of 11 times or more, all refresh blocks cannot be reproduced, so that an area in which an image cannot be formed occurs as in the case shown in FIG. 42 (d). If, as a VTR specification, high-speed reproduction at 20 times speed is desired, one track may be divided into 20. Further, when it is desired to realize fast high speed reproduction, refresh blocks may be arranged on the track at equal intervals.

FIG. 2E shows a timing pulse for dividing one track into ten, and the one track period shown in FIGS. 2B and 2C is divided into ten substantially equal parts.
Then, this one divided period is referred to as a sector.

In other words, as the definition of the word, the sector: one track period is divided into d (in this case, 1
0) The divided period.

In this embodiment, as shown in FIG. 2 (f), 24 refresh blocks are placed in one sector. In this way, one track consists of 10 sectors, and 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, the number of refresh blocks e in one sector is b, which is the number of super blocks on which periodic intraframe processing is performed.
If b intra-frame processed signals are recorded on c tracks, e = b / c × d (in this case, 240/1 × 10
= 24).

By performing the code exchange as described above, the refresh block for one frame is conventionally arranged in one frame period indicated by the NMP signal, but the refresh block for one frame is replaced in one track period. Can be arranged to be present.

FIG. 4 shows a track pattern. That is, the tracks T _{1 to} T ₁₁ on the magnetic tape 26.
The G _{1 to} G ₁₁ entered in the frame of No. correspond to the refresh block number G _n described above. The relationship between this refresh block and the track T _n is the number G in the track T _n .
The relationship is that _n refresh blocks are recorded. Further, H _{1 to} H ₁₁ entered in the frames of the tracks T _{1 to} T ₁₁ are the non-refresh block numbers H described above.
Corresponds to _n . The switching point of the non-refresh block is the thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

Track 38 in FIG. 4 shows the relationship between sectors and tracks. The track 38 is divided into 10 and d =
It is divided into 10 sectors. In this one sector,
e = 24 refresh blocks are arranged. The non-refresh block is inserted between the refresh blocks.

[0044] Here, if the track T _5, T ₆ will be described in detail as an example, the track T ₅ to record refresh blocks G ₅ of the frame F _5. Also, track T
The ₆ records the refresh block G ₆ of the frame F _6. A non-refresh block is recorded in the free space where this refresh block is arranged. The track T ₅ records non refresh block H _5, H _6, the track T ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the above-described recording form, the band compression encoded video code obtained from the variable length encoding circuit 16 in FIG. 1 is supplied to the code exchange circuit 39 again. Further, the refresh block control circuit 40 generates the code position signal of the refresh block described above, and this code position signal is supplied to the code exchange circuit 39. The code exchange circuit 39 rearranges refresh blocks and non-refresh blocks based on the input video code and code position signal.

That is, a process of inserting 24 refresh blocks into each of 10 sectors provided in one track is performed. In order to perform this processing, the code is temporarily stored in a memory (not shown), and when the code is read from the memory, 24 refresh blocks are read in one sector.

The output of the code exchange circuit 39 is
It is supplied to the index insertion circuit 41. The index insertion circuit 41 inserts an index signal into the control data section of each sector so that it can be detected during reproduction that the non-refresh block is partially separated and recorded. The index signal is prepared by the index generation circuit 42 to which the code position signal from the refresh block control circuit 40 is supplied. The output of the index insertion circuit 41 is
The data is supplied to the A head and the B head via the multiplexer 43 and recorded on the magnetic tape 26.

When the refresh block and the non-refresh block are exchanged in the decoder, the PCM / DPC of the head data existing at the head of the macro block in the video code shown in FIG.
A refresh sequence code included in the M determination code and the system control signal may be detected and used as an output signal of the refresh block control circuit 40.

FIGS. 5A and 5B show the trace traces X _{1 to} X ₁₁ of the head during double speed reproduction. It should be noted that the refresh block G _n and the non-refresh block H are arranged in the frame of each track T _{1 to} T ₂₂ as in FIG.
_n is shown. Then, in the head trace at the time of double speed reproduction shown in FIG. 5, reproducible refresh blocks are shown in FIGS. 6 (a) to 6 (h) and FIGS. 7 (a) to 7 (c). 6 (a) to (h) and FIG. 7 (a) to
Frames 1 to 11 shown in (c) are 2 shown in FIG.
Speed indicates playable refresh block at a head trace loci X ₁ to X ₁₁ at the time of reproduction.

For example, in the frame 1, by performing the head trace X ₁ , it is possible to display the refresh block G ₁ in the upper half of the screen and the refresh block G ₂ in the lower half of the screen. Similarly, in the frames 2 to 11, the refresh block G ₃
Up to G ₂₂ can be reproduced. Therefore, when reproducible refresh blocks are stored in frames 1 to 11, the codes of all screen areas can be reproduced as shown in FIG. 7 (d).

The inter-frame processed code and the intra-frame processed code according to the contents of the image are periodically put between the intra-frame coded codes. Then, these codes have no correspondence between the image area and the recording medium area.

In the present invention, the correspondence between a image areas and d × c × f recording medium areas is 1: 1.
May be associated with, or 1: 2, 2: 1
Any correspondence may be made, such as a correspondence in which a blank is put in the area of the recording medium. The recording medium is not limited to the magnetic tape 26 but can be a video disk, and in this case, one round of the disk corresponds to one track of the tape.

High-speed reproduction is possible by inserting a refresh block in a predetermined area on the VTR track, but it is necessary to prevent the code amount from exceeding the code amount recordable in the predetermined region.

The code amount of a predetermined refresh block is
When the amount of code that can be recorded in a predetermined area of the recording medium is exceeded, refresh is not performed at the position on the screen corresponding to the exceeded code.

Even if this is not avoided, since the refresh is performed from a certain position on the image, it is highly possible that the content of the image can be determined, but in order to perform the refresh more reliably. It is necessary to control the amount of code generated in the refresh block.

In this example, by dividing the code of the refresh block into a plurality of parts, the low frequency component or the MSB of the refresh block is divided into a predetermined area on the track of the VTR.
Enter the sign.

Therefore, the code amount of the refresh block will be described in detail.

First, the two-dimensional DCT circuit will be described.

First, the image is divided into small blocks (N × N) each consisting of N pixels in both the horizontal and vertical directions, and two-dimensional DCT is applied to each block. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by equation 1, and its inverse transform equation is given by equation 2.

[0061]

[Equation 1] Here, F (0,0) represents the coefficient of the DC component, and F (0,0)
(U, v) includes a high frequency horizontal frequency component as u increases, and includes a high frequency vertical frequency component as v increases.

First, the nature of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing the average luminance value in the image block, and its average power is usually considerably higher than other components.

Further, when the DC component is roughly quantized, noise (block distortion) peculiar to the orthogonal transformation, which is visually perceived as a large image quality deterioration, occurs. Therefore, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is uniformly quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
Describe the nature of. The average value of F (u, v) is
It becomes “0” excluding that of the DC component F (0,0).

In order to perform efficient encoding, when a certain number of bits are assigned to a small block of an image for encoding, a large number of encoding bits are allocated to the transform coefficient of the low frequency component, and conversely. By assigning a small number of coding bits to the transform coefficient of the high frequency component and performing the coding, it is possible to reduce the image quality deterioration and perform the coding with a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions, and the two-dimensional D
When CT is applied, the converted coefficients for each frequency component become 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 8, the upper left is the DC coefficient (direct current component). The other 63 are AC coefficients (AC components), and the spatial frequency increases toward the lower right. Since the AC component has a two-dimensional spread, it is converted into one dimension by zigzag scanning shown in the order of 0 to 63 at the time of encoding and transmission.

Here, the 64 DCT coefficients are converted to DCT _i
It is represented by [i = 0 to 63].

In the case of an image signal, the number of quantization bits for quantizing each pixel is often 8 bits.

The DCT coefficient of the output obtained by DCT converting the 8-bit pixel may be represented by 12 bits.

Next, the quantization will be described.

The 64 DCT coefficients described above are linearly quantized with a different step size for each coefficient position, using a quantization table that defines a quantization step size for each coefficient.

There are two kinds of quantization step setting methods, but basically the same method.

The first method is a method of transmitting a code indicating the quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 9 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes that represent a quantization table, and by transmitting this code, the decoder can perform inverse quantization.

Further, 64 numbers arranged in a square represent the number of quantization bits, and have a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. For example, 7 at the upper left of the quantization table for q = 0 indicates that the DC component is quantized with 7 bits.

Hereinafter, each coefficient is similarly quantized with the number of bits shown in the quantization table.

In the second method, first, 64 DCT coefficients are weighted by a weighting matrix.

After this, the quantization width data QS (Quantize-S
cale) is used to uniformly divide each coefficient and then quantize it. When transmitting, a code corresponding to the quantization width data is sent. Also, the weighting matrix has a predetermined default value. Furthermore, it is possible to transmit a specific type of weighting matrix.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is represented by QS _j [j = 0 to 31].

Here, the quantization width data QS _{j will be} defined.

The coefficient value of the DCT is quantized with the maximum number of quantization bits, and the case of quantization is represented by j = 0 and QS ₀ = 1.

Further, the case where the coefficient value of the DCT is not transmitted is represented by j = 31, and at this time, the number of quantization bits to be described later is QL ₃₁ = 0.

Here, j is named a quantization level.

FIG. 10 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, the 64 numbers of 8 × 8 are
There is a correspondence relationship with the 64 two-dimensional coefficients shown in FIG.
The weighting value for each DCT coefficient is shown.

In the encoder, each DCT coefficient is divided by the corresponding weighting value and the quantization width data QS.

The coefficients of 64 DCTs are converted into DCT _i [i = 0
˜63], each value of the weighting matrix is WEIGHT _i [i = 0 to 6]
3] Representing each value after quantization by Q _i [i = 0 to 63],

[Equation 2] It is represented by.

The number of quantization bits at this time is

[Equation 3] It is represented by.

An example is shown below.

MPEG. First vertical direction of I luminance signal
The th AC component is represented by DCT ₁ in FIG. 8 described above.

The value corresponding to DCT ₁ of the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
It corresponds to the part marked with a circle. When the quantization width data QS ₀ = 1

[Equation 4] Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[Equation 5] Becomes

FIG. 11 shows the maximum number of quantization bits required after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix representing the number of quantization bits of 8 × 8 = 64, and each number indicates the number of quantization bits corresponding to each position of the DCT coefficient shown in FIG.

FIG. 12 and FIG. 13 quantitatively show typical 9 types of quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

In order to explain the case of using the above-mentioned second method regarding the quantization table, this table is based on the quantization width data QS.

Here, j = 31 is an example in which no data is generated at all, and corresponds to quantizing all the coefficients with 0 bits. Further, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bit allocation is based on the weighting table shown in FIG.

In FIGS. 12 and 13, the horizontal axis is DCT.
64 coefficients of the above, which correspond to the order of the zigzag scanning shown in FIG. The vertical axis is D
In each coefficient of CT, the number of bits to be transmitted is shown.

When quantizing the DCT coefficient, M
SB (Most Significant Bit) to LSB (Least Sign
ificant Bit) exists. When limiting the number of bits to be transmitted, naturally, the MSB is preferentially transmitted.

As described above, if the number of quantization bits for the DC component is reduced, block distortion or the like becomes conspicuous. Therefore, there is an example of separately treating the DC component or assigning a certain number of quantization bits. Here, it is assumed that 8 bits are assigned.

MPEG. In the case of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

The number of quantization bits and the quantization width data will be quantitatively described with reference to FIGS. 12 and 13.

The generated code amount becomes maximum when j = 0. The generated code amount decreases as j increases, and j =
It becomes 0 at 31 and no code is generated.

It is possible to control the amount of code generated by controlling the quantization width data.

There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, since the generated code amount of the refresh block is suppressed, the image quality of the refresh block itself is deteriorated. However, in the next frame, since the difference between the intra-frame processed signal of the refresh block and the video signal of the next frame is sent, the image quality is only momentarily degraded.

The second method divides the code, which has been quantized once, into two, and determines the code amount of the MSB or the low frequency component by VTR
This is a method that keeps the code amount that can be read out at high speed on a recording medium such as.

On the other hand, in a recording medium such as a VTR, when the special reproduction is realized by using the refresh block, the code amount of the refresh block is suppressed to a predetermined code amount so that the screen can be refreshed reliably at a constant cycle. ..

Regarding this, Japanese Patent Application No. 3-250671
No. etc.

There are the following two methods depending on the special reproduction method of the VTR.

The first method is a method of using DTF as a servo system of VTR.

When the maximum recording code amount that can be recorded in p tracks formed in one scan is α, and when a video signal is recorded by head scanning of c times per frame, 1 / c of the video of one frame is used. It is necessary to keep the maximum code amount of the refresh block of the area to be α or less as described above.

The second method is a case where DTF is not used.

When the DTF is not used, the high reproduction speed is i
In the case of 1, the area of 1 / i of the p tracks formed by one scan is traced.

Similarly to the above, when the maximum code amount that can be recorded on p tracks formed in one scan is α, and a video signal is recorded by scanning c times per frame,
It is necessary to keep the maximum code amount in the 1 / c × i area of the refresh block of one frame below α / i.

In this case, as the special reproduction head, a head having an extremely wide head width is not used.

FIG. 14 is a diagram showing an embodiment of the present invention.

This embodiment will be described using an example on the encoder side, but it can also be realized in a decoder. In that case, it can be realized by taking out a necessary signal from the output of the variable length decoding circuit of the decoder or from the inside.

First, the output signal of the quantization circuit 15 is passed through the zigzag scan circuit 44 and then input to the code arrangement circuit (code exchange circuit) 45.

The zigzag scanning circuit 44 rearranges the 8 × 8 DCT coefficients by the scanning method shown in FIG.

The purpose of the operation of the code arranging circuit 45 is the same as that of the code replacing circuit 39 described in FIG. 1, and by arranging the codes so that the signals of the refresh block are recorded in a predetermined area on the tape. is there.

In this embodiment, the code of the refresh block is divided so that the code amount can be recorded in a predetermined area on the tape, and the code corresponding to the low frequency component or the MSB component is recorded in the predetermined area. The case will be mainly described.

If the code amount of the refresh block is not divided and the code amount of the refresh block is suppressed to a code amount that can be recorded in a predetermined area on the tape, the refresh block is recorded in the predetermined area and the decoder circuit The effect of the present invention can be realized without using a part (the refresh block division circuit 72 and the refresh block low-frequency / high-frequency code synthesis circuit 73).

In the code arranging circuit 45, the refresh block separating circuit 46 first performs the refresh block selection 46a and the non-refresh block selection 46b.

As for the non-refresh block selection 46b, the variable length coding circuit 47 performs the variable length coding process as in the conventional example and temporarily stores it in the memory 48.

Refresh block code division circuit 49
Is a low frequency band or MSB extraction circuit 49a and a high frequency band or L
It consists of an SB extraction circuit 49b. This output signal is stored in the memory 48 through the variable length coding circuits 50 and 51, respectively. In the low range or MSB extraction circuit 49a, the VTR
The low-range or MSB code of the refresh block is extracted so that the code quantity is within the predetermined area to be reproduced during the special reproduction. This extraction method will be described in detail later.

The memory 48 replaces the code of the low frequency component or the MSB component of the refresh block so that the special reproduction can be performed, and reads it from the memory.

Next, a method of dividing the code of the refresh block will be shown.

First, the features of the conventional refresh block will be summarized.

1) The refresh block is a super block which is forcibly subjected to intraframe processing.

2) Eight luminance signal blocks and two chrominance signal blocks are included in the super block. The DC components of the eight luminance signal blocks are converted into DPCM and Huffman coded.

3) The AC component of the luminance signal and the chrominance signal are
Zigzag scan and Huffman code.

There are four methods for dividing the refresh block.
There are types.

This will be described with reference to FIGS.

The code of the non-refresh block is not divided and is processed as in the conventional example.

Similar to FIGS. 12 and 13, FIGS. 15 to 18 show the DCT coefficients arranged on the horizontal axis by zigzag scanning. The vertical axis shows the number of bits for quantization.

Further, FIG. 15 (a), FIG. 16 (a), and FIG.
7 (a) and FIG. 18 (a) show the number of quantization bits before the code is divided. Here, the case where the quantization level j = 0 before division is shown.

The first method is a method of dividing the DC component and AC component of the refresh block as shown in FIG.

That is, the code of FIG. 15A is divided into a DC component (FIG. 15B) and an AC component (FIG. 15C). Then, the code is transmitted so that the DC component (FIG. 15B) is recorded in the trick sector.

Here, the words are defined.

Trick sector: The area on the recording medium in which the track of the tape is divided into a plurality of parts is called a sector, and the sector to be reproduced is called a trick sector during special reproduction.

As a method of reducing the change from the conventional circuit, there is a method of recording only the DC component of the luminance signal in the trick sector.

The remaining codes shown in FIG. 15 (c) are recorded in places other than the positions of the codes in FIG. 15 (b).

Since the DC components of the conventional example are all quantized with the same bit, additional information indicating the number of quantized bits is not necessary.

If the code amount of the DC component of the refresh block exceeds the maximum recording code amount of the trick sector on the tape, the MSB side bit of the DC component is transmitted, together with additional information indicating the quantization level. There is also a method of transmitting.

The second method is the low-frequency component (FIG. 16B) and high-frequency component (FIG. 16C) of the refresh block.
Is a method of dividing. The non-refresh block is not divided.

In this case, the DC component of the refresh block and the AC component on the low frequency side as shown in FIG. 16 (b) are recorded in the trick sector on the track, and the refresh block is recorded in the other portions. The high frequency component and the code of the non-refresh block are recorded.

In the non-trick sector, the AC component on the high frequency side of the refresh block and the code of the non-refresh block are recorded.

The low frequency AC component shown in FIG. 16B is
Zigzag scanning is performed halfway, and after that, an EOB (End of Block) code indicating the end point of the block is forcibly inserted and transmitted as a code of one block.

In the example of FIG. 16B, the EOB code is inserted after the first to ninth coefficients of the DC component and AC component of the zigzag scan.

Next, the high frequency side AC shown in FIG.
The components will be described. Here, since the component corresponding to the low frequency component transmitted in FIG. 16B has already been transmitted,
The amplitude becomes 0. Therefore, after assigning a Huffman code indicating the number of consecutive 0s, Huffman coding is performed after that by indicating the number of consecutive 0s and the amplitude of the non-zero coefficient, as in the conventional example.

At the time of normal reproduction and slow reproduction, the low-frequency component of the refresh block recorded in the trick sector and the high-frequency component of the refresh block recorded at other locations are combined to reproduce a high-resolution reproduced image. To get

In the synthesizing method, the low-frequency component and the high-frequency component of the refresh block are Huffman-decoded respectively, and when the inverse zigzag scan is performed, the respective codes are arranged to obtain the DCT coefficient values.

At the time of high speed reproduction, a high speed reproduction image is obtained by using the low frequency component of the refresh block reproduced from the trick sector.

Since the high frequency AC component is not used, the resolution is reduced, but there is no problem in cueing the screen.

The third method is to record the MSB side of the code in the trick sector.

In the conventional method of determining the quantization table, the weighting coefficient is first applied, and then the quantization width data is applied. The quantization level j corresponding to this quantization width data is transmitted.

In this method, the code of the quantization level j = 0 shown in FIG. 17A is Huffman-decoded once,
After obtaining the transform coefficient of the DCT, a large value of the quantization level number j, that is, j for transmitting the MSB side at the time of quantization is set.

Here, as shown in FIG. 17B, the input quantization level j = 0 is used to generate a code of j = 16, and the code is recorded in the trick sector. Also, this quantization level j = 16 is recorded. This code corresponds to the one in which the number of quantization levels is increased and the content of the image is roughly quantized. Therefore, as can be seen by comparing FIGS. 17A and 17B, the code of the quantization level j = 16 represents the MSB side of the code of the quantization level j = 0.

The code shown in FIG. 17C is the code corresponding to the difference between the quantization levels j = 0 and j = 16.
This represents the LSB side of j = 0. This code is Huffman coded.

17 (b) except that the code of the quantization level j = 16 is recorded in the trick sector, FIG.
Record the code of (c).

During normal reproduction and slow reproduction, the roughly quantized code of FIG. 17 (b) reproduced from the trick sector and the code of FIG. 17 (c) are combined to produce the result of FIG. 17 (a).
By obtaining the signal of, the image with less quantization noise is obtained.

At the time of special reproduction, the rough and quantized code reproduced from the trick sector is output. Although a lot of quantization noise is generated, it is possible to find the beginning of a VTR.

The fourth method is to record the MSB side code in the low frequency band in the trick sector.

FIG. 18B shows distribution of the number of quantization bits in the quantization table. As a quantization table for high speed reproduction, a table for finely quantizing low frequencies and coarsely quantizing high frequencies is prepared.

Then, the code (FIG. 18B) using the quantization table for high speed reproduction is recorded in the trick sector.

In addition, input code FIG. 18 (a) and FIG.
The sign of the difference in (b) is shown in FIG.

The code and the code of the non-refresh block are recorded in a place other than the position where the code of FIG. 18B for special reproduction is recorded.

By using such a quantization table, the generated code amount is suppressed, but the second image is
It is possible to obtain a slightly better image quality than the above method.

The encoding method is similar to that of the third method, and a code is constructed by the quantization bit number distribution shown in FIG. 18B and recorded in the trick sector. Furthermore, FIG.
The code shown in (c) is Huffman coded, and the code shown in FIG.
Record in a place other than the one where the code was recorded.

As described above, the code of the refresh block is divided into the low frequency band or MSB component and the high frequency band or LSB component, and the low frequency band or MSB component is recorded in the trick sector. Blocking is performed, and the image quality of special reproduction images can be improved.

FIG. 19 is a diagram showing another embodiment of the present invention.

In the figure, the same components as in the conventional example are
The same number is attached. In addition, the present embodiment considers that the difference from the conventional example is minimized, and thus is a minimum change. However, it is possible to variously change the block configuration without changing the gist of the present invention. Needless to say.

The gist of the present invention is to divide the refresh block to be subjected to the intra-frame processing into the entire area of the screen in a cycle of f frames, and set the generated code amount of the low band or MSB code to
It is to keep the code amount below a predetermined value determined from the recording medium.

In order to realize this purpose, in the present invention,
The code amount of the low frequency band or MSB code of the refresh block is calculated independently, and this value is used to determine the division level of the refresh block. As described above, there are four types of code division methods, and it is possible to control the amount of codes in the low frequency band or MSB in each of them, but here, in order to simplify the explanation, the low frequency band shown in FIG. A case of dividing into a band code and a high band code will be described.

As the configuration, each refresh block code amount detection circuit 52, refresh block low frequency band code amount calculation circuit 53, and refresh block division level setting circuit 54 are used as the main configuration other than the above-mentioned embodiments.

First, in each refresh block code amount detection circuit 52, from the refresh block selection 46a,
The refresh block is input, and the number of consecutive 0 coefficients of DCT coefficients and the amplitude of the non-zero coefficient of each block inside the refresh block are detected. A ROM that stores a table as shown in FIG. 20 for the number of consecutive 0 coefficients and the amplitude of non-zero coefficients.
Then, the code amount of each refresh block is calculated.

FIG. 20, which is also used in the conventional example, shows the amplitude of the non-zero coefficient on the horizontal axis and the number of consecutive zero coefficients on the vertical axis. The numbers in the frame indicate the number of bits of the code. By adding the number of bits of this code,
The generated code amount can be calculated in block units or super block units.

By comparing the calculated code amount with the target low frequency band code amount of each refresh block, the division level is set by the refresh block division level setting circuit 54 and is input to the refresh block code division circuit 49. The target low frequency band code amount of the refresh block may be a constant value.

Further, in order to improve the control accuracy of the low frequency band code amount, the refresh block low frequency band code amount calculation circuit 53 may be used.

The refresh block low band code amount calculation circuit 53 calculates the low band code amount of the refresh block in a predetermined period.

As the servo of VTR, without using DTF,
Refreshing every 1 / c × i = 1/2 area of 1-frame video when recording a video signal with c = 1 head scan per frame and realizing i = 2 × speed as a special playback speed A case of calculating the code amount of a block will be described.

When the code amount of this refresh block is the maximum recording code amount α which can be recorded on p tracks formed in one scan, the code amount of the refresh block in the area of 1/2 of one frame is α / c. The division level is set by the refresh block division level setting circuit 54 so that xi = α / 2 or less.

FIG. 21 shows a setting method for setting the quantization level by the output signal of the refresh block low band code amount calculation circuit 53. In this example, the case where the head scan of the VTR is one scan and the average code amount of the video signal of one frame is recorded will be described. In addition, a case will be described in which the special reproduction speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector. This will be described in detail.

22 (a) and 22 (b) show a refresh block in one screen and a division method when the refresh block is further divided. F _n shown in FIG. 22A shows the screen of the nth frame. Further, G _n represents a refresh block in the nth frame. This refresh block is 240
There are individuals. In addition, G shown on the left side of the screen
_n (0) and G _n (1) indicate refresh blocks obtained by dividing 240 refresh blocks into two equal parts in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
The refresh block in the lower area of the screen is shown and includes 120 refresh blocks.
FIG. 22B shows the refresh block with the frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as in FIG. 22A. .

Next, the track pattern of the VTR will be described. FIG. 23 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₀ and T _n are the rotary drum 3
Tracks recorded using heads A and B of 0 are shown. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, c =
The case of 1 will be described. This corresponds to the case where the b = 240 refresh blocks are recorded on one track. That is, the refresh block G _{n with} the frame number F _n is recorded on the track T _n .

In this structure, when reproducing at a double speed, the reproducing head crosses two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area of 2, the reproduction signal is obtained over two tracks. Here, if one part divided into two is called a sector, one track is formed per frame, so that two sector numbers S _{0 to} S ₁ are assigned as shown in FIG.

Generally, an area obtained by dividing one track into approximately equal parts is named a sector.

In order to realize high-speed reproduction of i times speed, the head straddles i tracks, so that one track reproduces an area of 1 / i. Therefore, assuming that the maximum high-speed playback speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1
Express with.

Next, the relationship between the refresh block and the sector will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
... S ₀ , G _n (1) ... S ₁ is recorded.

Here, assuming that the number of refresh blocks in one sector is evenly arranged, the number of refresh blocks in one sector is as follows. That is, 1
If the number of refresh blocks per frame is b, the number of tracks for recording b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks in one sector is e, then e = b / c × d Become. That is, e = 240/1 × 2 = 120.

In FIG. 23, the head traces X _{0 to} X ₄ represent the head locus at double speed. That is, in the head trace X _0, sector S ₀ of the track T ₀ (refresh block G ₀ (0)), the sector S ₁ of the track T ₁ (refresh block G
₁ (1)) can be reproduced.

Here, since the recording capacity that can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape is determined,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

21A and 21B, the horizontal axis represents the refresh block number. In this embodiment, the refresh block number of the sector 0 and the refresh block number of the sector 1 are shown to record the refresh block of one frame in two sectors. Also, in this example, 1
Recording code amount of 1 sector in 20 refresh blocks α /
Do not exceed 2.

The vertical axis of FIG. 21 shows the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250 k bits. In FIG. 21A, the solid line A is the target low band code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since the solid line A is an example for control, it does not need to be a straight line, and what is necessary is to suppress the generated code amount per sector to α / 2.

The polygonal line B is a line showing an example of a change in the refresh block low band code accumulated code amount. This shows the output signal of the refresh block low band code amount calculation circuit 53. The division level is determined so that the refresh block low band target code amount A is not exceeded.

Since the output signal of each refresh block code amount detection circuit 52 is input to the refresh block division level setting circuit 54, the refresh block target code amount is compared by comparing with the refresh block low band code accumulation code amount B. It is possible to select a divided table so as not to exceed A.

Here, when the low-pass code and the high-pass code are divided as shown in FIG. 16, the zigzag scan coefficient that determines the division level is to be determined as a dividing position when sequentially scanned.

Details will be described with reference to FIG.

FIG. 21 (b) is an enlarged view of the horizontal axis of FIG. 21 (a). Refresh block number 80 to 8
A method of determining the division level to 1 will be described with reference to FIG.

First, it is assumed that the refresh block low frequency band code amount calculation circuit 60 has calculated the code amount up to the refresh block number 80, which is the code amount shown by C in FIG. 21 (b). The target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by D in FIG. 21B.

Since the refresh division level setting circuit 54 receives the signal of the coefficient obtained by DCT of the refresh block as the output signal of each refresh block code amount detection circuit 52, the generated code amount can be calculated.

Zigzag scan number ω = 6, 7, 8, 9 corresponding to the refresh block division level (FIG. 8)
If the code amount on the low frequency side becomes E to H in FIG. 21B, ω = 7 of the generated code amount of F that does not exceed the target value D is selected.

As a result, since the low band code amount of the refresh block can be controlled to the code amount in the trick sector, high image quality can be obtained even during high speed reproduction.

The configuration of each block when the code of the refresh block is divided into the reduction component and the high frequency component as shown in FIG. 19 will be described with reference to FIG.

FIG. 24A shows the codes in one super block. That is, the blocks Y ₀ to
Y ₇ and the color signal blocks U and V are shown on the vertical axis, and the horizontal axis shows the coefficient of DCT when zigzag scanning is performed. The numbers below the horizontal axis correspond to the zigzag scan numbers in FIG. The same applies to the horizontal axis in FIGS. 24 (b) to 24 (e).

When storing in the VCR, the reduced component and the high frequency component of the refresh block are divided and recorded.

A method of dividing refresh blocks in the case of DigiCipher will be described.
24B to 24E show examples when the refresh block shown in FIG. 24A is divided.

FIGS. 24B and 24C show a method of dividing the color signals U and V.

The color signals of the DigiCipher refresh block shown in FIG. 24 (b) are shown in FIG. 24 (c) for the VCR.
As shown in FIG. 3, the coefficient C _LF (U _LF , V _LF ) of the low frequency component and the coefficient C _HF (U _HF , V _HF ) of the high frequency component are divided.

As described above, the dividing method is such that the code amount in the low frequency band is kept within a predetermined code amount. Therefore, the coefficient of the DCT zigzag scan is determined so as to be within a predetermined code amount.

FIGS. 24D and 24E show the luminance signals Y ₀ to.
The division method of Y ₇ is shown. In DigiCipher, the DC component Y _DC of the luminance signal is converted into DPCM by collecting the DC coefficients of the eight luminance signals DCT in the super block. Therefore, Y _DC is directly used as the code on the low-frequency component side.

The AC component Y _AC of the block of the luminance signals Y _{0 to} Y ₇ is divided into a low band code and a high band code. The method of division is determined by the code amount in the low frequency band, like the color signal. As a result, the low frequency component code Y _LF and the high frequency component code Y _HF are obtained.

FIGS. 25 (a) and 25 (b) are diagrams showing code division in macroblock units. There are refresh blocks and non-refresh blocks in the macroblock. Of these, only the refresh block is subjected to the above-described code division, and the DC of the luminance signal that is the low frequency component is
Of the component Y _DC and the AC component of the luminance signal, the low-frequency code Y
_{0LF ~Y 7LF} and produce the luminance signal high-pass code Y _0HF ~Y _7HF a high-frequency component.

[0212] Then, a low frequency block to the head traces when the special reproduction, a DC code Y _DC luminance signal of the refresh block, the luminance signal low band code Y _0LF ~Y _7LF and the chrominance signal low-frequency encoding U _LF, V _LF Consists of.

Further, the non-trick block which the head does not trace during special reproduction is the non-refresh block and the high frequency code Y _0HF of the luminance signal of the refresh block.
˜Y _{7F H} is composed of high-frequency codes U _HF and V _HF of color signals.

26 to 29 are examples of a method of arranging trick blocks and non-trick blocks in a bitstream.
It is shown using.

26 and 27 regarding the trick block.
Will be explained.

First, the trick block is defined.

Trick block: In a recording medium such as a VCR, a block for tracing and reproducing the head during high speed reproduction. The trick block is composed of a plurality of low frequency component refresh blocks and their overhead data.

FIG. 26 shows an example of a trick block. In this example, the case where five refresh blocks of low frequency components (low frequency blocks) are put in the trick block is shown.

FIG. 27 shows the arrangement of five low frequency blocks.

In the conventional example, 2 contained in the vertical 4 columns GO ₀ , GO ₁ , GO ₂ and GO ₃ of the screen (shown in FIG. 26).
40 super blocks are refreshed. Therefore, there are 240 low frequency blocks per frame.

Of these, five low frequency blocks adjacent to each other in the vertical direction were put together to form a trick block. Figure 2
6, FIG. 27 is numbered 0 to 4 to show an example of the order of the five low frequency blocks.

Also, the vertical ID (VID) is included in the overhead data to indicate the position of the trick block in the vertical direction. The positional relationship of this vertical ID on the screen is shown at the left end of FIG.

Further, as will be described later, trick block address codes 0 to 15 are set as shown in FIG.

The vertical ID changes in the order of VID = 0 to 2,
In this example, three low frequency refresh blocks (VID = 0 to 2) are combined into one trick block.

The bitstream structure of the trick block is shown in FIG.

The trick block overhead data consists of a vertical ID, a trick block code length, a quantization level of each low frequency block, and a code indicating field / frame discrimination.

If the vertical ID is set to a predetermined number, the frame count code is selected.

In the conventional example, since a 1/11 area is refreshed per frame, a code indicating the position on the screen for refreshing is required, which is the frame count.

Further, variable length codes of five low frequency blocks are inserted into the trick block.

Next, regarding non-trick blocks, FIG.
Will be explained.

A non-trick block is defined.

Non-trick block: In a recording medium such as a VCR, a block that is not used to compose a reproduced image during high speed reproduction.

The non-trick block is composed of a high frequency component of one refresh block, 10 non-refresh blocks and its overhead data.

FIG. 28 shows the structure of the non-trick block.

For overhead data, channel I
D, non-trick block code length, quantization level, field / frame discrimination, PCM / DPCM discrimination, motion vector.

The difference between the macro block of the conventional example and the non-trick block is that the refresh block is composed of the code of the high frequency component.

FIG. 29 is a diagram showing the bitstream structure of trick blocks and non-trick blocks.

In FIG. 29, the non-trick block 55 is shown in FIG.
It has the structure shown in FIG. Here, NTBA (Non
Trick Block Address) indicates an address code of a non-trick block, and indicates that NTBA = ₁ to n ₁ are sequentially transmitted.

After sending the non-trick block, the trick block 56 is sent.

The trick block 56 has the structure shown in FIG. Here, TBA (Trick Block Addr
ess) is the address code of the trick block on the screen, and in FIG. 29, TBA = 0 to 15 is sequentially transmitted.

After sending the trick block 56, N
Non-trick block 57 with TBA = n ₁ +1 to n ₂
Is sent.

This bit stream corresponds to the output signal of the memory 48 of the code arrangement circuit 45 of FIG.

Next, a method of setting the switching point NTBA = n ₁ between the non-trick block and the trick block will be described with reference to FIG.

The point when arranging the trick block is to record the trick block in the trick sector to be reproduced at the time of high speed reproduction.

Here, a case will be described in which the average generated code amount per frame is recorded in one track and a high speed reproduction speed of double speed is realized.

FIG. 31 shows the recording position of the head trace and the trick blocks G _{0 to} G ₁₀ at the recording track and at the double speed. Sector S ₀ of the track T _0, records the trick block G _0, to the sector S ₁ of the track T ₁ recorded trick block G _1.

FIG. 30 shows the VCR data multiplex format in this case.

The figure shows the transmission data of frame 1 and frame 2.

The horizontal axis corresponds to the period of one unit, which will be described later, and the vertical axis corresponds to the number of units recorded on one track.

Since the case where one frame is recorded on one track is described here, the vertical axis also corresponds to one frame.

Here, the broken line drawn in the transmission code of each frame shows the switching point of the sector.

In the bit stream structure of FIG. 29, NTB
The method of determining A = n ₁ and NTBA = n ₂ is that the trick blocks G ₀ and G ₁ are the sector S of the track T ₀ .
_{0 so that} it can be inserted in sector S ₁ of ₀ and track T ₁
Determine the BA.

As described above, after the non-trick block and the code of the trick block are arranged, as shown in FIG. 30, a sync signal, a non-trick / trick block position, a non-trick / trick block address code, other additional information, and Record by adding an error correction code.

Since the VCR has jitter due to uneven rotation of the cylinder, track jump during special reproduction, etc.,
It is necessary to add sync signals at predetermined intervals.

Here, one period of this sync signal will be referred to as one unit.

Definition of words Unit: One period of sync in transmission data to VCR During this period, sync, additional information, non-trick / trick block position code (NTBP / TBP), non-trick / trick block address code (NTBA /
TBA) and non-trick block or trick block codes, error correction codes, etc.

FIG. 32 is an enlarged view of the VCR data multiplex format.

First, an example of a non-trick / trick block area code will be described. This code represents the projection position information of each block. In one frame,
There are 240 non-trick blocks. Also, the trick block address code is as shown in FIG.
Since there are 16 codes, the projection position can be expressed by using 256 codes. Here, the area code of the non-trick block is temporarily shown as 0 to 239, and the area code of the trick block is shown as 240 to 255.

Since each block is composed of a variable length code, the block switching point is not fixed.
Therefore, the address code of the first non-trick / trick block that enters each unit is placed at the rear of the sync signal.

Furthermore, the starting point of this block is not fixed either. Therefore, this starting point is indicated by a non-trick / trick block position code.

In the example of FIG. 32, the non-trick block address 11 of the unit number 20 is inserted as a non-trick / trick block address code after the sync, and the start point 5 of the code of this non-trick block is set to non-trick / trick.
Insert as trick block position code and record.

When arranging a trick block between non-trick blocks, the trick block position code is inserted so as to always indicate the position of the first block of the trick block.

There may be a plurality of trick blocks and non-trick blocks in the unit. in this case,
The position indicated by the trick block position code indicates the position of the (non) trick block that appears first. Therefore, the first block of the trick block is arranged so that it appears first in the unit. That is, T in FIG.
Arrange as BA = 0.

The VCR data multiplex format only adds additional information such as an index,
There is no requirement for source coding from this format. Therefore, the content of the video information is not deteriorated by this format.

The operation at the time of decoding will be described. First, the normal reproduction operation will be described.

In FIG. 33, the input terminal 58 has a VC
A signal obtained by subjecting the reproduced signal from R to reproduction waveform equalization and error correction is input.

The unit sync detection circuit 59 detects the sync signal inserted in each unit. This eliminates the influence of VTR jitter and the like. Furthermore, during special playback such as slow or high-speed playback, by detecting this sync signal, each unit can be grasped and the ID or (Non
-) Trick Block Position, (Non-) Trick Brock Addre
ss signal is detected. In the (non) trick block position detection circuit 60, the VCR Data Multiplex Format
The starting point of the (non) trick block is grasped by the (Non-) Trick Block Position signal of.

Further, the (non) trick block address detection circuit 61 grasps the projected position of the (non) trick block on the screen by the (Non-) Trick Brock Address signal of VCR Data Multiplex Format.

A signal represented by VCR Data Multiplex Format is input to the (non-) trick block separation circuit 62, and the code of the trick block and the code of the non-trick block are separated and output.

For this separation, (Non-) Trick Block Posi
tion signal and (Non-) Trick Brock Address signal are used.

The code of the trick block has the bit stream structure shown in FIG.

The trick block overhead data detection circuit 63 detects the vertical ID, the quantization level, the field / frame discrimination signal, the trick block code table, and the frame count.

The trick block memory 64 is shown in FIG.
The variable length code of the trick block shown in FIG.

At the time of writing to the memory 64, the address generation circuit 65 is operated by the Trick Brock Address signal and the vertical I
D, generate address using trick block code length frame count.

When reading the memory 64, the address generating circuit 65 uses a signal obtained by feeding back the signal of the variable length code decoding circuit 66 in addition to the signal used at the time of writing. Decoding of the variable length code and the bit stream are sequentially compared with the Huffman table to determine the code delimiter. At this time, the decoding is performed while feeding back the signal of the variable length code decoding circuit 66.

The trick block code subjected to the variable length decoding is once stored in the memory 67. During normal reproduction, this matches the phase with the code address of the non-trick block.

The sign of the non-trick block output from the (non-) trick block separation circuit 62 is input to the non-trick block overhead data detection circuit 68 and the non-trick block memory 69.

The non-trick block overhead data detection circuit 68 detects the overhead data of the non-trick block, that is, the channel ID, the non-trick block code length, the quantization level, the field / frame discrimination, the PCM / DPCM discrimination, and the motion vector detection. To do.

The non-trick block memory 69 is shown in FIG.
The variable length code shown in is stored.

At the time of writing to the memory 69, the address generation circuit 70 generates an address using the non-Trick Block Address signal, the non-trick block code length, the channel ID, and the frame count reproduced from the trick block.

When the memory 69 is read, the address generation circuit 70 uses the signal fed back from the signal of the variable length code decoding circuit 71 in addition to the signal used at the time of writing.

The output signal of the variable length code decoding circuit 71 is input to the refresh block separation circuit 72.

The non-trick block has the structure of the non-trick block shown in FIG. Therefore, by counting the EOB, the refresh high band code and the non-refresh block are separated.

The refresh high band code output from the refresh block separating circuit 72 and the refresh low band code output from the memory 67 are input to the refresh block low band / high band code synthesizing circuit 73. In order to perform this operation, memory address generating circuit 74 generates a necessary address.

This synthesis is shown in FIGS. 24 (c)-(b),
The operations (e) to (d) are performed.

That is, in the color signal blocks U and V, the low-frequency code and the high-frequency code are sequentially arranged according to the zigzag scan order.

In the luminance signal blocks Y _{0 to} Y ₇ ,
The DC code and the low-pass code and the high-pass code are sequentially arranged according to the zigzag scan order.

This constitutes the code of the refresh block.

The non-refresh block separated by the refresh block separation circuit 72 and the refresh block output from the refresh block low-frequency / high-frequency code synthesis circuit 73 are synthesized by the macroblock construction circuit 75.

This operation is the operation shown in FIG. 25 (b) → (a).

That is, refresh blocks and non-refresh blocks are sequentially arranged to form a macro block.

Further, the overhead data reconstructing circuit 7
In 6, the overhead data is reorganized from the output of the trick block overhead data detection circuit 63 and the output of the non-trick block overhead data detection circuit 68.

The output signals of the overhead data reconstructing circuit 76 are input to the circuit shown in FIG.

The operations of the inverse quantization circuit 77, the inverse DCT circuit 78, the motion compensation circuit 79, the YC separation circuit 80, and the frame delay circuit 81 are the same as the conventional operation.

At the time of high-speed reproduction, the memory address generation circuit 74 controls the reading of the memory 67 so that the arrangement of the trick blocks read from the tape and the arrangement of the macro blocks at the time of outputting the video are matched.

The macro block of the conventional example has 11 super blocks in the horizontal direction of the screen. This is also because the trick block is composed of refresh blocks and thus has one column in the vertical direction.

When the content of the video signal is not updated, the skip signal is generated by the skip signal generation circuit 82, and the data accumulated in the past is directly output by the frame delay circuit 81 and the YC separation circuit 80.

To perform this operation, the control signal of memory address generating circuit 74 is input to skip signal generating circuit 82.

As for overhead data, the output signal of the trick block overhead data detecting circuit 63 is rearranged by the overhead data reconstructing circuit 76 and transmitted.

By the above operation, the trick block can be reproduced at the time of high speed reproduction to form a reproduced image.

In this embodiment, as shown in FIG. 25, the case where the refresh block is divided into the low frequency component and the high frequency component has been described. However, the generated code amount of the refresh block is determined by the recording medium. When the value is set to the value, it is not necessary to divide the refresh block.

In this case, the low frequency block of the trick block shown in FIG. 27 is constituted by the refresh block, and the low frequency block shown in FIG.
The high frequency block 0 of the 8 non-trick blocks is deleted, and the non-trick blocks are composed of non-refresh blocks.

Further, in this case, in the decoder of FIG. 33, it is not necessary to use refresh block separating circuit 72 and refresh block low / high band code synthesizing circuit 73, and the output signal of variable length code decoding circuit 71 and the memory. The effect of the present invention can be realized by inputting the output signal of 67 to the macro block construction circuit 75.

The present invention is not limited to the above embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0305]

As described in detail above, according to the present invention,
It is possible to provide an extremely good band-compressed signal processing device that can easily obtain a good reproduced image during high-speed reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a band compression signal processing device according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a view showing a relationship between refresh blocks having frame numbers F ₅ and F ₆ and non-refresh blocks in the embodiment.

FIG. 4 is a diagram showing a track pattern in the same embodiment.

FIG. 5 is a diagram showing a head trace locus during double speed reproduction in the example.

FIG. 6 is a diagram showing refreshable refresh blocks of frames 1 to 8 in the embodiment.

FIG. 7 is a diagram showing a reproducible refresh block of frames 9 to 11 and a refresh block in which 11 frames are accumulated in the embodiment.

FIG. 8 is a diagram showing a scan order when performing zigzag scanning of DCT coefficients.

FIG. 9 is a diagram showing an example of a quantization table.

FIG. 10 is a diagram showing an example of a weighting table.

FIG. 11 is a diagram showing an example in which the same weighting table is converted into the number of bits.

FIG. 12 is a diagram showing the number of generated bits based on a quantization table.

FIG. 13 is a diagram showing the number of generated bits based on a quantization table.

FIG. 14 is a block configuration diagram showing details of a main part of the embodiment.

FIG. 15 is a diagram showing code division in the example.

FIG. 16 is a diagram showing code division in the example.

FIG. 17 is a diagram showing code division in the example.

FIG. 18 is a diagram showing code division in the example.

FIG. 19 is a block diagram showing another embodiment of the present invention.

FIG. 20 is a diagram showing the code amount of the other embodiment.

FIG. 21 is a diagram for explaining the operation of the other embodiment.

FIG. 22 is a diagram showing a refresh block of another embodiment.

FIG. 23 is a diagram showing a track pattern of another embodiment.

FIG. 24 is a view showing the symbols of trick blocks of the other embodiment.

FIG. 25 is a view showing the symbols of trick blocks of the other embodiment.

FIG. 26 is a diagram showing an address code of a trick block of the other embodiment.

FIG. 27 is a diagram showing a bitstream of trick blocks according to another embodiment.

FIG. 28 is a diagram showing a bitstream of non-trick blocks according to another embodiment.

FIG. 29 is a diagram showing a bitstream of a (non) trick block according to the other embodiment.

FIG. 30 is a diagram showing transmission data according to another embodiment.

FIG. 31 is a diagram showing a track pattern of another embodiment.

FIG. 32 is a diagram showing a structure of transmission data according to the other embodiment.

FIG. 33 is a block diagram showing a configuration example of a decoder according to the present invention.

FIG. 34 is a diagram showing a processing circuit of overhead data of the same decoder.

FIG. 35 is a block diagram showing a conventional band compression system.

FIG. 36 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 37 is a diagram showing refresh blocks that can be played back in frames 1 to 8 during normal playback in the conventional system.

FIG. 38 is a diagram showing refreshable blocks that can be reproduced in frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal reproduction in the conventional system.

FIG. 39 is a view showing a track pattern in the conventional system.

FIG. 40 is a diagram showing a head trace locus during double-speed reproduction in the conventional system.

FIG. 41 is a diagram showing refresh blocks capable of reproducing frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 42 is a diagram showing refreshable blocks that can be reproduced up to frames 9 to 11 and refresh blocks that have accumulated 11 frames during double-speed reproduction in the conventional system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27 ... Input terminal, 28 ... SYNC signal detecting circuit, 29 ... Track forming signal generating circuit, 30 ... Rotating drum, 31 ... Track forming control circuit, 32, 33 ... Input terminal, 34, 35 ... Decimator, 36 ... Input terminal, 37 ... Multiplexer, 38
... track, 39 ... code exchange circuit, 40 ... refresh block control circuit, 41 ... index insertion circuit,
42 ... Index generating circuit, 43 ... Multiplexer,
44 ... Zigzag scan circuit, 45 ... Code arrangement circuit, 4
6 ... Refresh block separating circuit, 47 ... Variable length coding circuit, 48 ... Memory, 49 ... Refresh block code dividing circuit, 50, 51 ... Variable length coding circuit, 52 ... Each refresh block code amount detecting circuit, 53 ... Refresh Block low-frequency code amount calculation circuit, 54 ... Refresh block division level setting circuit, 55 ... Non-trick block, 56 ... Trick block, 57 ... Non-trick block, 58 ... Input terminal, 59 ... Unit sync detection circuit,
60 ... (Non) trick block position detection circuit, 6
1 ... (Non) trick block address detection circuit, 62 ...
(Non) trick block separation circuit, 63 ... Trick block overhead data detection circuit, 64 ... Trick block memory, 65 ... Address generation circuit, 66 ... Variable length code decoding circuit, 67 ... Memory, 68 ... Non-trick block overhead data detection Circuits, 69 ... Non-trick block memory, 70 ... Address generation circuit, 71 ... Variable length code decoding circuit, 72 ... Refresh block separation circuit, 73 ... Refresh block low / high band code synthesis circuit, 74 ... Memory address generation circuit , 75 ... Macroblock construction circuit, 76 ... Overhead data reconstruction circuit, 77 ... Inverse quantization circuit, 78 ... Inverse DCT circuit, 79 ...
Motion compensation circuit, 80 ... YC separation circuit, 81 ... Frame delay circuit, 82 ... Skip signal generation circuit.

Claims (2)

[Claims] 1. A frame in which a (a is a positive integer) image area is formed in a video signal of one screen, and the video signal is subjected to intraframe coding processing using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoded processing using difference information between frames are created, and after the intra-frame encoded processing, the inter-frame encoded processing is applied, and this signal A band compression unit that adaptively repeats the processing method according to the motion evaluation of the input video signal, and f frames (f is an integer of f ≧ 2) as a cycle, and b units of the a regions are set for each frame. Refresh encoding processing means for periodically performing the intra-frame encoding processing on a signal in an image area, combining a plurality of blocks subjected to the refresh encoding processing to form a trick block, and refreshing Bandwidth compression signal processing apparatus characterized by being arranged between the non-trick block not subjected to No. process. 2. The band compression signal processing device according to claim 1, wherein a code indicating a code length of the trick block is added to the overhead data.