JPH06284376A - Recording/reproducing device - Google Patents

Abstract

PURPOSE:To make it possible to excellently perform a screen display without lowering screen reproduction ratio even when a variable speed reproduction is performed in a recording/reproducing device. CONSTITUTION:In a device where a screen is expressed by the frequency area each plural blocks, information compression is performed by a variable length code successively from DC components to high frequency components, and a recording and a reproducing are performed, the signal having the fixed length which is the same as the longest code word length in a variable length code cord book is taken out from the head of each block of an arbitrary super block of an information compression signal in a format conversion circuit 28, a hierarchical signal expressing the low frequency component of an image signal by fixed length data is obtained, the hierarchical signal is recorded at the stipulated location of a recording medium in a channel coding circuit 30, the hierarchical signal recorded at least of the stipulated location is reproduced in a data discrimination circuit 34, the only variable length codes which can be decoded from every block of the reproduced hierarchical, signal are decoded in a format reverse conversion circuit 36, the variable length code which can not be decoded subsequently is defined as zero and the image signal is restored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for recording and reproducing a video signal, and particularly to improve the image quality during variable speed reproduction.

[0002]

2. Description of the Related Art Recently, in the field of magnetic recording, the transition from an analog recording system to a digital recording system is progressing.

Digital recording, compared to analog recording,
Although there is no signal deterioration at the time of dubbing, it is widespread only in professional video tape recorders (VTRs) because the recording signal band is wide.

However, due to the progress of information compression technology, the amount of information required for digital recording is reduced, and the VTR for home use is reduced.
The possibility of widespread use has emerged.

Currently, in order to digitally transmit a video signal, a transmission method using a variable length coding method, an intra-frame coding process (hereinafter referred to as an intra process) and an inter-frame coding process (hereinafter referred to as an inter process). ) And a method of transmitting information by compressing information are being studied. Among these, the technique of combining the intra process and the inter process to compress and transmit the information is disclosed in, for example, the document IEEE.
Woo Paik: '' Digital compatible HD-TV Broad described in Trans.on Broadcast-ing Vol.36 No.4 DEC 1990
It is an information compression technology as shown in "cast system", and its characteristic part is explained below.

In FIG. 19, the video signal input to the terminal 1 is supplied to the subtraction circuit 2 and the motion detection circuit 3, respectively. In the subtraction circuit 2, a subtraction process described later is performed, and its output is input to the discrete cosine transform (hereinafter DCT) circuit 4. The DCT circuit 14 has eight horizontal pixels,
Eight vertical pixels are taken in as a unit block (8 × 8 pixels = 64 pixels), and a coefficient obtained by converting the pixel array from the spatial domain to the frequency domain is output (see FIG. 20). Then, each coefficient is quantized by the quantization circuit 5. In this case, the quantization circuit 5 has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 5 is provided with a plurality of quantizing tables so that the amount of information generated and the amount of information sent can be kept within a certain range.

The coefficient data output from the quantizing circuit 5 is zigzag-scanned from the low band to the high band for each unit block (see FIG. 21), and then input to the variable length coding circuit 6. Variable length coding is performed by combining a number (run length) following zero coefficients and a non-zero coefficient as one set.
The encoder is a variable-length encoder whose code length varies depending on the frequency of occurrence of Huffman code or the like. The variable-length coded data is input to the buffer circuit 7, read at a prescribed speed, and then output to the terminal 8.

The output of the quantization circuit 5 is input to the inverse quantization circuit 9 and inversely quantized. Further, the output of the inverse quantization circuit 9 is input to the inverse DCT circuit 10 and returned to the original signal. This signal is input to the frame delay circuit 12 via the adder circuit 11. The output of the frame delay circuit 12 is supplied to the motion compensation circuit 13 and the motion detection circuit 3, respectively. The motion detection circuit 3 compares the input signal from the terminal 1 with the output signal of the frame delay circuit 12,
The overall motion of the image is detected and the phase position of the signal output from the motion compensation circuit 13 is controlled. For videos,
Compensation is performed so that the original image and the image one frame before match. The output of the motion compensation circuit 13 can be supplied to the subtraction circuit 2 via the switch 14 and can also be fed back from the addition circuit 11 to the frame delay circuit 12 via the switch 15.

Next, the basic operation of the above system will be described.

The basic operation of this system includes intra processing and inter processing.

The intra process is performed as follows. When this process is performed, both switches 14 and 15 are off. The video signal at the terminal 1 is transformed from the spatial domain to the frequency domain by the DCT circuit 4 and quantized by the quantization circuit 5. This quantized signal is output to the terminal 8 via the buffer circuit 7 after undergoing variable length coding processing. The quantized signal is supplied to the inverse quantization circuit 9 and the inverse DCT.
The circuit 10 restores the original signal and the frame delay circuit 12 delays it. Therefore, in the case of intra processing, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra processing is performed in a predetermined block unit at an appropriate cycle in order to prevent the scene change of the input video signal and the propagation of the error.

Next, the inter processing will be described. When the inter process is executed, both the switches 14 and 15 are turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 2. This difference signal is input to the DCT circuit 4, converted from the spatial domain to the frequency domain, and then quantized by the quantization circuit 5. The difference signal and the motion-compensated predicted video signal are added to the frame delay circuit 12 by the adder circuit 11 and input. This is the same as inputting the input video signal to the frame delay circuit 12.

Next, the definition of a set of pixels processed by the above information compression system will be described.

Block: An area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: luminance signal in horizontal direction 4
Block, an area consisting of two blocks in the vertical direction. This area contains one block each of the color signals U and V (see FIG. 22). Macro block: 11 super blocks in the horizontal direction. One frame is composed of 4 macro blocks in the horizontal direction and 60 macro blocks in the vertical direction (see FIG. 23).

A block is a unit of DCT processing, and a super block is a unit of inter processing. A macroblock is a unit of data transmission.

The intra-processed image signal has low compression efficiency, but can be restored to the original image independently. However, the inter-processed image signal has a high compression efficiency because it sends only the differential signal, but cannot be restored unless the image signal of the previous frame is completely restored. Therefore, the intra process is partially performed as a countermeasure.

In this information compression system, at least one super block in a macro block is intra-processed so that it makes a cycle of 11 super blocks in 11 frames (see FIG. 24). The super block is forcibly refreshed at a constant cycle (see FIG. 25) so that error propagation from the previous frame, which is a problem in inter processing, does not continue. Further, this processing makes the code rates for each frame substantially uniform. By the way, the above information compression system is used as an encoder for compressing information of a television signal.

Consider recording the above transmission signal in a VTR.

When the transmission signal of the above information compression system is recorded on the VTR as it is and is reproduced at a tape speed different from that at the time of recording (hereinafter, variable speed reproduction), all recording tracks can be reproduced by normal reproduction as shown in FIG. But (Fig. 26
(A)), in the + 4 × speed reproduction, the recording track is obliquely traversed and reproduced (FIG. 26 (B)), and therefore all the recorded data cannot be reproduced. Therefore, at this time, the reproduced image must be composed only of the intra-processed signal that can be independently restored to the original image without being affected by the image of the previous frame. However, since the intra-processed signal has low compression efficiency, the information amount is much larger than that of the inter-processed signal. Further, since all the signals are compressed by the variable length coding, the position of the signal on the tape at the specific position on the screen cannot be specified because it changes depending on the compression state.

Therefore, as shown in FIG. 27, the reproduced signal becomes intermittent at + 4 × speed as compared with the normal reproduction, and therefore the number of intra-processed blocks included therein is small. In other words, the screen reproduction rate is lowered and it becomes difficult to identify the screen contents.

[0022]

As described above, when the magnetic tape is reproduced at a speed different from that at the time of recording in the VTR for recording the information-compressed signal by the conventional information compression system, the screen reproduction rate is lowered, There is a problem that it is difficult to identify the screen contents.

Therefore, an object of the present invention is to provide a recording / reproducing apparatus capable of obtaining a good and stable reproduced image even in the above case.

[0024]

According to the present invention, one screen is divided into a plurality of blocks, and each block is expressed in the frequency domain,
When the data having a length equal to or longer than the longest code word length of the variable length code is taken out from each block of the image signal whose information is compressed by using the variable length code in order from the DC component to the high frequency component, the data is defined when the VTR is recorded. Record at the position of. In the variable speed reproduction, the reproduction speed is controlled to reproduce the data recorded at the specified position and the decoding is performed so that a good and stable signal can be obtained.

[0025]

When the data having a length equal to or longer than the longest code word length of the variable length code is extracted, at least the DC component coefficient among the coefficients expressed in the frequency domain of the block is included. Therefore, after the decodable coefficient included in the data having the length of the longest codeword length or more is processed as the coefficient that cannot be decoded thereafter as zero, the resolution is lowered, but the screen content can be discriminated. A reproduced image can be obtained. Also, since the amount of data is limited, it is possible to record at a specified position on the tape with a VTR, and at the time of variable speed reproduction, the contents of the screen can be discriminated by reproducing the data at this specified position, and a stable reproduction image can be obtained. Can be obtained.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. First, terminals 20, 21, and 2 which will be described from the recording system
The R, G, and B video signals input to 2 are converted by the preprocessor 26 into a multiplexed signal of a luminance signal Y and color signals U and V.

FIG. 2A shows a block diagram of the preprocessor 26.

R input to terminals 40, 41 and 42,
Each of the G and B video signals is converted from an analog signal to a digital signal by analog-to-digital (A / D) conversion circuits 43, 44 and 45. Then, the matrix conversion circuit 46
Then, the R, G and B signals are matrix-operated and converted into a luminance signal Y and color signals U and V. With respect to the color signals U and V, the thinning circuits 47 and 48 thin pixels to 1/4 in the horizontal direction and 1/2 in the vertical direction, and then the luminance signal Y.
At the same time, the multiplexer 49 converts the signals into one system of multiplexed signals and outputs the multiplexed signals to the terminal 50.

Returning to FIG. 1, the signal thus preprocessed is subjected to data compression by the data compression circuit 27. The data compression circuit 27 is a circuit similar to the circuit described above. The capacity of the buffer circuit at the output stage of the data compression circuit 27 is one frame, and the data rate is controlled so that it does not flow. The next compressed signal is
The format conversion circuit 28 converts the signal transmission format.

FIG. 2B is a block diagram of the format conversion circuit 28.

The signal input from the terminal 70 is decoded by the variable length code decoding circuit 71 into a variable length code and input to the control circuit 82. The control circuit 82 determines whether the variable length code from the terminal 70 is separated, and the multiplexer 72
Data is separated for each macroblock input at.

The longest code length of the variable length code used in this embodiment is 14 bits, and the length of the fixed length data cut out from the compressed data is 14 bits. The macro block if there is one intra treated superblock refresh (Fig. 3 (A)), 8 two luminance signal blocks constituting the super block (Y ₁ to Y ₈₎ and two color signal block 14bit from the beginning of each (U, V)
The data is cut out (Fig. 3 (B)). At this time, if the block data ends within 14 bits like Y ₅ in FIG. 3B, blank data BK is added behind it to secure a 14-bit data length. Note that DC means a direct current component and AC means an alternating current component.
In this way, the fixed length data of the refresh super block cut out by the multiplexer 72 is temporarily stored in the memory 76 (FIG. 4 (G)). The refresh super block (FIG. 3C) other than the cut-out fixed-length data is output from the multiplexer 72, added with a pointer indicating the data length for each block by the demultiplexer 73, and then temporarily stored in the memory 77 ( FIG. 4 (E)). The above pointer is created by the pointer generation circuit 79 from the decoding content from the variable length code decoding circuit 71 and supplied to the demultiplexer 73.

The pointer insertion timing is sent from the control circuit 82 to the demultiplexer 73.

Data other than the refresh super block (FIG. 3 (D)) is output from the multiplexer 72, a demultiplexer 74 adds a pointer indicating the data length for each break of the data, and then temporarily stored in the memory 78. (FIG. 4 (F)). The above insertion index is created by the pointer generation circuit 79 from the decoding content from the variable length code decoding circuit 71 and supplied to the demultiplexer 74. The pointer insertion timing is the control circuit 82.
Sent to the demultiplexer 74.

Therefore, the low frequency component (fixed length) of the refresh super block shown in FIG. 15G is stored in the memory 76, and the high frequency component (variable length) of the refresh super block is stored in the memory 77. The memory 78 stores data of blocks other than the refresh super block.

The data thus separated is organized into macroblock data for each recording data frame of the VTR, which will be described later, and then is demultiplexed by the demultiplexer 75.
The control circuit 82 outputs the output timing in the order of the header, the fixed length portion of the refresh super block, the remaining portion of the refresh super block, and the data other than the refresh super block to the terminal 81 as the multiplexed signal with the header as shown in FIG. Controlled and output.

The header includes location data indicating the position of the refresh super block on the screen, pointer data indicating the data start position of data other than the refresh super block based on the header, and quantization control data at the time of data compression. ing. The header is created by the header generation circuit 80 according to the decoding content of the variable length code decoding circuit 71 and added by the demultiplexer 75.

Returning to FIG. 1, an error correction code adding circuit 29 adds an error correction code to the format-converted signal. The error correction code used here is a Reed-Solomon product code, which is an outer code (C2) (68, 6).
2), the inner code (C1) (95, 87) is used.

The recording data format of the VTR is shown in FIG.

Further, the error correction code adding circuit 29 has an index for identifying a recording block and a synchronization signal (SYNC).
Is also added to create a data frame to be recorded in the VTR.

Returning to FIG. 1, the output of the error correction code adding circuit 29 is modulated by the NRZI coding in the channel coding circuit 30, passes through the switch 31, and passes through the magnetic head 3.
It is recorded on the magnetic tape 33 by 2A and 32B.

Next, the reproducing system will be described.

In FIG. 1, the signal recorded on the magnetic tape 33 is reproduced by the magnetic heads 32A and 32B, passes through the switch 31, and is input to the data identification circuit 34. The data identification circuit 34 equalizes the waveform of the reproduction signal and converts it to a digital signal. The digitized reproduced signal is subjected to error correction by the error correction circuit 35. The format-inverse conversion circuit 36 restores the data format of the error-corrected signal.

FIG. 7 is a block diagram of the format inverse conversion circuit 36.

The format reverse conversion circuit 36 has two operation modes, a normal reproduction mode and a variable speed reproduction mode.
First, the normal reproduction mode will be described. The reproduction signal of FIG. 5 (H) input to the terminal 91 has the information in the header decoded by the header decoding circuit 92, and the input signal of the terminal 91 is multiplexed by the multiplexer 93 into the fixed length portion of the refresh super block and the rest of the refresh super block. And the data other than the refresh super block are stored in the temporary memories 94, 95 and 96, respectively. When the data for one data frame of the VTR is stored, the data other than the refresh super block stored in the memory 96 is selected by the control circuit 100 by the demultiplexer 101 and read from the memory 96. At the same time, the pointer detection circuit 99 detects a pointer indicating a data delimiter in the read data and sends it to the control circuit 100. Control circuit 10
At 0, it is judged from this pointer until the data delimiter,
Data other than the refresh super block is read from the memory 96.

Next, the control circuit 100 operates the memory 9
6, the read operation is switched to the memory 94, the input of the demultiplexer 101 is switched to the output of the switch 103, and the output is output to the terminal 105. Switch 103
During normal reproduction, the output of the memory 94 is the switch 103
Output.

The refresh super block fixed length portion stored in the memory 94 is read for one block. At this time, the read data is the variable length code decoding circuit 9
If the read data is decoded in step 7 and read out by the control circuit 100 and is ended in the middle of reading, the memory 94 is controlled to skip the subsequent blank data.

Next, the control circuit 100 operates the memory 9
4, the read operation is switched to the memory 95, the demultiplexer 101 selects the output of the memory 95, and the data of the remaining portion of the refresh super block is read from the memory 95. At this time, the read data is also input to the pointer detection circuit 98, and the pointer detection circuit 9
Reference numeral 8 detects a pointer indicating a break in the read data and sends it to the control circuit 100. In the control circuit 100, the data of the remaining portion of the refresh super block is read from the memory 95 until it is judged from this pointer and the data is divided.

[0050] and later, reading the same repeated the memory 94 → memory 95 9 times, to read out of the 10 refresh blocks _{(Y 1 ~Y 8, U,} V). Next, returning to the reading of the memory 96, the reading is similarly performed according to the pointer. By the above operation, the data of one macro block is restored. FIG. 8 shows a diagram showing the above operation.

Next, the variable speed reproduction mode will be described.

The reproduction signal of FIG. 5 (H) inputted to the terminal 91 has the information in the header decoded by the header decoding circuit 92. The input signal of the terminal 91 is divided into a fixed length portion of the refresh super block, the remaining portion of the refresh super block, and data other than the refresh super block by the multiplexer 93 and stored in the temporary memories 94, 95 and 96, respectively.

When data for one VTR data frame is stored in the memories 94, 95, 96, the memory 9
The data of the fixed length portion of the refresh super block stored in No. 4 is read by the control circuit 100. The read data is the deshuffling circuit 1
By 02, the refresh super block data whose reproduction order is different for variable speed reproduction is rearranged in the order of the screen position.
When the refresh superblocks of two or more different phases are reproduced, the refresh superblocks are combined on the macroblock as shown in FIG. The data thus rearranged is input to the switch 103 and the super block determination circuit 106. Switch 10
3 selects the output side of the deshuffling circuit 102.

The fixed-length part data of the refresh super block is output from the deshuffling circuit 102 according to the transmission order of the macro blocks. Based on this output signal, the super block determination circuit 106 detects a refresh super block that has not been reproduced from the VTR, and the control circuit 100 switches the demultiplexer 101 to the zero code generation circuit 104 at that timing.
The inter-process zero code is sent to the terminal 105.

Sending the zero code of the inter processing means that the image information of the super block retains the previous value when the compressed data is restored.

In the super block determining circuit 106, when the data of the refresh super block fixed length portion exists, the control circuit 100 switches the demultiplexer 101 to the switch 103 side, and the data of the refresh super block fixed length portion is the terminal. It is output to 105. At this time, the output of the switch 103 is decoded by the variable length code decoding circuit 97 and input to the control circuit 100. The control circuit 100 detects the decodable data from the fixed length data of the refresh super block as shown in FIG. 10, and replaces the undecodable data thereafter with the zero code from the zero code generation circuit 104. It is added by switching the multiplexer 101.

As a result, during variable speed reproduction, the refresh super block in which the high frequency band data is limited is transmitted to the next stage.

Returning to FIG. 1, the data processed by the format reverse conversion circuit 36 as described above is subjected to the decompression process of the data compressed by the data decompression circuit 37.

FIG. 11A shows a block diagram of the data restoration circuit 37.

There are intra processing and inter processing in the restoration processing. First, the intra processing will be described.

The data input from the terminal 110 is temporarily stored in the buffer circuit 111 and read out in a data unit for one frame. The variable length code decoding circuit 112 decodes the variable length code of the read data, and after the inverse quantization circuit 113 performs the inverse quantization, the inverse DCT circuit 114.
Return the data expressed in the frequency domain to the data in the spatial domain. In the intra processing, the switch 118 is in the off state, and the output of the inverse DCT circuit 114 is the addition circuit 1
15 (Since the switch 118 is in the off state, the inverse DCT
Nothing is added to the output of the circuit 114), terminal 119
Is output to. At the same time, the output of the adder circuit 115 is delayed by one frame by the one-frame delay circuit 116, and
Motion compensation is performed by the motion compensation circuit 117 based on the motion information from 0, and prediction data for inter-process data restoration is created.

In the inter processing, the same processing as the intra processing is performed up to the inverse DCT circuit 114. In the inter process, the switch 118 is in the ON state, and the adder circuit 115 adds the prediction data from the motion compensation circuit 117 to the data from the inverse DCT circuit 114 to restore the data and output it to the terminal 119. It The restored data is input to the 1-frame delay circuit 116, and predictive data for inter-process data restoration is created in the same manner as in the intra processing.

Returning to FIG. 1, the data restored by the data restoration circuit 37 is converted by the post processor 38 from one system of Y, U, V multiplexed signals into three systems of R, G, B signals, and the terminal 23. , 24, 25. FIG. 11 (b)
A block diagram of the post processor 38 is shown in FIG.

The multiplexed signal of Y, U and V input from the terminal 51 is separated into three systems of Y, U and V by the demultiplexer 52. U and V are 1 / in the horizontal direction by the interpolation circuits 53 and 54.
4. Pixels decimated to 1/2 in the vertical direction are restored by interpolation.

The interpolated U, V and Y are matrix-converted from Y, U, V into R, G, B by an inverse matrix conversion circuit 55. The matrix-converted R, G, B signals are converted from digital signals to analog signals by D / A conversion circuits 56, 57, 58 and output to terminals 59, 60, 61.

In the VTR of this embodiment, for example, four recording tracks form one data frame, and the data recorded in each segment is a data stream having a structure as shown in FIG. 12B. Record on tape in a format such as. The header + refresh block fixed length part (A) is divided into two parts, which are arranged on the tape lower end side of segment 1 and the tape upper end side of segment 4 (FIG. 12).
(a), A (1), A (2)).

Next, the remaining portion of the refresh block is divided into two (B), and one of them is arranged subsequent to A (1) of segment 1. When the area of the segment 1 is exceeded, the overflow portion is arranged from the lower end side of the tape of the segment 2 (FIG. 12 (a), B (1)). The other one is arranged from the upper end side to the lower end side of the tape, following A (2) of segment 4. When the area of the segment 4 is exceeded, the overflow portion is arranged from the upper end side of the tape of the segment 3 (FIG. 12 (a), B (2)). Data other than the refresh block is arranged in the remaining area (see FIG. 12).
(a), C).

FIG. 13 shows the data arrangement on the tape thus recorded.

FIG. 14 shows a trace pattern of the magnetic head when reproducing at +4 speed on such a tape format.

At + 4 × speed, the magnetic head traces on the fixed length portion of the refresh superblocks arranged in the segments 1 and 4, and as shown in FIG. 15, the refresh superblock fixed length portion is always included in the reproducible envelope. It is included. This is because the data in the fixed length part of the refresh block is 4 per video signal frame.
X60 x 13 x 10 = 33600 bits, where 4x60 is the number of refresh superblocks in one screen 13 is the number of fixed-length bits 10 is the number of blocks in one superblock Also, the information compression system used here (Fig. 19) is
Since the buffer circuit 7 having a capacity of one frame is provided, the VTR data frame contains only video signals of at most two frames.

Therefore, assuming that there is a fixed length part of maximum 33600 (bits) × 2 (frames) / 8 (bits) = 8400 (bytes), the length of the refresh superblock fixed length part in one track is one track. Total [(8400/2) / {84 × (5 × 62 + 30}] × 100 = 15% (8400/2) is a fixed length part recorded on one track {84 × (5 × 62 + 30} is one track This is because the total amount of data will be less than or equal to it.

Therefore, in the + 4 × speed reproduction, the fixed length portion of the refresh super block recorded on the tape can be entirely reproduced, so that the resolution of the image is lowered, but the screen reproduction rate can be maximized.

Further, as shown in FIG. 16, two refresh superblock fixed length parts are taken per block (refresh superblock fixed lengths 1 and 2), and the refresh superblock fixed length parts are shown on the tape as shown in FIG. By arranging the data in order, the screen is reproduced with the refresh super block fixed length data 1 including the low frequency data at + 4 × speed, and the refresh can be continuously reproduced at + 2 × speed reproduction as shown in FIG. By connecting and processing the super block fixed length data 1 and 2, more variable length codes than the fixed length data 1 can be decoded, so that the resolution of the reproduced image is higher than that of the +4 speed reproduction. Can be improved.

[0074]

As described above in detail, according to the present invention,
Even when performing variable speed reproduction, it is possible to provide a very good recording / reproducing apparatus capable of performing good screen display without lowering the screen reproduction rate.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a preprocessor and a format conversion circuit of FIG.

FIG. 3 is a diagram for explaining the operation of a format conversion circuit.

FIG. 4 is a diagram for similarly explaining the operation of the format conversion circuit.

FIG. 5 is a diagram for explaining the operation of the format conversion circuit.

FIG. 6 is a diagram showing an example of a data format obtained by the present invention.

7 is a diagram showing a configuration example of the format inverse conversion circuit of FIG.

FIG. 8 is a diagram for explaining the operation of the format inverse conversion circuit.

FIG. 9 is a diagram for explaining a synthesis process of a refresh super block.

FIG. 10 is a diagram for explaining processing of reproduced block data.

FIG. 11 is a diagram showing a configuration example of a data restoration circuit and a post processor.

FIG. 12 is a diagram showing a data frame on a tape and a data stream after format conversion according to the present invention.

FIG. 13 is a diagram showing an example of data arrangement on a tape obtained by the system of the present invention.

FIG. 14 is an explanatory diagram of a trace pattern when the system of the present invention performs quad speed reproduction.

FIG. 15 is a diagram showing reproduction data similarly obtained at 4 × speed reproduction.

FIG. 16 is a diagram showing an example of a block configuration according to another embodiment of the present invention.

17 is a diagram showing a data arrangement on a tape having the block configuration of FIG.

FIG. 18 is a diagram showing a trace pattern when the tape having the data arrangement shown in FIG. 17 is reproduced at double speed.

FIG. 19 is an explanatory diagram of the basic configuration of the information compression system.

FIG. 20 is an explanatory diagram of the principle of discrete cosine transform performed in the information compression system.

FIG. 21 is an explanatory diagram of zigzag scanning executed in the quantization processing.

FIG. 22 is a diagram showing a configuration of a super block.

FIG. 23 is a diagram showing a screen configuration using macroblocks and a macroblock structure.

FIG. 24 is a diagram showing the progress of data refresh in a macro block.

FIG. 25 is a view showing the on-screen patrol situation of data refresh.

FIG. 26 is a diagram showing an example of a trace pattern during variable speed reproduction in a VTR.

FIG. 27 is a diagram showing an example of a reproduction output envelope during variable speed reproduction.

[Explanation of Codes] 26 ... Preprocessor, 27 ... Data compression circuit, 28 ...
Format conversion circuit, 29 ... Error correction circuit, 30 ... Channel coding circuit, 31 ... Switch, 32A,
32B ... Magnetic head, 33 ... Magnetic tape, 34 ... Data identification circuit, 35 ... Error correction circuit, 36 ... Format reverse conversion circuit, 37 ... Data restoration circuit, 38 ... Post processor.

Claims (3)

[Claims] 1. A screen is divided into a plurality of blocks, and an image signal expressed in the frequency domain for each block is information-compressed in order from a DC component to a high frequency component by using a variable length code for each block. In the recording / reproducing apparatus for recording / reproducing the information-compressed signal, the length of the variable-length code is greater than or equal to the maximum codeword length in the codebook from the beginning of the information-compressed signal for each block Recording / reproducing, comprising means for taking out and connecting signals to create a hierarchical signal in which a low-frequency component of an image signal is represented by fixed length data, and means for recording the hierarchical signal at a prescribed position of a recording medium. apparatus. 2. One screen is divided into a plurality of blocks, and the image signal expressed in the frequency domain for each block is information-compressed for each block in order from a DC component to a high frequency component by using a variable length code. In the recording / reproducing apparatus for recording / reproducing the information-compressed signal, the length of the variable-length code is greater than or equal to the maximum codeword length in the codebook from the beginning of the information-compressed signal for each block Means for taking out and connecting the signals to create a hierarchical signal in which the low-frequency component of the image signal is represented by fixed length data; means for recording the hierarchical signal at a specified position of a recording medium; Means for reproducing a signal layer indicating a low-frequency component recorded at a specified position of a recording medium, and decoding only a variable length code that can be decoded from a signal for each block of the reproduced signal layer, It considers all zeros variable-length code which can not be later decoded is, the recording and reproducing apparatus characterized by comprising a means for restoring the image signal. 3. The means for creating the hierarchical signal, when extracting a signal having a fixed length same as the longest codeword length in a codebook of a variable length code from the head of the information-compressed signal for each block, 2. The recording / reproducing apparatus according to claim 1, further comprising means for extracting a plurality of image signals from the head and dividing the image signal into a plurality of layers.