JPH06244358A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06244358A JPH06244358A JP2652493A JP2652493A JPH06244358A JP H06244358 A JPH06244358 A JP H06244358A JP 2652493 A JP2652493 A JP 2652493A JP 2652493 A JP2652493 A JP 2652493A JP H06244358 A JPH06244358 A JP H06244358A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal package
- heat sink
- package
- bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は金属パッケージと回路部
及びヒートシンクを一体にした半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a metal package, a circuit portion and a heat sink are integrated.
【０００２】[0002]
【従来の技術】従来の半導体装置の一例を、図１０を基
に説明する。この半導体装置は製品化されており、セラ
ミックパッケージ１０と回路部１２が一体化している。
なお１はワイヤ、２ははんだ、３は裸ＩＣチップ、５は
リードピン、８は導体膜、９はメタルカバーである。2. Description of the Related Art An example of a conventional semiconductor device will be described with reference to FIG. This semiconductor device has been commercialized, and the ceramic package 10 and the circuit portion 12 are integrated.
1 is a wire, 2 is a solder, 3 is a bare IC chip, 5 is a lead pin, 8 is a conductor film, and 9 is a metal cover.
【０００３】図１１は、例えば特開平３−２８５３４７
号公報などに見られる、従来の半導体装置の他の例を示
している。この半導体装置では、金属（メタル）パッケ
ージ６と、回路基板であるセラミック基板１１が一体化
している。金属パッケージ６内では、はんだ２や接着剤
によりセラミック基板１１が固定されている。また金属
パッケージ６に放熱性が要求される場合は、金属パッケ
ージ６をヒートシンク材料１３に、ネジ１４等で固定す
る。なお図１１において、１はワイヤ、３は裸ＩＣチッ
プ、４はガラス、５はリードピン、９はメタルカバーで
ある。FIG. 11 shows, for example, Japanese Patent Laid-Open No. 3-285347.
Another example of a conventional semiconductor device, which is found in Japanese Unexamined Patent Publication (Kokai), is shown. In this semiconductor device, a metal package 6 and a ceramic substrate 11, which is a circuit substrate, are integrated. In the metal package 6, the ceramic substrate 11 is fixed by the solder 2 or an adhesive. If the metal package 6 is required to have heat dissipation, the metal package 6 is fixed to the heat sink material 13 with screws 14 or the like. In FIG. 11, 1 is a wire, 3 is a bare IC chip, 4 is glass, 5 is a lead pin, and 9 is a metal cover.
【０００４】[0004]
【発明が解決しようとする課題】ところで図１０に示す
従来技術では、セラミックパッケージ１０を焼成により
製造しているため、次のような問題がある。 寸法精度が±0.５程度と悪い。 ヒートシンクとの一体化ができない。 大型パッケージ（最大５０mm程度）の製造が困難。 １２５℃以上の環境での使用ができない。By the way, in the prior art shown in FIG. 10, since the ceramic package 10 is manufactured by firing, there are the following problems. The dimensional accuracy is poor at about ± 0.5. Cannot be integrated with heat sink. It is difficult to manufacture large packages (up to about 50 mm). It cannot be used in environments above 125 ° C.
【０００５】また図１１に示す従来技術では、次のよう
な問題があった。 セラミック基板（回路部）１１，メタルパッケージ６
及びヒートシンク１３の一体構造ができなかった。 裸ＩＣチップ３からヒートシンク１３までの熱抵抗が
大きく、１２５℃以上の環境で長時間使用できなかっ
た。 部品点数が多く、製造工程が複雑でありコスト高とな
っていた。Further, the conventional technique shown in FIG. 11 has the following problems. Ceramic substrate (circuit part) 11 and metal package 6
Also, the heat sink 13 could not be integrally formed. The thermal resistance from the bare IC chip 3 to the heat sink 13 was large, and it could not be used for a long time in an environment of 125 ° C. or higher. The number of parts was large, the manufacturing process was complicated, and the cost was high.
【０００６】結局、裸ＩＣチップを有し、この裸ＩＣチ
ップを外気から密閉する封止部材を有する半導体装置
は、次に示す要求（１）〜（３）があるのに対し、従来
技術では前述したように多くの問題があり、この要求を
実現することができない。 （１）金属パッケージ，回路部及びヒートシンクの一体
化。 （２）寸法の大型化（一辺５０mm以上）及び寸法精度の
向上（±0.１mm以下）。 （３）１２５℃以上の環境での長期運用。具体的には１
４０℃の環境で長期使用できる。After all, the semiconductor device having the bare IC chip and the sealing member for sealing the bare IC chip from the outside air has the following requirements (1) to (3), whereas in the conventional technique. As mentioned above, there are many problems and this requirement cannot be fulfilled. (1) Metal package, circuit part and heat sink are integrated. (2) Larger size (50 mm or more per side) and improved dimensional accuracy (± 0.1 mm or less). (3) Long-term operation in an environment of 125 ° C or higher. Specifically 1
It can be used for a long time in an environment of 40 ° C.
【０００７】本発明は、上記従来技術に鑑み、一体化構
造をした大寸法で高温環境で使用できる半導体装置を提
供することを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned prior art, it is an object of the present invention to provide a semiconductor device having a large size and capable of being used in a high temperature environment.
【０００８】[0008]
【課題を解決するための手段】裸ＩＣチップを外気から
密閉した本発明の半導体装置は、熱伝導性に優れたＣｕ
Ｗ材料等を使った金属パッケージとヒートシンクを一体
にした上で、このＣｕＷ材料等のパッケージ内部表面に
直接、真空蒸着法を使って薄い絶縁膜（Ａｌ2Ｏ3，Ｓｉ
Ｏ2 等）及び導体膜（Ｃｒ，Ｎｉ，Ａｌ，Ａｕ，Ａｇ
等）を形成し、エッチング法で回路部を製造したもので
ある。The semiconductor device of the present invention in which a bare IC chip is sealed from the outside air is made of Cu excellent in thermal conductivity.
After a metal package using W material etc. and a heat sink are integrated, a thin insulating film (Al 2 O 3 , Si
O 2 etc.) and conductor film (Cr, Ni, Al, Au, Ag)
Etc.) and the circuit part is manufactured by an etching method.
【０００９】この回路部は次の製造法で容易に実現する
ことができる。まず、ＣｕＷ，Ｃｕ，Ｆｅ−Ｎｉ合金か
ら成る金属パッケージ内部表面を研磨し、表面あらさ0.
５〜１.0μｍＲＭＳ以下に仕上げる。この研磨には電解
複合研磨法やバフ研磨法が使用される。次に、Ｎｉ材料
を１μｍ程度成膜する。これには電解メッキ法や真空蒸
着法を使うことができる。このＮｉ膜を前述した研磨法
で表面あらさ0.５μｍＲＭＳ以下に表面を仕上げる。This circuit section can be easily realized by the following manufacturing method. First, the inner surface of a metal package made of CuW, Cu, and Fe-Ni alloy is polished to a surface roughness of 0.
Finish to 5 to 1.0 μm RMS or less. An electrolytic composite polishing method or a buff polishing method is used for this polishing. Next, a Ni material is formed into a film of about 1 μm. For this, an electrolytic plating method or a vacuum deposition method can be used. The surface of this Ni film is finished to have a surface roughness of 0.5 μm RMS or less by the above-mentioned polishing method.
【００１０】次に、Ａｌ2Ｏ3，ＡｌＮ，ＳｉＯ2 等の絶
縁膜を３〜１５μｍ成膜し金属パッケージと絶縁を取
る。この成膜には真空蒸着法を用いて行う。次に絶縁膜
の上にＣｒ，Ａｌ，Ａｕ，Ａｇ，Ｔｉ，Ｎｉ等適当な導
体材料を用途により１つあるいは複数の材料を選び真空
蒸着法により成膜を行う。この膜を化学的にエッチング
し、回路に加工する。エッチングに使う溶液は、導体材
料により選定する必要があるが、Ａｌ材料ならリン酸溶
液を使えば信号線幅は最小２０μｍまで容易にエッチン
グできる。また、この工程を繰り返すことで多層化が可
能で、５層程度までは同一手法で実現できる。ただし、
層間接続穴の加工には絶縁膜の化学的エッチングが必要
であり、Ａｌ2Ｏ3膜は、リン酸溶液でエッチングでき
る。Next, an insulating film of Al 2 O 3 , AlN, SiO 2 or the like is formed to a thickness of 3 to 15 μm to insulate the metal package. This film formation is performed using a vacuum vapor deposition method. Next, one or a plurality of suitable conductor materials such as Cr, Al, Au, Ag, Ti, Ni, etc. are selected on the insulating film according to the use, and a film is formed by a vacuum evaporation method. This film is chemically etched and processed into a circuit. The solution used for etching needs to be selected depending on the conductor material, but if the material is Al, phosphoric acid solution can be used to easily etch the signal line to a minimum width of 20 μm. Further, by repeating this process, it is possible to form a multilayer, and up to about 5 layers can be realized by the same method. However,
Chemical etching of the insulating film is required for processing the interlayer connection hole, and the Al 2 O 3 film can be etched with a phosphoric acid solution.
【００１１】[0011]
【作用】本発明により、金属パッケージと回路部とヒー
トシンクを一体として製造することが可能となる。これ
により、半導体装置の半導体と外部周囲環境間の熱抵抗
θjcを0.３℃／ｗ以下にすることができ、周囲環境温度
が１４０℃においても、内部半導体の種類によっては長
期運用が可能となった。また、金属パッケージを使用し
ているため半導体装置の大型化及び±0.１mmの高寸法精
度が可能になった。According to the present invention, the metal package, the circuit portion and the heat sink can be integrally manufactured. As a result, the thermal resistance θ jc between the semiconductor of the semiconductor device and the external ambient environment can be reduced to 0.3 ° C / w or less, and long-term operation is possible depending on the type of internal semiconductor even when the ambient temperature is 140 ° C Became. Further, since the metal package is used, the semiconductor device can be upsized and the dimensional accuracy can be as high as ± 0.1 mm.
【００１２】[0012]
【実施例】以下に本発明の実施例を図面に基づき詳細に
説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１３】＜第１実施例＞図１及び図２を参照して第
１実施例を説明する。両図に示すようにＣｕＷ材料によ
りなる金属パッケージ６にはヒートシンク６ａが一体に
形成されており、金属パッケージ６の内部表面に、真空
蒸着法及びエッチング法により絶縁膜７と導体膜８とで
なる二層の回路部１２を直接製造している。裸ＩＣチッ
プ３は、はんだ２により固定されると共に、ワイヤ１で
ボンディングされて回路部１２と接続されている。なお
４はガラス、５はリードピン、９はメタルカバーであ
る。<First Embodiment> A first embodiment will be described with reference to FIGS. 1 and 2. As shown in both figures, a heat sink 6a is integrally formed on the metal package 6 made of a CuW material, and an insulating film 7 and a conductor film 8 are formed on the inner surface of the metal package 6 by a vacuum deposition method and an etching method. The two-layer circuit part 12 is directly manufactured. The bare IC chip 3 is fixed by the solder 2 and bonded by the wire 1 to be connected to the circuit section 12. In addition, 4 is glass, 5 is a lead pin, and 9 is a metal cover.
【００１４】本半導体装置は表面実装可能な構造を有し
ており、ヒートシンク６ａが上に向き、メタルカバー９
が実装するプリント基板側となる。また、本半導体装置
の外形寸法は、一辺１５０mm程度まで大型化することが
でき、外形寸法精度も±0.１mmを満足できる。The present semiconductor device has a surface mountable structure, the heat sink 6a faces upward, and the metal cover 9
Will be the printed circuit board side to be mounted. Further, the external dimensions of the present semiconductor device can be increased to about 150 mm on a side, and the external dimension accuracy can satisfy ± 0.1 mm.
【００１５】裸ＩＣチップ３の発熱は、まず薄い回路部
１２の絶縁膜（Ａｌ2Ｏ3−５μｍ／層）７及び導体膜
（Ａｌ−５μｍ／層）８を通り、ＣｕＷ材料（熱伝導率
約３００ｗ／ｍｋ）から成るメタルパッケージ６とヒー
トシンク６ａが一体となった放熱部に高熱伝導パスで伝
わる。この間の熱抵抗θjcは、0.３℃／ｗ以下となり、
３０Ｗクラスの裸ＩＣチップでさえ、ジャンクション温
度を９℃の温度上昇でおさえることができ、１５０℃の
ジャンクション温度を有するＩＣでは１４０℃の環境温
度（ヒートシンク温度）でも使用することが十分でき
る。The heat generated by the bare IC chip 3 first passes through the insulating film (Al 2 O 3 -5 μm / layer) 7 and the conductor film (Al-5 μm / layer) 8 of the thin circuit portion 12, and the CuW material (thermal conductivity). A metal package 6 made of about 300 w / mk) and a heat sink 6a are transmitted to a heat radiating portion integrated with a high heat conduction path. The thermal resistance θ jc during this period is 0.3 ° C / w or less,
Even a 30W class bare IC chip can suppress the junction temperature by a temperature increase of 9 ° C, and an IC having a junction temperature of 150 ° C can be sufficiently used even at an ambient temperature (heat sink temperature) of 140 ° C.
【００１６】＜第２実施例＞図３，図４に本発明の第２
実施例を説明する。第２実施例は第１実施例とほぼ同じ
構造を有しているが、次の（１）〜（３）の点が第１実
施例と異なる構造となっている。 （１）第２実施例は、プリント基板側（実装面）にヒー
トシンク６ａを有している。 （２）リードピン５は、表面実装タイプでなく、ＤＩＰ
タイプである。 （３）金属パッケージ材料として、低コスト化を図るた
め、コバール材料（Ｆｅ−Ｎｉ合金）を使用している。
なお、Ａｌ材料を用いることもできる。<Second Embodiment> FIGS. 3 and 4 show a second embodiment of the present invention.
An example will be described. The second embodiment has almost the same structure as the first embodiment, but the following points (1) to (3) are different from the first embodiment. (1) In the second embodiment, the heat sink 6a is provided on the printed circuit board side (mounting surface). (2) The lead pin 5 is not a surface mount type, but a DIP
It is a type. (3) As a metal package material, a Kovar material (Fe-Ni alloy) is used for cost reduction.
Note that an Al material can also be used.
【００１７】＜第３実施例＞図５，図６，図７に本発明
の第３実施例を説明する。第３実施例は第１実施例とほ
ぼ同じ構造を有しているが、次の（１）（２）の点が第
１実施例と異なる構造となっている。なお、図６は外形
が円筒のタイプを、図７は外形が角形のタイプを示して
いる。 （１）ヒートシンク６ａを側面に有する。 （２）リードピン５はＤＩＰタイプである。<Third Embodiment> A third embodiment of the present invention will be described with reference to FIGS. 5, 6 and 7. The third embodiment has almost the same structure as the first embodiment, but the following points (1) and (2) are different from the first embodiment. Note that FIG. 6 shows a cylindrical type and FIG. 7 shows a rectangular type. (1) The heat sink 6a is provided on the side surface. (2) The lead pin 5 is a DIP type.
【００１８】＜第４実施例＞図８，図９に本発明の第４
実施例を説明する。第４実施例は第１実施例とほぼ同じ
構造を有しているが、次の（１）（２）の点が第１実施
例と異なる構造となっている。 （１）ヒートシンク６ａとして大型の金属部を有し、高
発熱ＩＣの熱を十分蓄積することができる構造を有して
いる。 （２）複数の半導体装置を１つのヒートシンク６ａと一
体化し、構成している。<Fourth Embodiment> FIGS. 8 and 9 show a fourth embodiment of the present invention.
An example will be described. The fourth embodiment has almost the same structure as the first embodiment, but the following points (1) and (2) are different from the first embodiment. (1) The heat sink 6a has a large metal part and has a structure capable of sufficiently storing the heat of the high heat generating IC. (2) A plurality of semiconductor devices are integrated with one heat sink 6a.
【００１９】[0019]
【発明の効果】以上実施例と共に具体的に説明したよう
に本発明によれば、金属パッケージと回路部及びヒート
シンクを一体にしたため、大型でありながら寸法精度が
高く、しかも周囲環境温度が１４０℃でも使用できる半
導体装置が実現した。According to the present invention as described in detail with reference to the above embodiments, since the metal package, the circuit portion and the heat sink are integrated, the size is high and the dimensional accuracy is high, and the ambient temperature is 140 ° C. But a semiconductor device that can be used has been realized.
【図１】本発明の第１実施例に係る半導体装置を示す断
面図。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】第１実施例を示す斜視図。FIG. 2 is a perspective view showing a first embodiment.
【図３】本発明の第２実施例に係る半導体装置を示す断
面図。FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図４】第２実施例を示す斜視図。FIG. 4 is a perspective view showing a second embodiment.
【図５】本発明の第３実施例に係る半導体装置を示す断
面図。FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図６】外形円筒タイプの第３実施例を示す斜視図。FIG. 6 is a perspective view showing a third embodiment of an external cylindrical type.
【図７】外形角形タイプの第３実施例を示す斜視図。FIG. 7 is a perspective view showing a third embodiment of a rectangular outer shape type.
【図８】本発明の第４実施例に係る半導体装置を示す断
面図。FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
【図９】第４実施例を示す斜視図。FIG. 9 is a perspective view showing a fourth embodiment.
【図１０】従来の半導体装置を示す断面図。FIG. 10 is a sectional view showing a conventional semiconductor device.
【図１１】従来の半導体装置を示す断面図。FIG. 11 is a sectional view showing a conventional semiconductor device.
１ ワイヤ ２ はんだ ３ 裸ＩＣチップ ４ ガラス ５ リードピン ６ 金属パッケージ ６ａ ヒートシンク ７ 絶縁膜 ８ 導体膜 ９ メタルカバー １０ セラミックパッケージ １１ 回路基板 １２ 回路部 １３ ヒートシンク １４ ネジ 1 Wire 2 Solder 3 Bare IC Chip 4 Glass 5 Lead Pin 6 Metal Package 6a Heat Sink 7 Insulating Film 8 Conductor Film 9 Metal Cover 10 Ceramic Package 11 Circuit Board 12 Circuit Section 13 Heat Sink 14 Screw
───────────────────────────────────────────────────── フロントページの続き (72)発明者 柴山 直樹 愛知県小牧市大字東田中1200番地 三菱重 工業株式会社名古屋誘導推進システム製作 所内 (72)発明者 川崎 幸治 愛知県犬山市犬山三本縄手11番地 プラザ イトウビル４階 東航エンジニアリング株 式会社 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Shibayama 1200, Higashi-Tanaka, Komaki City, Aichi Prefecture Mitsubishi Heavy Industries, Ltd.Nagoya guidance propulsion system manufacturing plant (72) Inventor Koji Kawasaki 11 Inuyama Sanbonawa, Inuyama City, Aichi Prefecture Plaza Ito Building 4F Tokai Engineering Co., Ltd.
Claims (5)
を外気から密閉する封止部材を有する金属パッケージと
ヒートシンク及び回路部が一体となっていることを特徴
とする半導体装置。1. A semiconductor device comprising a bare IC chip, a metal package having a sealing member for sealing the bare IC chip from the outside air, a heat sink, and a circuit unit, which are integrated with each other.
及びヒートシンクが、ＣｕＷ材料，Ａｌ材料又はＦｅ−
Ｎｉ合金材料の少なくとも１つよりなることを特徴とす
る半導体装置。2. The metal package and heat sink according to claim 1, wherein the CuW material, the Al material, or the Fe-- material.
A semiconductor device comprising at least one Ni alloy material.
ッケージ内部底面上に直接、真空蒸着法及びエッチング
法により製造されることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the circuit portion is directly manufactured on the inner bottom surface of the metal package by a vacuum deposition method and an etching method.
路であることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein the circuit portion is a multilayer circuit.
の少なくとも一辺の寸法が５０mm以上である大型金属パ
ッケージであることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the metal package is a large-sized metal package having a dimension of at least one side of 50 mm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2652493A JPH06244358A (en) | 1993-02-16 | 1993-02-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2652493A JPH06244358A (en) | 1993-02-16 | 1993-02-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06244358A true JPH06244358A (en) | 1994-09-02 |
Family
ID=12195868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2652493A Pending JPH06244358A (en) | 1993-02-16 | 1993-02-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06244358A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
-
1993
- 1993-02-16 JP JP2652493A patent/JPH06244358A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
| US8179688B2 (en) | 2004-04-14 | 2012-05-15 | Denso Corporation | Semiconductor device |
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