JPH06244190A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH06244190A
JPH06244190A JP5508393A JP5508393A JPH06244190A JP H06244190 A JPH06244190 A JP H06244190A JP 5508393 A JP5508393 A JP 5508393A JP 5508393 A JP5508393 A JP 5508393A JP H06244190 A JPH06244190 A JP H06244190A
Authority
JP
Japan
Prior art keywords
signal
wiring
conductor
amplifier
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5508393A
Other languages
Japanese (ja)
Inventor
Katsu Isobe
克 礒部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP5508393A priority Critical patent/JPH06244190A/en
Publication of JPH06244190A publication Critical patent/JPH06244190A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To cancel a parasitic quantity between signal wiring and a substrate and improve the quantity of the output waveform by extending conductor along the wiring and separately applying a signal, which is almost the same as a signal applied to the wiring, to the conductor. CONSTITUTION:An oxide film 3 is formed on a substrate 2, signal wiring 1 is buried in the oxide film 3 and conductor 4 is buried in the oxide film 3 so as to surround the signal wiring 1. An amplifier 5a for applying an input signal to the signal wiring 1, an amplifier 5b for separately applying the same signal as the signal applied to the signal wiring 1 to the conductor 4 and an amplifier 5c for distributing the signal to the amplifier 5a and 5b are connected to the semiconductor integrated circuit. When a square wave signal is applied to the amplifier 5c, a signal which passes through the conductor is influenced by the parasitic quantity generated between the substrate and the wiring, however, a signal which passes through the wiring gets almost no influence from the parasitic quantity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路に関し、
特に回路の高速化に伴い、伝送される信号の波形が寄生
容量等の外部要因により変化することを防止した回路に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a circuit in which the waveform of a transmitted signal is prevented from changing due to an external factor such as a parasitic capacitance as the circuit speed increases.

【0002】[0002]

【従来の技術】半導体集積回路に於ける高密度化及び回
路動作の高速化に伴い、信号配線と隣接した導体との間
に発生する寄生容量により、出力波形がなまり易くな
る。
2. Description of the Related Art With the increase in density and speed of circuit operation in semiconductor integrated circuits, the output waveform is apt to be blunted by the parasitic capacitance generated between the signal wiring and the adjacent conductor.

【0003】図3は、従来形式の半導体集積回路に於け
る配線の断面図を示すもので、導電性を有する基板2上
に、絶縁層である酸化膜3が形成され、その上に信号配
線1が配設されている。この信号配線1には、図4に示
すようにアンプ6より入力信号が供給される。
FIG. 3 is a cross-sectional view of wiring in a conventional type semiconductor integrated circuit, in which an oxide film 3 as an insulating layer is formed on a conductive substrate 2 and signal wiring is formed thereon. 1 is provided. An input signal is supplied to the signal wiring 1 from an amplifier 6 as shown in FIG.

【0004】この配線1と基板2との間には、容量成分
が寄生するが、この容量の大きさは信号配線1の面積に
比例する。よって、大規模化する集積回路に伴い配線1
が長くなると、この寄生容量が大きくなるため、出力信
号の波形がなまり、信号伝送遅れ等の不具合が生じる。
A capacitance component is parasitic between the wiring 1 and the substrate 2, and the magnitude of this capacitance is proportional to the area of the signal wiring 1. Therefore, as the integrated circuit becomes larger, the wiring 1
As the length becomes longer, the parasitic capacitance becomes larger, so that the waveform of the output signal is blunted, causing a problem such as a signal transmission delay.

【0005】[0005]

【発明が解決しようとする課題】このような従来技術の
問題点に鑑み、本発明の主な目的は、信号配線と基板間
に寄生する容量をキャンセルし、出力波形の品質を向上
させた半導体集積回路を提供することにある。
SUMMARY OF THE INVENTION In view of the problems of the prior art as described above, the main object of the present invention is to cancel the parasitic capacitance between the signal wiring and the substrate and improve the quality of the output waveform. It is to provide an integrated circuit.

【0006】[0006]

【課題を解決するための手段】上述した目的は本発明に
よれば、信号配線を有する半導体集積回路に於て、前記
配線に沿って延設された導電体と、前記配線に印加する
信号と略同一の信号を前記導電体に別個に印加するため
の手段とを有することを特徴とする半導体集積回路を提
供することにより達成される。
According to the present invention, in the semiconductor integrated circuit having a signal wiring, a conductor extending along the wiring and a signal applied to the wiring are provided. And a means for separately applying substantially the same signals to the conductors. This is achieved by providing a semiconductor integrated circuit.

【0007】[0007]

【作用】このようにすれば、配線に沿って延設された導
電体は、配線と常に同電位におかれるため、電荷が蓄積
されることがなく、よって信号配線は導電体からの寄生
容量の影響を受けず、配線を伝送される信号がなまる事
がない。
With this configuration, the conductor extending along the wiring is always kept at the same potential as the wiring, so that no electric charge is accumulated, and therefore the signal wiring has a parasitic capacitance from the conductor. The signal transmitted through the wiring is not dulled without being affected by.

【0008】また、配線と導電体とが互いに別個に信号
の供給を受けることから、浮遊容量は基板と導電体の間
に対してのみ寄生し、導電体を伝送される信号の波形は
なまるが、配線自体を伝送させる信号はなまることがな
い。
Further, since the wiring and the conductor are supplied with signals separately from each other, the stray capacitance is parasitic only between the substrate and the conductor, and the waveform of the signal transmitted through the conductor is rounded. The signal that transmits the wiring itself does not dull.

【0009】[0009]

【実施例】以下、本発明の好適実施例を添付の図面につ
いて詳しく説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

【0010】図1は、本発明に基づく半導体集積回路の
一実施例を示す図で、基板2と、基板の上に形成された
酸化膜3と、その酸化膜3に埋め込まれた信号配線1
と、信号配線1を外囲するように酸化膜3に埋め込まれ
た導電体4とからなる。この半導体集積回路には、図2
に示すように、信号配線1に入力信号を印加するための
アンプ5aと、信号配線1に印加した信号と同一の信号
を独立に導電体4に印加するためのアンプ5bと、アン
プ5a、5bに信号を分配するためのアンプ5cが接続
されている。
FIG. 1 is a diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. A substrate 2, an oxide film 3 formed on the substrate, and a signal wiring 1 embedded in the oxide film 3 are shown.
And a conductor 4 embedded in the oxide film 3 so as to surround the signal wiring 1. This semiconductor integrated circuit is shown in FIG.
As shown in FIG. 5, an amplifier 5a for applying an input signal to the signal wire 1, an amplifier 5b for independently applying the same signal as the signal applied to the signal wire 1 to the conductor 4, and an amplifier 5a, 5b. An amplifier 5c for distributing a signal is connected to.

【0011】このアンプ5cに、例えば図5の(a)部
に示すような方形波信号を印加すると、アンプ5a、5
bにより、同一の信号が独立に配線1と導電体4に入力
される。導電体4を伝送される信号は、基板2との間に
発生する寄生容量の影響を受け、その出力信号は図5の
(b)部に示したような波形になる。しかし、配線1を
伝送される信号は寄生容量の影響を殆ど受けず、その出
力信号は(c)部に示すような波形となり、殆どなまら
ない。
If, for example, a square wave signal as shown in FIG. 5A is applied to the amplifier 5c, the amplifiers 5a, 5
By b, the same signal is independently input to the wiring 1 and the conductor 4. The signal transmitted through the conductor 4 is affected by the parasitic capacitance generated between the conductor 4 and the output signal thereof has a waveform as shown in part (b) of FIG. However, the signal transmitted through the wiring 1 is hardly affected by the parasitic capacitance, and the output signal thereof has a waveform as shown in the part (c), and is hardly rounded.

【0012】これは、信号配線と導電体には同一の信号
が印加されているために、両者の間には、Q=CVの関
係式に於て、電位差Vが常に0に保持されることから、
電荷Qの蓄積がなされず、寄生容量Cの実効値は0とな
り、信号配線が寄生容量の影響を受けないため、アンプ
出力の負荷が軽減されるからである。
This is because the same signal is applied to the signal wiring and the conductor, so that the potential difference V is always maintained at 0 between them in the relational expression of Q = CV. From
This is because the charge Q is not accumulated, the effective value of the parasitic capacitance C becomes 0, and the signal wiring is not affected by the parasitic capacitance, so that the load of the amplifier output is reduced.

【0013】[0013]

【発明の効果】このように、簡単な構造により、配線を
伝送される信号波形のなまりが軽減されることから、高
速動作、高品質波形伝送が可能となる。
As described above, the simple structure reduces the rounding of the signal waveform transmitted through the wiring, which enables high-speed operation and high-quality waveform transmission.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明に基づく半導体集積回路の配線の
断面斜視図である。
FIG. 1 is a cross-sectional perspective view of a wiring of a semiconductor integrated circuit according to the present invention.

【図2】図2は本発明に基づく回路図である。FIG. 2 is a circuit diagram according to the present invention.

【図3】図3は従来の半導体集積回路の配線の断面斜視
図である。
FIG. 3 is a cross-sectional perspective view of wiring of a conventional semiconductor integrated circuit.

【図4】図4は従来の回路図である。FIG. 4 is a conventional circuit diagram.

【図5】図5は波形伝送列を示す図である。FIG. 5 is a diagram showing a waveform transmission train.

【符号の説明】[Explanation of symbols]

1 信号配線 2 基板 3 酸化膜 4 導電体 5a、5b、5c アンプ 6 アンプ 1 signal wiring 2 substrate 3 oxide film 4 conductors 5a, 5b, 5c amplifier 6 amplifier

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/04 D 8427−4M 9355−4M H01L 23/12 Q 9355−4M 23/14 X ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 27/04 D 8427-4M 9355-4M H01L 23/12 Q 9355-4M 23/14 X

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 信号配線を有する半導体集積回路に於
て、 前記配線に沿って延設された導電体と、前記配線に印加
する信号と略同一の信号を前記導電体に別個に印加する
ための手段とを有することを特徴とする半導体集積回
路。
1. In a semiconductor integrated circuit having signal wiring, a conductor extending along the wiring and a signal substantially the same as a signal applied to the wiring are separately applied to the conductor. And a semiconductor integrated circuit.
JP5508393A 1993-02-18 1993-02-18 Semiconductor integrated circuit Withdrawn JPH06244190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5508393A JPH06244190A (en) 1993-02-18 1993-02-18 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5508393A JPH06244190A (en) 1993-02-18 1993-02-18 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH06244190A true JPH06244190A (en) 1994-09-02

Family

ID=12988827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5508393A Withdrawn JPH06244190A (en) 1993-02-18 1993-02-18 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH06244190A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000509