JPH06244116A - Semiconductor manufacturing equipment - Google Patents

Semiconductor manufacturing equipment

Info

Publication number
JPH06244116A
JPH06244116A JP3105093A JP3105093A JPH06244116A JP H06244116 A JPH06244116 A JP H06244116A JP 3105093 A JP3105093 A JP 3105093A JP 3105093 A JP3105093 A JP 3105093A JP H06244116 A JPH06244116 A JP H06244116A
Authority
JP
Japan
Prior art keywords
reaction chamber
semiconductor
semiconductor wafer
boat
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3105093A
Other languages
Japanese (ja)
Inventor
Tsutomu Udo
勉 有働
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP3105093A priority Critical patent/JPH06244116A/en
Publication of JPH06244116A publication Critical patent/JPH06244116A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To uniform the heat treatment temperature for a semiconductor wafer in a reaction chamber, and improve the uniformity of film formation. CONSTITUTION:In the title equipment, a plurality of semiconductor wafers 8 are accommodated in a boat 9, and a thin film is formed on the surface of each semiconductor wafer 8. When the semiconductor wafers 8 are accommodated, according to the formation state of film thickness, in every other grove or every two or more grooves. Thereby generation of temperature difference in a furnace which is caused by close interval accommodation of the semiconductor wafers 8 is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体の製造装置に関す
る技術、特に、CVD装置などにあって反応室内の熱処
理温度の均一化を図るために用いて効果のある技術に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor, and more particularly to a technique which is effective in a CVD apparatus or the like for uniformizing a heat treatment temperature in a reaction chamber.

【0002】[0002]

【従来の技術】酸化シリコン膜、窒化シリコン膜、多結
晶シリコン膜などの薄膜を半導体ウェハの表面に堆積す
る装置としてCVD(Chemical Vapour Deposision:化
学気相成長)装置がある。
2. Description of the Related Art A CVD (Chemical Vapor Deposision) apparatus is known as an apparatus for depositing a thin film such as a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film on the surface of a semiconductor wafer.

【0003】この種の装置は、反応室をヒータで加熱
し、この反応室内にボートと称する治具に厚み方向かつ
同一中心線上にセットした複数枚の半導体ウェハを挿入
し、処理に必要な各種のガスを反応室内に供給してCV
Dを行う構成になっている。CVD装置にあっては、反
応室内に収容された半導体ウェハに対し、如何に均一性
良く成膜するかが重要な課題の一つになっている。
In this type of apparatus, a reaction chamber is heated by a heater, and a plurality of semiconductor wafers set in the thickness direction and on the same center line are inserted into a jig called a boat in the reaction chamber, and various kinds of processing required for processing are performed. CV by supplying the gas of
It is configured to perform D. In a CVD apparatus, one of important issues is how to form a film uniformly on a semiconductor wafer housed in a reaction chamber.

【0004】反応室は、縦型の場合、外周にヒータが配
設されると共に上端が閉塞された円筒状の外管と、この
外筒内に同軸状に配設される内管とを主体に構成されて
いる。このような構造のため、半導体ウェハの搬入・搬
出のための開口部を有する下部が他の部分に比べて温度
が低くなり易い。
In the case of the vertical type, the reaction chamber is mainly composed of a cylindrical outer tube having a heater arranged on the outer periphery and a closed upper end, and an inner tube coaxially arranged in the outer tube. Is configured. Due to such a structure, the temperature of the lower portion having the opening for loading and unloading the semiconductor wafer is likely to be lower than that of other portions.

【0005】この問題を解決するため、例えば、特開平
3−46223号公報では、反応室の軸方向にヒータを
複数のゾーンに区分して配設し、各々を個別に電力制御
(すなわちヒータ発熱量を制御し、反応室の下部の温度
が高くなるようにする)し、反応室に収容された半導体
ウェハへの成膜均一性を向上させる技術が提案されてい
る。また、特開平3−142823号公報に示されるよ
うに、複数の原料ガス導入管及びノズルを設け、成膜の
均一性向上を図る技術が提案されている。
In order to solve this problem, for example, in Japanese Unexamined Patent Publication (Kokai) No. 3-46223, heaters are divided into a plurality of zones in the axial direction of the reaction chamber, and each of them is individually controlled for electric power (that is, heater heat generation). A technique has been proposed in which the amount is controlled so that the temperature in the lower part of the reaction chamber becomes high) to improve the film formation uniformity on the semiconductor wafer housed in the reaction chamber. Further, as disclosed in Japanese Patent Laid-Open No. 3-142823, a technique has been proposed in which a plurality of source gas introduction pipes and nozzles are provided to improve the uniformity of film formation.

【0006】[0006]

【発明が解決しようとする課題】本発明者の検討によれ
ば、ヒータを複数のゾーンに区分して温度制御を行う従
来技術は、ヒータ発熱量の制御には限界があり、半導体
ウェハ内での熱処理温度が違ってくるために特性ばらつ
きの変化は避けられず、また、後者の従来技術にあって
は、複数の原料ガス導入管を施設する必要があるため、
構造が複雑になると共にメンテナンス性が悪いという問
題がある。
According to the study by the present inventor, in the prior art in which the heater is divided into a plurality of zones and the temperature is controlled, there is a limit in controlling the heat value of the heater. Since the heat treatment temperature of 1 changes, the variation of the characteristics cannot be avoided, and in the latter prior art, it is necessary to install a plurality of source gas introduction pipes.
There is a problem that the structure becomes complicated and maintainability is poor.

【0007】そこで、本発明の目的は、反応室内の半導
体ウェハに対する熱処理温度を均一にし、成膜の均一性
を図ることが可能な技術を提供することにある。
Therefore, an object of the present invention is to provide a technique capable of making the heat treatment temperature for the semiconductor wafer in the reaction chamber uniform and achieving the uniformity of film formation.

【0008】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0009】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【0010】すなわち、複数枚の半導体ウェハを治具に
収納して反応室で前記半導体ウェハの各々の表面に薄膜
を形成する半導体製造装置であって、前記治具に収納す
る際の前記半導体ウェハの間隔を膜厚の形成状態に応じ
て任意に設定している。
That is, a semiconductor manufacturing apparatus for accommodating a plurality of semiconductor wafers in a jig to form a thin film on each surface of the semiconductor wafer in a reaction chamber, wherein the semiconductor wafers are accommodated in the jig. Is arbitrarily set according to the film thickness formation state.

【0011】[0011]

【作用】上記した手段によれば、半導体ウェハを一定間
隔にして反応室に入れた場合の温度分布を把握し、この
温度分布に応じて治具に対する半導体ウェハの収納間隔
を可変する。これにより、半導体ウェハの収納位置にか
かわらず熱処理温度に差を生じさせることがなく、半導
体ウェハ表面における膜厚のばらつきを低減し、膜厚を
均一にすることが可能になる。
According to the above-mentioned means, the temperature distribution when the semiconductor wafers are placed in the reaction chamber at regular intervals is grasped, and the storage interval of the semiconductor wafers in the jig is varied according to this temperature distribution. This makes it possible to reduce the variation in the film thickness on the surface of the semiconductor wafer and to make the film thickness uniform without causing a difference in the heat treatment temperature regardless of the storage position of the semiconductor wafer.

【0012】[0012]

【実施例】図1は本発明による半導体製造装置の一実施
例を示す正面断面図である。
1 is a front sectional view showing an embodiment of a semiconductor manufacturing apparatus according to the present invention.

【0013】反応室1は、円筒状で上部が閉塞されると
共に下端が開口された石英ガラス製の外管2と、この外
管2の内壁に近接させて該外管2と同軸に配設された石
英ガラス製の内管3とよりなる縦型の構造である。
The reaction chamber 1 is cylindrical and has an outer tube 2 made of quartz glass, the upper part of which is closed and the lower end of which is open, and an outer wall of the outer tube 2, which is arranged coaxially with the outer tube 2. This is a vertical structure composed of the formed inner tube 3 made of quartz glass.

【0014】外管2の外周部には、外管2を取り巻くよ
うにヒータ4が配設され、不図示の制御装置によって制
御される。外管2と内管3は下端部の受台5によって連
結され、2つの管の間に形成された空隙部の下端には排
気口6が設けられている。また、連結部の下部には、処
理ガスを反応室1内へ供給するためのガス供給管7が取
り付けられている。
A heater 4 is arranged on the outer peripheral portion of the outer tube 2 so as to surround the outer tube 2, and is controlled by a controller (not shown). The outer pipe 2 and the inner pipe 3 are connected by a pedestal 5 at the lower end, and an exhaust port 6 is provided at the lower end of the void formed between the two pipes. Further, a gas supply pipe 7 for supplying the processing gas into the reaction chamber 1 is attached to the lower part of the connecting portion.

【0015】反応室1の下部には、処理対象の半導体ウ
ェハ8を収納する治具としてのボート9が配設され、こ
のボート9は不図示の駆動機構によって昇降駆動される
ボートエレベータ10に取り付けられている。ボート9
は、4本(または3本)の棒状の柱を主体に構成され、
各柱の内側には長さ方向に一定間隔に溝(不図示)が設
けられており、この溝内に半導体ウェハ8の周縁が嵌入
することにより、半導体ウェハ8が保持される。
A boat 9 as a jig for accommodating the semiconductor wafer 8 to be processed is disposed below the reaction chamber 1. The boat 9 is attached to a boat elevator 10 which is driven up and down by a drive mechanism (not shown). Has been. Boat 9
Is composed mainly of four (or three) rod-shaped pillars,
Grooves (not shown) are provided inside the columns at regular intervals in the length direction, and the semiconductor wafer 8 is held by fitting the peripheral edge of the semiconductor wafer 8 into the grooves.

【0016】ボートエレベータ10に隣接させてウェハ
移載機11が設置されている。このウェハ移載機11
は、半導体ウェハ8をボート9へ搬入ならびに搬出する
ためのアーム12を有している。このアーム12は、ウ
ェハ移載機11に取り付けられた駆動部13によって、
自在に水平方向及び鉛直方向への移動が可能なように構
成されている。
A wafer transfer machine 11 is installed adjacent to the boat elevator 10. This wafer transfer machine 11
Has an arm 12 for loading and unloading the semiconductor wafer 8 into and from the boat 9. This arm 12 is driven by the drive unit 13 attached to the wafer transfer machine 11.
It is configured to be freely movable in the horizontal direction and the vertical direction.

【0017】以上の構成において、半導体ウェハ8の表
面に酸化シリコン膜、窒化シリコン膜、多結晶シリコン
膜などの絶縁膜を堆積させる処理を行う場合、ウェハ移
載機11を動作させ、ウェハ収納ボックスから半導体ウ
ェハ8をアーム12によって取り出し、ボート9内へ順
次移送し、所定枚数をボート9に収納する。ボート9へ
の半導体ウェハ8の移送が終了すると、反応室1の下端
部のゲートを開け、ボートエレベータ10を駆動してボ
ート9を反応室1内へ挿入する。
In the above structure, when a process of depositing an insulating film such as a silicon oxide film, a silicon nitride film or a polycrystalline silicon film on the surface of the semiconductor wafer 8 is performed, the wafer transfer machine 11 is operated to operate the wafer storage box. The semiconductor wafers 8 are taken out by the arm 12 and sequentially transferred into the boat 9, and a predetermined number of wafers are stored in the boat 9. When the transfer of the semiconductor wafer 8 to the boat 9 is completed, the gate at the lower end of the reaction chamber 1 is opened, the boat elevator 10 is driven, and the boat 9 is inserted into the reaction chamber 1.

【0018】反応室1はヒータ4によって処理に必要な
温度に加熱されており、ガス供給管7から処理ガスを供
給しながら半導体ウェハ8の表面に酸化シリコン膜、窒
化シリコン膜、多結晶シリコン膜などの絶縁膜を堆積さ
せる。このとき、ガス供給管7から供給された処理ガス
は、反応室1内を上昇し、反応室1の上端に到達したあ
と、外管2と内管3の隙間を通して下降し、排気口6か
ら反応室外へ排出される。
The reaction chamber 1 is heated to a temperature required for processing by the heater 4, and a silicon oxide film, a silicon nitride film, a polycrystalline silicon film are formed on the surface of the semiconductor wafer 8 while supplying a processing gas from the gas supply pipe 7. An insulating film such as is deposited. At this time, the processing gas supplied from the gas supply pipe 7 ascends in the reaction chamber 1, reaches the upper end of the reaction chamber 1, and then descends through the gap between the outer pipe 2 and the inner pipe 3 from the exhaust port 6. It is discharged outside the reaction chamber.

【0019】所望の処理が終了すると、ボートエレベー
タ10の駆動により、ボート9が降下して反応室1から
半導体ウェハ8の全てが引き出され、定位置に降下した
後、アーム12を駆動してボート9から半導体ウェハ8
が順次取り出される。
When the desired processing is completed, the boat elevator 10 is driven to lower the boat 9 so that all of the semiconductor wafers 8 are pulled out from the reaction chamber 1, and after descending to a fixed position, the arm 12 is driven to drive the boat. 9 to semiconductor wafer 8
Are sequentially taken out.

【0020】以上のように構成された半導体製造装置に
あっては、前記したように、ボート9に一定間隔に半導
体ウェハ8を収納して反応室1へ搬入すると、半導体ウ
ェハ8内の成膜厚の均一性が悪くなる。そこで、本発明
では、ウェハ移載機11によって半導体ウェハ8をボー
ト9に移送する際、ボート9上のウェハ収納間隔14を
任意に変えるようにしている。
In the semiconductor manufacturing apparatus configured as described above, when the semiconductor wafers 8 are accommodated in the boat 9 at regular intervals and are carried into the reaction chamber 1 as described above, film formation in the semiconductor wafer 8 is performed. Thickness uniformity is poor. Therefore, in the present invention, when the semiconductor wafer 8 is transferred to the boat 9 by the wafer transfer machine 11, the wafer storage interval 14 on the boat 9 is arbitrarily changed.

【0021】具体的には、ボート9の各支柱に設けられ
た溝に対して1つおき、2つおきというように間隔をお
いて半導体ウェハ8を収納する。ボート9の上部にあっ
ては密の間隔に半導体ウェハ8を収納し、ボート9の下
部側は疎の間隔に収納して反応室1内の温度を均一に保
ち、半導体ウェハ8の各々に均一に炉内温度が及ぶよう
にしている。
Specifically, the semiconductor wafers 8 are housed at intervals such that every other groove is provided in each of the columns of the boat 9 and every two grooves. In the upper part of the boat 9, the semiconductor wafers 8 are housed in a close space, and in the lower part of the boat 9 are housed in a sparse space to keep the temperature in the reaction chamber 1 uniform and to make the semiconductor wafers 8 uniform. The temperature inside the furnace is controlled to reach.

【0022】この結果、図2に示すような好結果が得ら
れた。ここでは、ガス流量、反応速度及び圧力の各々を
一定にして、成膜速度、面内ばらつき、及びバッチ内ば
らつきを比較している。ボート溝は、「溝1」、「溝
2」、・・・「溝42」のように上側から通し番号を付
けている。図中、1倍ピッチは従来構成に該当し、2倍
ピッチが本発明に該当する。
As a result, good results as shown in FIG. 2 were obtained. Here, the film flow rate, the in-plane variation, and the in-batch variation are compared with each other by keeping the gas flow rate, the reaction rate, and the pressure constant. The boat grooves are serially numbered from the upper side like "groove 1", "groove 2", ... "Groove 42". In the figure, the 1 × pitch corresponds to the conventional configuration, and the 2 × pitch corresponds to the present invention.

【0023】図2から明らかなように、本発明によれ
ば、成膜速度、面内ばらつき、バッチ内ばらつきのいず
れもがピッチを広く取ることによって改善され、半導体
ウェハ8によるLSIの製造歩留りを向上させことが可
能になる。そして、従来、ヒータ4に対して各ゾーン毎
に温度制御を行う必要があったのに対し、それが不要に
なる。
As is clear from FIG. 2, according to the present invention, the film forming rate, the in-plane variation, and the in-batch variation are all improved by making the pitch wide, and the manufacturing yield of LSI by the semiconductor wafer 8 is improved. It will be possible to improve. And, conventionally, it was necessary to control the temperature of the heater 4 for each zone, but this is not necessary.

【0024】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

【0025】例えば、上記実施例においては、反応室が
縦型の場合について例示したが、横型についても同様に
本発明を適用可能である。
For example, in the above-mentioned embodiment, the case where the reaction chamber is vertical is illustrated, but the present invention can be similarly applied to the case where the reaction chamber is horizontal.

【0026】[0026]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

【0027】すなわち、複数枚の半導体ウェハを治具に
収納して反応室で前記半導体ウェハの各々の表面に薄膜
を形成する半導体製造装置であって、前記治具に収納す
る際の前記半導体ウェハの間隔を膜厚の形成状態に応じ
て任意にするようにしたので、半導体ウェハの収納位置
にかかわらず熱処理温度に差を生じさせることがなく、
半導体ウェハ表面における膜厚のばらつきを低減し、膜
厚を均一にすることが可能になる。したがって、LSI
などの半導体製品の歩留りを向上させることができるよ
うになる。
That is, a semiconductor manufacturing apparatus for accommodating a plurality of semiconductor wafers in a jig to form a thin film on each surface of the semiconductor wafer in a reaction chamber, wherein the semiconductor wafers are accommodated in the jig. Since the distance between the two is arbitrarily set according to the film thickness formation state, there is no difference in the heat treatment temperature regardless of the storage position of the semiconductor wafer,
It is possible to reduce variations in film thickness on the surface of the semiconductor wafer and to make the film thickness uniform. Therefore, LSI
It will be possible to improve the yield of semiconductor products such as.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体製造装置の一実施例を示す
正面断面図である。
FIG. 1 is a front sectional view showing an embodiment of a semiconductor manufacturing apparatus according to the present invention.

【図2】本発明と従来とにおける酸化シリコン膜の成膜
速度及び膜厚ばらつきのウェハ間隔依存性の実測結果を
示す説明図である。
FIG. 2 is an explanatory diagram showing actual measurement results of wafer spacing dependency of film formation rate and film thickness variation of the present invention and the related art.

【符号の説明】[Explanation of symbols]

1 反応室 2 外管 3 内管 4 ヒータ 5 受台 6 排気口 7 ガス供給管 8 半導体ウェハ 9 ボート 10 ボートエレベータ 11 ウェハ移載機 12 アーム 13 駆動部 14 ウェハ収納間隔 1 Reaction Chamber 2 Outer Tube 3 Inner Tube 4 Heater 5 Cradle 6 Exhaust Port 7 Gas Supply Pipe 8 Semiconductor Wafer 9 Boat 10 Boat Elevator 11 Wafer Transfer Machine 12 Arm 13 Drive Unit 14 Wafer Storage Interval

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数枚の半導体ウェハを治具に収納して
反応室で前記半導体ウェハの各々の表面に薄膜を形成す
る半導体製造装置であって、前記治具に収納する際の前
記半導体ウェハの間隔を膜厚の形成状態に応じて任意に
することを特徴とする半導体製造装置。
1. A semiconductor manufacturing apparatus for accommodating a plurality of semiconductor wafers in a jig to form a thin film on each surface of the semiconductor wafer in a reaction chamber, wherein the semiconductor wafer is accommodated in the jig. The semiconductor manufacturing apparatus is characterized in that the interval between the two is arbitrarily set according to the formation state of the film thickness.
【請求項2】 前記半導体ウェハの前記収納間隔は、前
記治具の長さ方向に一定間隔に設けられたウェハ収納溝
に対し、空きを設けるものであることを特徴とする請求
項1記載の半導体製造装置。
2. The storage space of the semiconductor wafer is such that a space is provided in a wafer storage groove provided at a constant interval in the length direction of the jig. Semiconductor manufacturing equipment.
【請求項3】 前記反応室を加熱するヒータが複数のゾ
ーンからなる場合、各々のゾーンの消費電力を同一にす
ることを特徴とする請求項1記載の半導体製造装置。
3. The semiconductor manufacturing apparatus according to claim 1, wherein when the heater for heating the reaction chamber comprises a plurality of zones, the power consumption of each zone is the same.
JP3105093A 1993-02-22 1993-02-22 Semiconductor manufacturing equipment Withdrawn JPH06244116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3105093A JPH06244116A (en) 1993-02-22 1993-02-22 Semiconductor manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3105093A JPH06244116A (en) 1993-02-22 1993-02-22 Semiconductor manufacturing equipment

Publications (1)

Publication Number Publication Date
JPH06244116A true JPH06244116A (en) 1994-09-02

Family

ID=12320663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3105093A Withdrawn JPH06244116A (en) 1993-02-22 1993-02-22 Semiconductor manufacturing equipment

Country Status (1)

Country Link
JP (1) JPH06244116A (en)

Similar Documents

Publication Publication Date Title
JP4174837B2 (en) Vertical heat treatment furnace
US5015330A (en) Film forming method and film forming device
KR100870807B1 (en) Substrate processing apparatus and method for manufacturing semiconductor device
US20030049372A1 (en) High rate deposition at low pressures in a small batch reactor
JP2662722B2 (en) Batch type heat treatment equipment
JPH06302523A (en) Vertical thermal treatment equipment
JP2009135551A (en) Method of manufacturing semiconductor device
CN106997859A (en) The manufacture method of lining processor and semiconductor devices
EP0823491B1 (en) Gas injection system for CVD reactors
JPH0794419A (en) Semiconductor treating device
US8303712B2 (en) Substrate processing apparatus, method for manufacturing semiconductor device, and process tube
CN104810306A (en) Vertical heat treatment apparatus, heat treatment method
JP7212790B2 (en) SUBSTRATE PROCESSING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, PROGRAM AND RECORDING MEDIUM
JPH06244116A (en) Semiconductor manufacturing equipment
JP3904497B2 (en) Manufacturing method of semiconductor device
KR100239405B1 (en) Semiconductor fabricating system
JP4218360B2 (en) Heat treatment apparatus and heat treatment method
KR101628786B1 (en) Apparatus and method for processing substrate
JP2006186015A (en) Substrate processor
JPH02226721A (en) Treating apparatus and treating method
KR100350612B1 (en) Dual Vertical Heat Treatment Furnace
JP2000077346A (en) Heat treatment apparatus
JPS60165379A (en) Method and apparatus for continuous-type vapor growth
JP2004335825A (en) Substrate processing device
KR101570227B1 (en) Apparatus and method for processing substrate

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000509