JPH06242749A - Liquid crystal driving device - Google Patents

Abstract

PURPOSE:To provide the liquid crystal driving device which drives TFT liquid crystal stably at a high speed. CONSTITUTION:Transistors TR11-TR1 of driving control circuits Dr1-Drm supply display data of an analog data line 4 to capacitors C11-C1m when inputting select signals SS1, SS2...SSm from a shift register 3 and transistors TR31-TR3m initialize capacitances C21-C2m charged on data lines DL1-DLm and initializes pixel capacitances G11-G1m..., Gn1-Gnm through switching transistors ST11-STn1... ST1m-STnm which ore turned on at that time, if a clear signal CS is inputted from a clear signal line 7. Transistors Tr21-Tr2m, if a latch signal RS is inputted from a latch signal line 6, supply display data of capacitances C11-C1m to the pixel capacitances G11-Gn1..., G1m-Gnm through data lines DL1-DLm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device,
For details, refer to thin film transistor (hereinafter, TFT: thin fil)
m matrix) active matrix type liquid crystal display device (LCD: liquid crystal display)
Said) in the liquid crystal driving device.

[0002]

2. Description of the Related Art Recently, for example, in an information processing device represented by a word processor, a personal computer, etc., the display device has been improved in size and weight as the performance and function have been improved. Especially, lightweight and thin ones are desired.

Therefore, an ordinary cathode ray tube (CRT: cath) is used.
Compared with a display device using an ode ray tube, it is extremely thin and consumes less power, so many LCDs have been developed to become the mainstream of future display devices.

LCDs currently provided in many markets
Are roughly classified into TN (Twisted Nemat-ic) and STN (Su
simple matrix LCD by per Twisted Nematic
And TFT (Thin Film Transistor) and MIM (Metal
Insulator Metal) active matrix LC
Generally, two types of LCDs, D and D, are used. The active matrix type LCD can control fine halftones, can secure a high contrast ratio, and has a high response speed as compared with the simple matrix type LCD. Therefore, it is widely used in the field where high-quality and multi-gradation color display is required. In particular, an active matrix type LCD using a TFT which is a three-terminal element has been particularly noted because it can obtain a high image quality comparable to that of a CRT.

A liquid crystal driving device including such a TFT active matrix type liquid crystal display panel has conventionally been composed of a liquid crystal display panel, a scanning side driving circuit and a data side driving circuit. TFTs which are switching elements and pixel capacitors (liquid crystals) are formed in a matrix between the electrode layers. That is, the liquid crystal display panel includes a TFT and a pixel capacitance for each pixel,
It is driven line by line during the scanning period of one frame.

The scanning side drive circuit usually comprises a shift register and a plurality of buffer amplifiers, scans the scanning signal lines of the liquid crystal display panel, and scans the scanning signal lines selected by the scanning of the TFTs in the liquid crystal display panel. A gate drive signal is output to the gate to control the on / off operation of the TFT.

The data side drive circuit outputs the display data to the pixel capacitance through an arbitrary TFT selected by the scanning side drive circuit so as to write to each pixel of the liquid crystal display panel.

In a liquid crystal display device using a TFT, conventionally, a shift register is generally used as a data side driving circuit, and pixel capacitances selected by the scanning side driving circuit are sequentially applied based on a transfer clock. The driving is performed by a dot-sequential method in which display data is supplied at predetermined time intervals.

That is, a scan line to be displayed is selected by the scan side drive circuit, and display data is sequentially supplied from the data side drive circuit to each pixel of the selected scan line in synchronization with the transfer clock to be selected. Each pixel on the scan line is sequentially displayed.

[0010]

However, in such a conventional liquid crystal driving device, the data side driving circuit is selected based on the transfer clock which is sequentially input for each data line at predetermined time intervals. Since the dot-sequential method that outputs the display data to each pixel capacity on the scanning line is adopted, a time difference occurs in the output of the display data to each pixel by the interval of this transfer clock, and the pixel from the first data line to the final There is a delay before the display data is written to the pixels of the data line. As a result, depending on the timing of the scanning period, there is a problem that display data is duplicated and the display becomes unstable. Then, this problem becomes more prominent as the number of pixels increases.

Therefore, an object of the present invention is to provide a liquid crystal drive device capable of performing stable display at high speed with respect to a liquid crystal display device using a TFT.

[0012]

According to the present invention, among the switching transistors and pixel capacitors formed in a matrix in the column direction and the row direction on a substrate, data is stored in each pixel capacitor located on a selected scanning line. In a liquid crystal drive device that sequentially outputs display data at predetermined time intervals via lines, a data holding unit that is provided for each data line and that holds display data sequentially output at predetermined time intervals, and the data line First switch means provided for each of the data lines to connect a common potential to clear charges on the data lines, and display data held by the data holding means to the pixel capacitors via the data lines. Second switch means for outputting all at once, and after the charge on each data line is cleared by the first switch means, By outputting the display data simultaneously to each pixel capacitance on the scan line from said data holding means by a switch means, to achieve the above objects.

[0013]

According to the present invention, the display data sequentially supplied at predetermined time intervals is temporarily held in the data holding means, the charges on each data line are cleared, and then the display data held in the data holding means is changed to the data. Since it is simultaneously output to each pixel capacity via the line, it is possible to supply the display data all at once without causing a delay in each pixel capacity on the scanning line, and at the time of outputting the display data,
The effect of previous display data can be eliminated. As a result, stable display can be performed even when driven at high speed.

Further, the display data output from the data holding means is connected to the common potential via the first switch means and the second switch means for clearing the charges on the data lines. Since the pixel capacities are supplied all at once, accurate display corresponding to the display can be performed.

[0015]

EXAMPLES The present invention will be described below based on examples.

1 and 2 are views showing an embodiment of a liquid crystal drive device according to the present invention.

FIG. 1 shows a liquid crystal drive device 1 according to this embodiment.
FIG. 3 is a configuration diagram of the above, and particularly shows a data side drive circuit portion of the liquid crystal display panel 2 using a TFT.

In FIG. 1, the liquid crystal drive device 1 includes a shift register 3 and a plurality of drive control circuits Dr1 to Drm.

The liquid crystal display panel 2 includes a plurality of switching transistors ST11 to STnm and pixel capacitors G11 to G.
nm are formed in a matrix shape in the row direction and the column direction, and the pixel capacitances G11 to Gn1, ..., G in each column direction.
1m to Gnm is a switch transistor ST1
1 to STn1, ..., ST1m to STnm, and are connected to the data lines DL1 to DLm. In addition, switching transistors ST11 to ST1m in each row direction,
, STn1 to STnm are connected to the gate lines GL1 to GLn, respectively, and the gate lines GL1
When a gate signal is supplied to ˜GLn, it turns on.

The drive control circuits Dr1 to Drm include transistors Tr11 to Tr1m, Tr21 to Tr2m, Tr.
31 to Tr3m and capacitors C11 to C1m and C21
To C2m, and each of the transistors Tr11 to Tr
1m, ... Tr31 to Tr3m are n-channel MOS
A type FET (Field Effect Transistor) is used.

Each of the transistors Tr11 to Tr1m has its gate electrode connected to each output terminal of the shift register 3, and its source electrode connected to the analog data line 4. The drain electrodes of the transistors Tr11 to Tr1m are connected to one ends of the capacitors C11 to C1m, respectively, and the other ends of the capacitors C11 to C1m are connected to the common line 5. The common line 5 is connected to a common voltage power source (not shown) and is always maintained at the common potential. Therefore, each of the transistors Tr11 to Tr1m receives the selection signals SS1, SS2 ... SSm from the shift register 3,
When turned on, the display data (analog data) supplied to the analog data line 4 at that time is transferred to the capacitor C1.
1 to C1m, and the capacitors C11 to C1m store the supplied display data as electric charges.

Further, one ends of the capacitors C11 to C1m are
Transistors (second switch means) Tr21 to Tr2m
Connected to the source electrode of the transistor Tr21
The drain electrodes of Tr2m are the data lines DL1.
To DLm. The data lines DL1 to DL1
Capacitors C21 to C2 are provided between the DLm and the common line 5.
m is shown, but this is for each data line DL1 ...
This shows the capacity accumulated in DLm, and will be described in detail in the operation description below. Then, the transistors Tr21 to Tr21
The gate electrode of Tr2m is connected to the latch signal line 6, and the latch signal RS is supplied to the latch signal line 6 from a latch signal output circuit (not shown). Therefore, the transistors Tr21 to Tr2m receive the latch signal R
When S is input, it turns on and capacitors C11 to C1
The display data stored as electric charges in m are supplied to the data lines DL1 to DLm, are stored as the capacitors C21 to C2m, and are also stored in the data lines DL1 to DLm.
switching transistors ST11 to S connected to m
, ST1m to STnm are supplied to the pixel capacitors G11 to Gn1, ..., G1m to Gnm.
However, each pixel capacitance G11 to Gn1, ..., G1m
To Gnm are switching transistors ST1
1 to STn1, ..., ST1m to STnm, the switching transistors ST11 to STn1, ..., S are connected to the data lines DL1 to DLm.
Only when T1m to STnm is on, that is,
Only when selected by the scanning side drive circuit (not shown), the capacitor C is connected via the data lines DL1 to DLm.
Display data supplied from 11 to C1m is input.

Further, the data lines DL1 to DLm include
Transistors (first switch means) Tr31 to Tr3m
The source electrode of is connected to the transistor Tr31.
The drain electrodes of to Tr3m are connected to the common line 5. Then, the transistors Tr31 to T
The gate electrode of r3m is connected to the clear signal line 7, and the clear signal CS is supplied to the clear signal line 7 from a clear signal output circuit (not shown). Therefore,
When the clear signal CS is input, the transistors Tr31 to Tr3m turn on and the data lines DL1 to DLm.
Are connected to the common line 5, and the data lines DL1 to DL
The charges of the capacitors C21 to C2m stored in m are initialized and the switching transistors ST11 to STn1, ..., ST1m to ST turned on at this time are initialized.
, and pixel capacitances G11 to G1m, ..., Gn1
Initialize the charge of ~ Gnm.

Next, the operation of the liquid crystal driving device 1 shown in FIG. 1 will be described with reference to FIG.

FIG. 2 is a timing chart of the selection signals SS1, SS2 ... SSm, the clear signal CS and the latch signal RS which are input to the drive control circuits Dr1 to Drm.

The liquid crystal drive device 1 shown in FIG. 1, particularly the drive control circuits Dr1 to Drm, includes drive control circuits Dr1 to Drm.
The display data is stored in the capacitors C11 to C1m of m, the initialization processing of the data lines DL1 to DLm, and the display data supply processing are sequentially performed, thereby driving one scanning line and sequentially performing the driving processing. By executing the scan line, the liquid crystal display panel 1
Drive the screen.

The above processes will be sequentially described below.

<Display Data Storing Process> In the liquid crystal drive device 1, as shown in FIG. 2, the selection signal SS1 is supplied from the shift register 3 to the transistors Tr11 to Tr1m of the drive control circuits Dr1 to Drm at predetermined time intervals. SS
2 ... SSm is output and the transistors Tr11 to T
r1m is turned on when the selection signals SS1, SS2 ... SSm are input, and at that time, the analog data line 4
Display data supplied to the capacitors C11 to C1
Sequentially store in m. That is, when the transistor Tr11 is on, the display data supplied to the analog data line 4 at that time is supplied to the capacitor C11, and when the transistor Tr12 is on, it is supplied to the analog data line 4 at that time. The display data indicating that it is supplied to the capacitor C12. As shown in FIG. 2, this operation is performed by the drive control circuits Dr1 to Drm.
For the drive control circuits Dr1 to Dr on the last column.
Up to m, the transistors Tr11 to Tr1m are sequentially turned on, and the display data supplied to the analog data line 4 at that time are stored in the capacitors C11 to C1m.

<Data Lines DL1 to DLm Initialization Processing> Each drive control circuit Dr is processed by the above display data storage processing.
When the display data is stored in the capacitors C11 to C1m of 1 to Drm, next, as shown in FIG. 2, the clear signal CS is transmitted from the clear signal line 7 to the transistors Tr31 to Tr.
3m to turn on the transistors Tr31 to Tr3m all at once. When the clear signal CS is input, the transistors Tr31 to Tr3m are turned on to connect the data lines DL1 to DLm to the common line 5, and via the data lines DL1 to DLm, the transistors ST31 to Tr3m are turned on at that time. , ST1m to STnm, and pixel capacitances G11 to G1m, ..., Gn1 to Gnm.
Are connected to the common line 5.

Therefore, as shown in FIG. 2, the shift register 3 sequentially outputs the selection signals SS1, SS2 ... SSm to the drive control circuits Dr1 to Drm, and the capacitors C11 to Crm of the drive control circuits Dr1 to Drm. When the storage of the display data in C1m is completed, the clear signal CS is sent through the clear signal line 7 to each of the transistors Tr31 to Tr31.
By outputting to Tr3m and connecting the data lines DL1 to DLm to the common line 5, the data line DL1
To DLm and the pixel capacitances G11 to G1m on the scan line, ...
Gnm can be initialized to the common potential.

<Display data supply processing> Data line DL
When the 1 to DLm initialization process is completed, as shown in FIG. 2, after turning off the transistors Tr31 to Tr3m, the latch signal RS is output to the latch signal line 6 to turn on the transistors Tr21 to Tr2m all at once. When the transistors Tr21 to Tr2m are turned on, the display data accumulated as electric charges in the capacitors C11 to C1m are transferred to the data lines DL1 to DLm and the switching transistors ST11 to STn1, ...
.., Gn1 to G1m, ..., Gn1 to G1m on the scanning line all at once via ST1m to STnm
nm, and each pixel capacitance G11 to G11
, Gn1 to Gnm are driven.

As described above, according to the liquid crystal driving device 1, the T
At the time of driving the liquid crystal display panel 2 using the FT, the display data supplied by the dot-sequential method is temporarily changed to each drive control circuit D.
After accumulating in the capacitors C11 to C1m of r1 to Drm and clearing the pixel capacitances G11 to G1m, ..., Gn1 to Gnm on the data lines DL1 to DLm and the scanning lines, the transistors Tr21 to Tr2m are turned on all at once. Then, the display data accumulated in the capacitors C11 to C1m are converted into pixel capacitances G11 to G1m on the scanning line ,.
.., Gn1 to Gnm can be supplied all at once, so that display data is duplicated and the pixel capacities G11 to G1 are overlapped.
, Gn1 to Gnm can be prevented and stable driving can be performed at high speed.

At this time, the data lines DL1 to DL
The capacitors C21 to C2m stored in m are initialized by supplying the clear signal CS to the respective transistors Tr31 to Tr3m and then resetting the latch signal RS to the respective transistors Tr21.
.. to Tr2m and supplies it to the pixel capacitance on a predetermined scanning line, accurate display corresponding to display data can be performed.

[0034]

According to the present invention, the display data sequentially supplied at predetermined time intervals are temporarily held in the data holding means,
After clearing the charges on each data line, the display data held in the data holding means is simultaneously output to each pixel capacitance via the data line, so that each pixel capacitance on the scanning line is delayed. Instead, the display data can be supplied all at once, and the influence of the previous display data can be removed when the display data is output.
As a result, stable display can be performed even when driven at high speed.

In addition, each of the data lines is connected to a common potential via the first switch means to clear the charge on the data line, and the display output from the data holding means via the second switch means. Since the data is supplied to the respective pixel capacities all at once, accurate display corresponding to the display data can be performed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a liquid crystal drive device of the present invention.

FIG. 2 is a timing chart showing drive waveforms of the data side drive circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Liquid crystal drive device 2 Liquid crystal display panel 3 Shift register 4 Analog data line 5 Common line 6 Latch signal line 7 Clear signal line Dr1-Drm Drive control circuit Tr11-Tr1m, Tr21-Tr2m, Tr31-
Tr3m Transistors C11 to C1m, C21 to C2m Each data line DL
1 to DLm capacitances DL1 to DLm data lines G11 to G1m, ..., Gn1 to Gnm pixel capacitances ST11 to STn1, ..., ST1m to STnm switching transistors GL1 to GLn gate lines SS1 to SSm selection signals CS Clear signal RS latch signal

Claims (1)

[Claims] 1. A switching transistor and a pixel capacitor formed in a matrix on a substrate in a column direction and a row direction, and each pixel capacitor located on a selected scan line is sequentially provided with a predetermined time interval via a data line. In a liquid crystal drive device that outputs display data for each, data holding means that is provided for each of the data lines and that holds display data that is sequentially output at predetermined time intervals, and data lines that are provided for each of the data lines are provided. First connected to a common potential to clear the charge on the data line
Switch means and second switch means for simultaneously outputting the display data held by the data holding means to the respective pixel capacitors via the data lines, wherein the first switch means charges the charge on each data line. After clearing, the display data is simultaneously output from the data holding means to the pixel capacitors on the scanning line by the second switch means.