JPH06237170A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain the small sized synthesizer in which switching between channels of an oscillated frequency is quickened and a change in a spurious characteristic or the like is small between channels by setting a control voltage of a low channel of a voltage controlled oscillator at its low modulation sensitivity and setting the control voltage of a high channel of the voltage controlled oscillator at its high modulation sensitivity. CONSTITUTION:The PLL frequency synthesizer for 1GHz band is made up of a phase locked loop by means of a voltage controlled oscillator 1, a loop filter 2, a frequency division ratio setting circuit 3, a variable frequency divider 4, a phase comparator 5, and a charge pump 6. The frequency division ratio setting circuit 3, the variable frequency divider 4, the phase comparator 5, and the charge pump 6 are integrated in one chip to use as an IC7. The loop gain is increased by using a PNP transistor(TR) with a low DC amplification factor of the charge pump 6 by setting a control voltage for a low channel and a high channel of the voltage controlled oscillator 1 at its low and high modulation sensitivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer used for a local oscillator of a TDMA digital transmission device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a general PLL frequency synthesizer, and FIG. 4 shows an example of channel setting of an oscillation frequency with respect to modulation sensitivity of a voltage controlled oscillator.

In FIG. 3, 1 is a voltage controlled oscillator, 2 is a loop filter consisting of resistors R ₁ and R ₂ and capacitor C, 3 is a frequency division ratio setting circuit, 4 is a variable frequency divider, 5 is a phase comparator, Reference numeral 6 is a charge pump including a PNP transistor 8 and an NPN transistor 9.

The operation will be described below.

The oscillation frequency S ₁ of the voltage controlled oscillator 1 is divided by the variable frequency divider 4, and the divided signal S ₂ is phase-compared with the reference signal S ₃ by the phase comparator 5. The error signal S ₄ output from the charge pump 6 is integrated by the loop filter 2 and then fed back to the voltage controlled oscillator 1 as a control signal S ₅ .

Namely, when the oscillation frequency S ₁ of the voltage controlled oscillator 1 is lower than the reference signal S ₃ is output pin 1 is low level of the phase comparator 5, the output terminal 2 becomes a low level, NPN transistor 9 off , The PNP transistor 8 is turned on, the capacitor C of the loop filter 2 is charged, the control voltage of the control signal S ₅ rises, and the oscillation frequency S ₁ of the voltage controlled oscillator 1 rises.

On the other hand, the oscillation frequency S ₁ of the voltage controlled oscillator ₁
Is higher than the reference signal S ₃ , the output terminal 1 of the phase comparator 5 is at high level and the output terminal 2 is also at high level,
The NPN transistor 9 is turned on, the PNP transistor 8 is turned off, the capacitor C of the loop filter 2 is discharged,
The control voltage of the control signal S ₅ drops, and the oscillation frequency S ₁ of the voltage controlled oscillator 1 drops.

The channel switching of the oscillation frequency S ₁ is performed by switching the frequency division ratio of the variable frequency divider 4 in the frequency division ratio setting circuit 3.

As shown in FIG. 4, a low channel LC, a center channel SC,
The control voltage of the high channel HC is set.

[0010]

However, in the above-mentioned conventional configuration, the DC amplification factor of the PNP transistor 8 cannot be made higher than that of the NPN transistor 9 of the charge pump, so that the charging time of the capacitor C is slower than the discharging time. Become. Therefore, the phase comparison gain is high in the low channel and low in the high channel, so that the loop gain is high in the low channel and low in the high channel.

Therefore, although the switching time of the oscillation frequency from the high channel to the low channel is fast, the switching time from the low channel to the high channel is slow, so that the local oscillator of the TDMA transmission apparatus which requires high-speed frequency switching is used. I can not use it.

Further, there is a problem that the characteristics such as spurious are greatly different between the low channel and the high channel.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a PLL frequency synthesizer in which the switching time from the low channel to the high channel is fast and the characteristics such as spurious are not changed depending on the channel.

[0014]

SUMMARY OF THE INVENTION To solve this problem, the present invention provides a low-channel control voltage of a voltage-controlled oscillator to a low modulation sensitivity portion of a voltage-controlled oscillator and a high-channel control voltage of a modulation sensitivity to a low modulation sensitivity portion. It is characterized in that it is set in each high part.

[0015]

According to the present invention, the low-channel and high-channel control voltages of the voltage controlled oscillator are set to the low and high modulation sensitivities, respectively, so that the PNP transistor having the low DC amplification factor of the charge pump can be used. Since the loop gain can be increased, the switching time of the oscillation frequency from the low channel to the high channel can be made as fast as the switching time from the high channel to the low channel,
Furthermore, characteristics such as spurious do not change depending on the channel.

Further, when a charge divider using a variable frequency divider, a phase comparator, a PNP transistor and an NPN transistor is integrated, it is difficult to make the DC amplification factor of the PNP transistor the same as that of the NPN transistor.
In particular, when high speed is required, the charge pump is composed of an external discrete transistor, which makes it difficult to reduce the size. However, since the loop gain can be increased even if the DC amplification factor of the PNP transistor is low,
The variable frequency divider, phase comparator, and charge pump can be integrated on one chip.

[0017]

1 is a block diagram showing a configuration of a frequency synthesizer according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of channel setting of an oscillation frequency with respect to modulation sensitivity of a voltage controlled oscillator according to the present embodiment. In FIG. 1, the same reference numerals as those in FIG. 3 indicate the same parts or the same elements, and the description thereof will be omitted.

In this embodiment, a voltage controlled oscillator 1, a loop filter 2, a frequency division ratio setting circuit 3, a variable frequency divider 4, a phase comparator 5, and a charge pump 6 constitute a phase locked loop 1G.
It is a PLL frequency synthesizer in the Hz band. The configuration different from that of FIG. 3 of this embodiment uses an IC 7 by integrating the frequency division ratio setting circuit 3, the variable frequency divider 4, the phase comparator 5, and the charge pump 6 in one chip.

Further, it is characterized by the channel setting of the oscillation frequency with respect to the modulation sensitivity of the voltage controlled oscillator shown in FIG.

As shown in FIG. 2, the range of the control voltage (V) of the voltage controlled oscillator 1 is 0 to 3V, and the control voltage is about 1.5V.
The modulation sensitivity changes from 33 MHz / V to 44 MHz / V.

In this embodiment, the control voltage (about 1.5 V) at which the modulation sensitivity changes is the center channel SC, the control voltage of the low channel LC is about 1.0 V, and the high channel HC is the control voltage.
It has the feature that the control voltage of is about 1.8V.

That is, in this embodiment, the loop filter 2 is used so that desired characteristics can be obtained in the center channel SC.
The values of the resistors R ₁ and R ₂ and the capacitor C are determined, and the charge pump 6 can increase the loop gain even by using the PNP transistor 8 having a low DC amplification factor, so that the characteristics do not change even when the channel is switched. It can be a PLL frequency synthesizer.

Although an IC having a built-in charge pump is used in this embodiment, it goes without saying that the same effect can be obtained when the charge pump is externally attached.

[0024]

As described above, in the PLL frequency synthesizer of the present invention, the loop gain can be increased even if the PNP transistor of the charge pump having a low DC amplification factor is used, so that the oscillation frequency is changed from the low channel to the high channel. The switching time can be shortened to the same level as the switching time from the high channel to the low channel, and a PLL frequency synthesizer in which characteristics such as spurious do not change depending on the channel can be obtained.

When high-speed channel switching is required, a variable frequency divider, phase comparator, PNP transistor,
Since a charge pump using an NPN transistor can be used as an integrated IC on one chip, a small PLL frequency synthesizer can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a diagram showing channel setting of an oscillation frequency with respect to modulation sensitivity of the voltage controlled oscillator of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional PLL frequency synthesizer.

FIG. 4 is a diagram showing channel setting of an oscillation frequency with respect to modulation sensitivity of the voltage controlled oscillator of FIG.

[Explanation of symbols]

1 ... Voltage controlled oscillator, 2 ... Loop filter, 3 ... Dividing ratio setting circuit, 4 ... Variable divider, 5 ... Phase comparator,
6 ... Charge pump, 7 ... IC, 8 ... PNP transistor, 9 ... NPN transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 A

Claims (1)

[Claims] 1. A phase-locked loop is constituted by a voltage-controlled oscillator, a loop filter, a variable frequency divider, a phase comparator, and a charge pump using PNP transistors and NPN transistors. A PLL frequency synthesizer, wherein a control voltage is set in a portion having a low modulation sensitivity of the voltage controlled oscillator, and a high channel control voltage is set in a portion having a high modulation sensitivity of the voltage controlled oscillator.