JPH06236347A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To flexibly change the priority levels of plural bus master devices at the time of bus use arbitration according to the state of an object device or the system to be controlled. CONSTITUTION:The plural bus master devices such as a CPU 81, a communication controller 82, and a print controller 83 share a bus and a priority level table to which the operation state of the device to be controlled among those devices or the system is inputted as address information is arranged. In this table, desired priority levels of the individual bus master devices 81-83 for the controlled object are written and arbitration priority level data corresponding to the operation state of the device or system are outputted. An arbitrating circuit performs arbitration properly at all times by using the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration system which arbitrates a bus shared by a plurality of bus master devices when there is a conflict in its use.

[0002]

2. Description of the Related Art Generally, in a computer system, not only a CPU (central processing unit) but also various input / output devices share a bus. In such a system, data transfer to the shared bus may conflict, so a bus arbitration device for arbitrating the data is prepared. The bus arbitration device collectively receives bus use requests individually issued by a plurality of bus arbitration devices including a CPU, an input / output device, and the like, and permits the use of the bus so that they do not overlap in time.

The type of arbitration has a great influence on not only the efficiency of use of the shared bus but also the performance of the entire system. Therefore, various arbitration methods have been proposed in order to adapt to each system. For example, the IEEE (Institute of Electrical and Electronics Engineers) P1014 bus standard has a detailed explanation of bus arbitration methods. here,
Three typical methods will be described.

(1) Single level (daisy chain) method

FIG. 5 shows a single level (daisy chase).
The bus arbitration system configuration using
Of. Multiple bus master devices 11₀, 11₁, ...
…, 11_NArbitration priority for bus usage
They are arranged in a row from the highest to the lowest. this
Other bus master device 11₀, 11₁, ……, 11_NIs
Input terminal I for inputting the bus use permission signal 12_GAnd
Output terminal O_GAnd an input terminal for inputting the bus request signal 13
I_RAnd output terminal O_RIs equipped with. Bus request signal
13 is a low-order output terminal O_RBecause it is one step higher than this
Previous input terminal I _RTo be input respectively
And 0th bus arbitration device 11₀Output terminal O_ROut of
The input bus request signal 13 is an input terminal of the bus arbitration device 14.
Child I_RIt is designed to be input to.

On the other hand, the bus use permission signal 12 output from the output terminal O _G of the bus arbitration device 14 is input to the input terminal I _G of the 0th bus arbitration device 11 ₀ . The bus use permission signal 12 is adapted to be input from the respective output terminals O _G to the input terminal I _G one step lower, except for the N-th bus master device 11 _N.

FIG. 6 shows a circuit configuration between the input and output terminals of the bus master device. Bus master device 11
Includes first and second AND circuits 21 and 22 having one end connected to the input terminal I _G , and an OR circuit 23 having one end connected to the other input terminal I _R. An inverter 24 for inverting the logic is arranged between the other ends of the first and second AND circuits. Also, the first
The output side of the AND circuit 21 is connected to the output terminal O _G , and the output side of the OR circuit 23 is connected to the other output terminal O _R.

In such a bus master device 11, the internal bus request signal 25 is supplied to one input terminal of the OR circuit 23 and the input side terminal of the inverter 24. The other input terminal of the OR circuit 23 is adapted to be supplied with the bus request signal 13 _A from the bus master device at the lower level through the input terminal I _R. Therefore, the bus request signal 13 _B obtained by ORing these is output from the output terminal O _R of the bus master device 11 shown in FIG. As a result, the bus arbitration device 14 shown in FIG. 5 has bus master devices 11 ₀ , 11 ₁ , ...
.., 11 _N requests the use of the bus, the bus request signal 13 indicating the request is supplied.

On the other hand, the second AND circuit 22 in the bus master device 11 takes the logical product of the bus use permission signal 12 input to its own input terminal I _G and the internal bus request signal 25, and if this is true. In other words, if it is at the L (low) level, the internal bus use permission signal 26 is output as a signal that the use of the bus is permitted. At the same time, the internal bus request signal 25 is sent by the inverter 24.
Negative logic was taken and the logical product of the bus grant signal 12 taken at the first AND circuit 21, which by outputting to its own output terminal O _G, the lower bus master device when the self does not use the We are trying to give 11 an opportunity to use the bus.

By such control, the bus arbitration device 14
Will be received by the bus master device 11 having the highest priority, which is outputting the bus request signal 13 at that time. The disadvantage of this method is that the lower-order bus master device 11 cannot obtain the bus use right as long as the bus master device 11 having a higher priority than itself requests the use.

(2) Multi-level priority method

FIG. 7 shows a main part of a bus arbitration system using the multi-level priority method. In this manner, between the bus arbiter 31 and each bus master device 32 _{0-32 3,} a bus request line 33 _{0-33 3} priority are different from one another, the bus grant line also priorities different from each other 34 _{0-34 3} are connected one by one. Between the bus arbiter 31 and bus master 32 _{0-32 3,} one common bus release request line 35 is connected. Bus request line 33 _{0 to} 33 ₃
For, for example, the higher the number added as the subscript, the higher the priority is set.

In the second arbitration system, if a plurality of bus master devices 32 make a bus use request, the arbitration device 31 makes a request through the bus permission line 34 having the highest priority among them. The bus use request is permitted. For example, all bus request lines 33 _{0 to} 33 ₃
If a bus use request is sent to the
The bus use permission is given to the bus permission line 34 ₃ corresponding to the bus master device 32 ₃ of FIG.

The bus release request line 35 is used when a bus master device 32 is using the bus and a bus use request having a higher priority is issued. In this case, the bus release request line 35 is currently used. When the bus master device 32 in use finishes the work currently being processed, the usage right is handed over to the bus master device having a higher priority than this.

In the bus arbitration system using the multi-level priority system, as shown in FIG. 7, one bus request line 33 or one bus permission line 34 is provided.
Each bus master device 32 may be connected, or a plurality of bus master devices 32 may be connected. In this case, a single level (daisy chain) method as shown in FIG. 5, for example, is used together in order to set the priorities in order within the same priority group.

(3) Round robin system

FIG. 8 shows the principle of the round robin system. In this example, the 0th bus master device 41
There are four bus master devices from ₀ to the third bus master device 41 ₃ . In the round robin method, unlike the two methods described above, each bus master device 41
_{0-41 3} to equally adapted to provide the right to use the bus. In this example, it is assumed that all the bus master devices 41 _{0 to} 41 ₃ request the use of the bus, and the 0th bus master device 41
_It is assumed that the bus use right is given to the first bus master device 41 ₁ next to ₀ , the second bus master device 41 ₂ next, and then the third bus master device 41 ₃ next. In this case, the 0th bus master device 41 ₀ circled is shown.
Is using the bus, the first to third bus master devices 41 _{1 to} 41 ₃ will form a queue. After using the bus, the 0th bus master device 41 ₀ has the lowest priority for the next bus request. That is, it will be at the right end of the queue.

In this round robin system, the rank of the bus master device 41 that does not request the use of the bus is incremented every time another bus master device 41 obtains the bus use right. Therefore, when the bus master device 41 having a low frequency of use requests the use of the bus, the bus use right is obtained with a high priority. According to this method, even if the bus is congested, all the bus master devices 41 _{0 to} 41 ₃
Can obtain buses in sequence, and can realize arbitration with equal opportunity.

[0019]

In the first and second methods described above, the priority order for acquiring the bus use right is fixed when the system for bus arbitration is configured. Therefore, this cannot be changed according to changes in various situations during the operation of the system. On the other hand, in the last method, since equal opportunity is guaranteed, it is impossible to increase the priority of only a specific bus master device. However, in an actual system, a specific bus master device may frequently use the bus depending on the operating state.

FIG. 9 shows a system configuration of a page printer controller. Bus 51 with this system
A CPU 52, a memory device 53 for temporary storage, a print control device 55 connected to a printing device 54, a disk control device 57 connected to a magnetic disk device 56, a communication control device 59 connected to a communication cable 58, and an arbitration device 61. Are connected. This figure will be used to explain the situation in which a particular bus master device must frequently use the bus. The processing operation of the page printer shown in FIG.
Can be divided into two.

(1) Print data reception processing: This means that print data is received and processed from a host computer (not shown) via the communication control unit 59. It is necessary to receive the code data from the communication control device 59 that performs high-speed communication so as not to miss it, and store them in the magnetic disk device 56. Therefore, the bus request frequency of the communication control device 59 is highest when the print data receiving process is being performed.

(2) Print data expansion processing: This is the processing for expanding the print code data temporarily stored in the disk device so as to be output to the printing device 54. In this case, convert the print code data to bitmap data,
An output image is formed in the memory device 53. In such a print data expansion process, the CPU 52 has the highest processing load.

(3) Bitmap data output processing: This processing outputs the output image on the memory device 53 to the printing device 54 via the printing control device 55 in synchronization with the printing speed of the printing device 54. The print controller 55 normally performs DMA (direct memory access) transfer, and the bus request of the print controller 55 is the highest in this process.

FIG. 10 shows a state of print processing in page units in this page printer. At time t ₁ after the print suspension period t _R , printing is started on the paper 71 of the first page, and after the printing is completed, an inter-page gap (time) t _G is passed and then the paper 72 of the second page 72 from the time t _2.
The print shall be disclosed in. In the same manner, printing is performed on the third page paper 73, the fourth page paper 74, and the like. The print period of each page is t _P.

As described above, when actually printing with the page printer, the printing period t _P and the inter-page gap t
_G alternates. In the printing period t _P , the bitmap data output process shown in (3) among the processes described above should be prioritized. Also, the inter-page gap t _G
In the section (2), the print data expansion process shown in (2) should be given the highest priority.

However, in the conventional bus arbitration system, the order of bus acquisition is fixed irrespective of such changes in individual circumstances. For this reason, the bus master device that requires high-speed processing has to cope with this by providing an originally unnecessary buffer device and higher processing capability. For example, in Japanese Patent Laid-Open No. 62-26563, the bus request signal is transmitted at a transfer rate suitable for the characteristics of the input / output device. As a result, there has been a problem that the configuration of each bus master device becomes complicated.

Therefore, an object of the present invention is to provide a bus arbitration system capable of flexibly changing the priority of each of a plurality of bus master devices during bus use arbitration according to the status of the device or system to be controlled. Especially.

Another object of the present invention is to easily carry out this when setting or changing the priority order during bus use arbitration of each of a plurality of bus master devices according to the status of the device or system to be controlled. It is to provide a bus arbitration system that can do this.

[0029]

According to a first aspect of the present invention, there is provided a shared bus, a plurality of bus master devices such as a CPU, a print control device, a communication control device, and a disk control device, which share the shared bus, and a shared bus. Arbitration means for granting permission to use the shared bus according to the priority at the time of arbitration when the use requests for these bus master devices conflict with each other, and the operating state for inputting the operating state of the jurisdiction target of these bus master devices. The bus arbitration system is provided with an input unit and an arbitration priority changing unit that changes the arbitration priority of each of the plurality of bus master devices according to the operation state input by the operation state input unit.

That is, in the invention according to claim 1, CP
When a plurality of bus master devices such as U, print control device, communication control device, and disk control device share a bus, the operating state of a device or system under the jurisdiction of these bus master devices is input, and the bus master device is operated accordingly. By changing the priority of the plurality of bus master devices during the arbitration, the priority of the bus master devices during the bus use arbitration can be flexibly changed.

According to a second aspect of the present invention, a shared bus and a plurality of bus master devices such as a CPU, a print control device, a communication control device, and a disk control device, which share the shared bus,
An operating state input means for inputting an operating state of these bus master devices under the jurisdiction, and an arbitration representing the priority at the time of arbitration of each of the plurality of bus master devices using the operating state input by the operating state input means as address information. An arbitration priority setting table that outputs priority data and a bus master device with a higher priority based on the arbitration priority data output from the arbitration priority setting table when the usage requests for the shared bus conflict between the bus master devices. The bus arbitration system is provided with a contention arbitration means for giving permission to use the shared bus in order.

That is, in the second aspect of the invention, the CP
When a plurality of bus master devices such as U, print control device, communication control device, and disk control device share a bus, the arbitration priority order for inputting the operating state of the device or system under the jurisdiction of these bus master devices as address information Prepare a setting table. Then, in this table, the desired priority of each bus master device with respect to the operating state of the device or system to be controlled is written, and arbitration priority data corresponding to the operating state of the device or system is output. . As a result, the contention arbitration unit can always appropriately perform the arbitration when the bus requests for the shared bus compete.

[0033]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows an essential part of a page printer as a bus arbitration system according to an embodiment of the present invention. This page printer uses three types of bus master devices, a CPU 81, a communication control device 82, and a print control device 83, which are each connected to a system bus 84 as a shared bus. The communication control device 82 is connected to a communication cable 85 for communicating with other devices or systems, and the print control device 83 is connected to a printing device 86 such as a laser printer for printing. There is.

There are three types of page printers in this embodiment.
Order of bus master devices 81-83 for bus use arbitration
Set the rank and according to the set priority
An arbitration device 88 that performs arbitration is provided. Arbitration device 88
Are the CPU 81, the communication control device 82, and the printing.
A bus request line 91 is provided between the control device 83 and the control device 83, respectively.₁~ 91
₃And bus permission line 92₁~ 92₃Are connected.

FIG. 2 shows the main part of the circuit configuration of the arbitration device of this embodiment. The arbitration device 88 includes an operation state detection circuit 101 and a bus arbitration unit 102. The operating state detection circuit 101 detects the operating state of the page printer and outputs address information corresponding to the operating state of the page printer to the print period signal 1
03 and the inter-page gap signal 104. The operation state detection circuit 101 is adapted to input a line synchronization signal 105, a page synchronization signal 106 and a print start signal 107, respectively.

The page synchronization signal 106 is a signal output from the printing device 86 at the start of printing in page units in order to synchronize the printing device 86 and the printing control device 83. The line synchronization signal 105 is a signal output from the printing device 86 at the start of printing one line unit. The operating state detection circuit 101 uses the line synchronization signal 105
Are counted by a built-in counter 109, and the print period signal 103 and the inter-page gap signal 104 are created using this value and the page synchronization signal 106 and the like, as described in detail below.

FIG. 3 is a diagram for explaining the logic for the operation state detection circuit to generate the print period signal and the inter-page gap signal. FIG. 10A shows a signal change of the print start signal 107, and the signal level is changed from “0” to “1” at the time t ₁₁ to start printing. The section up to time t ₁₁ is a pause period t _S in which no control over printing is performed as shown in FIG. During the rest period t _S , the printing period signal 10
3 and the inter-page gap signal 104 are both signals "0". In FIG. 6E, this is expressed as (0,0).

[0039] When the print start signal 107 to the time t ₁₁ is changed to "1", rising up printing interval up to time t ₁₂ to change the page sync signal 106 is "1" shown in the coming FIG (b) Is the inter-page gap t _G ′ ((d) in the figure). In FIG. 10, the inter-page gap t _G ′ and the pause period t _S are collectively referred to as a print pause period t _R for the sake of simplicity. In this inter-page gap t _G ′, the print period signal 103 is “0” and the inter-page gap signal 104 is “1”.

When the print start signal 107 changes to "1" at time t ₁₁ , the printing operation is started, and line synchronization is started from the time when the printing operation is started for each line as shown in FIG. The signal 105 is generated. The counter 109 starts counting the line synchronization signal 105 and counts the printing period t _P for one page. During the printing period t _P , the printing period signal 103 is “1” and the inter-page gap signal 10
4 becomes "0".

When the counter 109 detects the end of the printing period t _P for one page at time t ₁₃ , the value is cleared. Then, the time t ₁₄ to the next page synchronization signal 106 from the time t ₁₃ is changed to the signal "1" from the signal "0"
Is the inter-page gap t _G from the end of printing the first page to the start of printing the second page. During the inter-page gap t _G , the print period signal 103 is “0” and the inter-page gap signal 104 is “1”.

As described above, the print period signal 103 and the inter-page gap signal 104, which change depending on the operating state of the page printer, are stored in the priority table 11 of the bus arbitration unit 102.
1 is input as address information.
The priority table 111 stores the contents shown in Table 1 below, and the priority order is set for each of the CPU 81, the communication control device 82, and the print control device 83 shown in FIG. ing.

[0043]

[Table 1]

Here, the priority "1" means the highest state, and the priority "3" means the lowest state.
The priority "2" is an intermediate state between these.
The priority information 112 indicating the priority of each of the CPU 81, the communication control device 82, and the print control device 83 is input to the arbitration circuit 113 in the bus arbitration unit 102, and arbitration is performed. For example, print period signal 1
03 is "1" and the inter-page gap signal 104 is "0".
In the print period of, the print control device 83 has the first priority and the communication control device 82 has the second priority. The CPU 81, which processes jobs other than the jobs assigned to these devices, has the lowest priority, the third priority.

FIG. 4 shows an arbitration procedure in the arbitration circuit. First, the arbitration circuit 113 checks the bus request line (BR) 91 (FIG. 1) of the first priority bus master device output from the priority table 111 (FIG. 2) (step S101). For example, during the printing period described above, the bus request line 91 corresponding to the printing control device 83
₃ is examined. As a result, if there is a bus request on the bus request line 91 (step S102; Y), the bus permission signal (BG) is output to the bus permission line 92 of the bus master device having the first priority (step S103). . In the example described above, the bus grant signal to the bus grant line 92 ₃ is outputted, the print control device 83 will be able to access the system bus 84 as a shared bus.

On the other hand, if there is no bus request on the bus request line 91 of the first priority bus master device (step S102; N), the bus request line 91 of the second priority bus master device is checked. (Step S104). For example, during the printing period described above, the bus request line 91 ₂ corresponding to the communication control device 82 is checked. As a result, if there is a bus request on the bus request line 91 (step S10).
5; Y), the bus permission signal is output to the bus permission line 92 of the bus master device having the second priority (step S1).
06). In the above-described example, the bus permission signal is output to the bus permission line 92 ₂ , and the communication control device 82 can access the system bus 84 as a shared bus.

If no bus request is made for the bus master device having the second priority in step S105 (step S105; N), the bus request line 91 of the bus master device having the third priority is checked (step S107). .
For example, during the printing period described above, the bus request line 91 ₁ corresponding to the CPU 81 is checked. As a result, if there is a bus request on the bus request line 91 (step S108;
Y), a bus permission signal is output to the bus permission line 92 of the bus master device having the third priority (step S10).
9). In the above-described example, the bus permission signal is output to the bus permission line 92 ₁ so that the CPU 81 can access the system bus 84 as the shared bus.

The procedure for mediation by the page printer within the page gap period has been described above. Actually, the priority order information 112 output from the priority order table 111 changes sequentially in the operating state of the page printer. In this way, the arbitration circuit 113 arbitrates the bus master devices 81 to 83 in a priority order according to each situation of the page printer. In this embodiment, as shown in the priority table 111, the communication control device 82 preferentially acquires the system bus 84 in the print pause state section, and the CPU 8 in the inter-page gap section.
1 preferentially acquires the system bus 84. In the printing period, the printing control device 83 preferentially takes the system bus 84.
Will be acquired.

In the above-described embodiments, the page printer has been described as an example, but it goes without saying that the present invention can be generally applied to a plurality of bus master devices connected to the shared bus. Further, in the embodiment, the present invention is applied to a computer system having three bus master devices, but it goes without saying that the number of bus master devices is not limited to this as long as it is plural.

Further, in the embodiment, the operating state of the device or system under the jurisdiction is grasped by using two kinds of signals, that is, the print period signal 103 and the inter-page gap signal 104. It is also possible to grasp the state of and control the priority order.

[0051]

As described above, according to the first and second aspects of the present invention, when a plurality of bus master devices such as a CPU, a print control device, a communication control device and a disk control device share a bus, Enter the operating status of the device or system under the jurisdiction of these bus master devices,
In accordance with this, it is decided to change the priority order of the plurality of bus master devices during arbitration. In this way, the bus master device with a higher priority is made to use the bus preferentially according to each situation, so even in the control in which the relative importance of each bus master device differs depending on the operating state, the individual bus master Efficient and smooth processing can be performed without particularly increasing the processing capacity of the device.

According to the second aspect of the present invention, since the arbitration priority setting table is prepared, the arbitration priority can be obtained only by inputting the operating state of the device or system under the jurisdiction of the bus master device as address information. There is an advantage that the data representing the ranking can be obtained, the processing for this is not burdened, and the processing up to the determination of the priority can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a page printer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a circuit configuration of the arbitration device of the present embodiment.

FIG. 3 is an explanatory diagram showing a logic for the operation state detection circuit of the present embodiment to generate a print period signal and an inter-page gap signal.

FIG. 4 is a flowchart showing an arbitration procedure in the arbitration circuit of the present embodiment.

FIG. 5 is a block diagram showing a configuration of a bus arbitration system using a single level method.

FIG. 6 is a circuit diagram showing a circuit configuration between input / output terminals of a bus master device using a single level method.

FIG. 7 is a block diagram showing a main part of a bus arbitration system using a multilevel priority method.

FIG. 8 is an explanatory diagram showing the principle of the round robin method.

FIG. 9 is a configuration diagram showing a general system configuration of a page printer control device.

FIG. 10 is an explanatory diagram showing a state of print processing in page units in the page printer.

[Explanation of symbols]

81 ... CPU (bus master device), 82 ... Communication control device (bus master device), 83 ... Printing control device (bus master device), 84 ... System bus (shared bus), 86 ... Printing device, 91 _{1 to} 91 ₃ ... Bus request line, 92 _{1-92 3} ...
Bus permission line, 101 ... Operating state detection circuit, 102 ... Bus arbitration unit, 105 ... Line synchronization signal, 106 ... Page synchronization signal, 107 ... Print start signal, 109 ... Counter, 11
1 ... Priority table, 112 ... Priority information, 113
… Arbitration circuit

Claims (2)

[Claims] 1. A shared bus, a plurality of bus master devices that share the shared bus, and when a usage request for the shared bus conflicts between these bus master devices, the shared bus Contention arbitration means for giving permission to use, operation state input means for inputting the operation state of these bus master devices under the jurisdiction, and arbitration priority for each of the plurality of bus master devices according to the operation state input by the operation state input means. A bus arbitration system comprising: arbitration priority changing means for changing the order. 2. A shared bus, a plurality of bus master devices sharing the shared bus, an operating state input means for inputting an operating state of a jurisdiction target of these bus master devices, and an operating state input by the operating state input means. An arbitration priority setting table that outputs arbitration priority data representing the priority of each of the plurality of bus master devices as address information, and arbitration priority when a use request for the shared bus conflicts between the bus master devices. A bus arbitration system comprising: contention arbitration means for granting permission to use the shared bus in order from a bus master device having a higher priority based on arbitration priority data output from the priority setting table.