JPH06231204A - Method for optimizing logic circuit delay time - Google Patents

Abstract

PURPOSE:To perform optimization of a delay time of a logic circuit exactly and in a short time by calculating the delay time by dividing a sequential circuit element into sets from a start point side. CONSTITUTION:A delay calculation set generating procedure 1 divides a sequential circuit element of a logic circuit 9 into several sets by referring to a delay constraint file 8. A separate set delay value setting procedure 2 sets each arrival time and necessary time of a start point side to separate sets by referring to a library 7 and the delay constraint file 8. A separate set delay value calculating procedure 3 calculates an arrival time and a necessary time of each logical element. A random logical tree extracting procedure 4 extracts a random logical tree to be recongsituted. A random logical tree cut end constraint setting procedure 5 sets constraint information of each cut end of an input and an output of the random logical tree. A random logical tree converting procedure 6 converts and reconstitutes the random logical tree.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit delay time optimizing method, and more particularly to a logic circuit delay time optimizing method for optimizing a delay time of a logic circuit including a multi-phase circuit and a multi-cycle path.

[0002]

2. Description of the Related Art There are the following two types of typical conventional logic circuit delay time optimization methods.

First, one set of required time and arrival time (or two sets if the rise / fall of the circuit is taken into consideration) is calculated for each logic element in the logic circuit, and those values are calculated. Based on this, it is a method of optimizing the delay time of the logic circuit. For a reference to this method, see “Timing Opt
imization on Mapped Circuits ”, Proceedings of 28t
h ACM / IEEE Design Automation Conference, 112 ~ 117
Page, 1991, K. Yosikawa etc.

Secondly, for all combinations of the input part of the logic circuit or the output pin of the sequential circuit element and the output part of the logic circuit or the input pin of the sequential circuit element,
This is a method of calculating and optimizing the worst delay time.

As a reference for this method, see Japanese Patent Laid-Open No.
3-280301, delay time optimization method "Tsushio Shimizu, Naohiro Kageyama.

[0006] Further, as other references mentioned above,
"Performance-oriented technology mapping", In Co
nf. on Advanced Research in VLSI, pp. 79-97, 1990
Year and “A heuristic for the fanout problem”, DA
C prcceedings, pp. 357-360, 1990, KJSingh et
c. etc.

[0007]

In the above-mentioned conventional logic circuit delay time optimizing method, the first method calculates a set of delay values for each logic element in the logic circuit.
Correct calculations cannot be performed for multi-phase circuits or multi-cycle circuits that have different delay constraints at the start and end points.
It has a drawback that the delay time cannot be properly optimized.

The second method has a drawback that the calculation time is very long because the delay time of the logic circuit is calculated for all combinations of the input side and the output side. .

[0009]

According to a first aspect of the present invention, there is provided a logic circuit delay time optimizing method, comprising: (A) reading out classification information of sequential circuit elements from a delay constraint file for a logic circuit to be subjected to delay optimization, A delay calculation set creating procedure for dividing the sequential circuit elements included in the logic circuit into some sets;
(B) The delay constraint information in the delay constraint file and the library information of each logic element including the sequential circuit element in the library are read out, and each input section of the logic circuit and each output pin of each sequential circuit element are read out. A set of arrival times corresponding to each set, and set necessary times corresponding to each set for each output pin of the logic circuit and each input pin other than the clock input of each sequential circuit element. Another delay value setting procedure,
(C) Based on the arrival time of each input section of the logic circuit and the output pin of each sequential circuit element set in the delay value setting procedure for each set, the arrival time of each logic element sequentially toward the output side While calculating for each set, based on the required time of each output section of the logic circuit and the input pin of each sequential circuit element set in the delay value setting procedure for each set, sequentially toward the input side. A delay value calculation procedure for each set for calculating the required time of each logic element for each set,
(D) AND, OR, NA existing in the logic circuit
Random logic tree extraction procedure for selecting a random logic tree that is a tree-like circuit to be reconfigured by random logic elements such as ND, NOR, EXOR, EXNOR, and their complex logic, and (E) extraction by the random logic tree extraction procedure For each cut of the input and output of the random logical tree, from the arrival time and the required time calculated for each set in the set-based delay value calculation procedure, by setting the representative value of the arrival time and the required time, A random logical tree cut constraint setting procedure for adding to the random logical tree of the logical circuit as constraint information for input / output of the random logical tree extracted by the random logical tree extraction procedure, and (F) the random logical tree cut constraint Based on the constraint information added in the setting procedure, the random logical tree extracted in the random logical tree extracting procedure is transformed and re-created. Has a random logic tree transformation procedure, a to optimize the delay time due to growth.

In the logic circuit delay time optimizing method of the second invention, (A) the classification information of the sequential circuit elements is read from the delay constraint file for the logic circuit to be the target of the delay optimization, and The sequential circuit elements included in the above are divided into several sets, and (B) the delay constraint information in the delay constraint file and the library information of each logic element including the sequential circuit elements in the library are read out, and For each input section and each output pin of each sequential circuit element, the arrival time corresponding to each set is set, and for each output section of the logic circuit and each input pin other than the clock input of each sequential circuit element. , (C) sets the required time corresponding to each set, and (C) arrives at each input section of the logic circuit and the output pin of each sequential circuit element. Based on the time, the arrival time of each logic element is calculated for each set sequentially toward the output side, and the required time of each output part of the logic circuit and the input pin of each sequential circuit element that has been set is calculated. On the basis of this, the required time of each logic element is calculated for each set sequentially toward the input side, and (D) AND, O existing in the logic circuit is calculated.
A random logic tree that is a tree-like circuit to be reconfigured by random logic elements such as R, NAND, NOR, EXOR, EXNOR and their complex logic is extracted, and (E) each input / output section of the extracted random logic tree For each set, a representative value of the arrival time and the required time is set from the arrival time and the required time calculated for each set, so that the logic circuit is used as constraint information for each cut of the input / output of the extracted random logic tree. To the random logical tree of (F)
It includes converting the extracted random logic tree based on the added constraint information and optimizing the delay time by reconstruction.

On the other hand, the logic circuit delay time optimizing method of the third invention comprises a delay calculation set creating procedure of the first invention and a first embodiment.
In the logic circuit delay time optimizing method having the set-by-set delay value setting procedure of the invention and the set-by-set delay value calculation procedure, (A) existing in a logic circuit to be subjected to delay optimization. And a signal distribution tree extracting procedure for selecting a signal distribution tree that is a tree-like circuit to be reconfigured by signal distribution elements such as a buffer, an inverter, and their complex logic.
From the arrival time and the required time calculated for each set by the set-based delay value calculation procedure for each input / output section of the signal distribution tree extracted by the signal distribution tree extraction procedure, a representative of the arrival time and the required time By setting a value, a signal distribution tree cut constraint setting procedure to be added to the signal distribution tree of the logic circuit as constraint information for input / output cuts of the signal distribution tree extracted in the signal distribution tree extraction procedure, C) A signal distribution tree for optimizing delay time by reconstruction by converting the signal distribution tree extracted in the signal distribution tree extraction procedure based on the constraint information added in the signal distribution tree cut constraint setting procedure. And a conversion procedure.

Further, in the logic circuit delay time optimizing method of the fourth invention, (A) the classification information of the sequential circuit element is read from the delay constraint file for the logic circuit to be the object of delay optimization, and The sequential circuit elements included in the above are divided into several sets, and (B) the delay constraint information in the delay constraint file and the library information of each logic element including the sequential circuit elements in the library are read out, and For each input section and each output pin of each sequential circuit element, the arrival time corresponding to each set is set, and for each output section of the logic circuit and each input pin other than the clock input of each sequential circuit element. ,
A required time corresponding to each set is set, and (C) each logic is sequentially directed toward the output side based on the arrival time of each set input part of the logic circuit and each output pin of each sequential circuit element. The arrival time of the elements is calculated for each set, and based on the required times of the output pins of the logic circuit and the input pins of the sequential circuit elements that have been set, the logical elements of the logic elements are sequentially turned toward the input side. (D) A tree-like circuit to be reconfigured by a signal distribution element such as a buffer, an inverter, and their complex logic, which is present in the logic circuit to be subjected to delay optimization, by calculating the required time for each set. A certain signal distribution tree is extracted, and (E) for each input / output section of the extracted signal distribution tree, a representative value of the arrival time and the necessary time is set from the arrival time and the necessary time calculated for each set. thing Then, the extracted signal distribution tree is added to the signal distribution tree of the logic circuit as constraint information for each input / output section of the extracted signal distribution tree, and (F) the extracted signal distribution tree is converted based on the added constraint information. , Including optimization of the delay time by reconstruction.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a flow chart showing a first embodiment of the logic circuit delay time optimizing method of the present invention. Also, FIG.
FIG. 6 is a diagram showing an example of a logic circuit 9 for optimizing a delay time. 3 is a diagram showing an example of the contents of the delay constraint file 8. Further, FIG. 4 is a diagram showing an example of a set S1, S2, S3, ... In which the sequential circuit elements Z1, Z2, Z3, Z4 ,.

First, as shown in FIG. 1, in the delay calculation set creation procedure 1, the contents of the logic circuit 9 shown in FIG. 2 and the contents of the delay constraint file 8 shown in FIG. 3 are read, and as shown below, Sequential circuit elements Z1, Z2, Z3, Z4, ...
1, S2, S3, ...

In FIG. 3, as constraint information for each phase combination, φi → φj = x (1), the sequential circuit element Z to which the clock φi is input is expressed by (1).
It indicates that the value of the delay constraint between the paths starting from i and ending at the sequential circuit element Zj to which the clock φj is input is x.

Further, the sequential circuit elements Z1, Z2, Z3, Z
Among 4 and, let Ui be the set of the starting points of the multi-period path and Vj be the set of the ending points of the multi-period path. From the elements of the set Ui, Ui → Vj = y (2) It indicates that the value of the delay constraint on the elements of the set Vj is y.

The expressions (1) and (2) are collectively referred to as a delay constraint between the sequential circuit elements Z1, Z2, Z3, Z4 ,. Note that the delay constraint value x,
y is the sequential circuit element Z1, Z2, Z3, Z4 on the starting point side.
It is a value indicating that the time when the reference edge of the clocks φ1, φ2, ...

On the other hand, Ii, φj = yj, φk = yh (3) The clock φ at the input portion Ii of the logic circuit 9 is expressed by
The arrival times yj, yh using j, φk are shown, and the clock φ at the output portion Oi of the logic circuit 9 is expressed by Oi, φj = yj, φk = yh (4)
The required times yj and yh using j and φk are shown.

Therefore, the delay calculation set creation procedure 1 is a set on the starting point side of the formulas (1) and (2), which are delay constraints among the sequential circuit elements Z1, Z2, Z3, Z4 ,. Sequential circuit elements Z1, Z based on the set that inputs the clock φi in equation (1) and the set Ui in equation (2).
2, Z3, Z4, ~ are divided as follows.

First, from the equation (2), the set Ui is used as the set Si. Then, the generated set Si and set Sj
If and have the same element, they are merged into one set Sk. Next, if there is an element a related to the clock φj and an element b related to the clock φk among the elements of the set Si,
The set Si is sequentially divided into a set Sj of elements related to the clock φj and a set Sk other than the above.

If the elements of the set Si and the elements of the set Sj are the same, the same elements are collected and the set S is obtained.
While dividing as k, the elements of the set Sk are removed from each of the sets Si and Sj, and the sets are changed to new sets Si and Sj. At this time, if there are no elements in the set Si or the set Sj, the set is deleted.

The sets S1, S2, to Sh created by performing all the above procedures are the sequential circuit elements Z.
1, Z2, Z3, Z4, ... are divisions for the entire set.

For example, when the delay constraint of FIG. 3 is given to the logic circuit 9 of FIG.
Sequential circuit elements Z1, Z2 and Z3 containing φ2
As shown in FIG. 4, the sequential circuit elements Z1 and Z2, which have Z4 but have the clock φ1, are divided by the delay constraint of FIG. 3 to form {Z1} as a set S1.
And {Z2} as a set S2, and the sequential circuit elements Z3, Z4 containing the clock φ2 are {Z3, Z4} as a set S3.

Next, the delay value setting procedure for each set 2 is the set S1, S2, ... S created by the delay calculation set creation procedure 1.
With respect to the logic circuit 9, delay values corresponding to the number h of h are input to the sequential circuit elements Z1, Z2, Z3, Z4, ...
2 to and output units O1, O2 to.

Such a delay value is [D1, D2, D
3, ~ Dh]. Here, the delay value D
i represents the delay value for the set Si. In the case shown in FIG. 4, as [D1, D2, D3], D1 can be the delay value for the set S1, D2 can be the delay value for the set S2, and D3 can be the delay value for the set S3.

For example, the sequential circuit elements Z1, Z2, Z3
As an example of the output pin of Z4, the sequential circuit element Z1, for the target set S1, S2, S3
For the delay values of Z2 and Z3, the value 0.8 read from the library 7 is entered, and the others are set to NULL to obtain the arrival time. That is, the arrival time of the output pin of the sequential circuit element Z1 [0.8,
NULL, NULL] Arrival time of the output pin of the sequential circuit element Z2 [NUL
L, 0.8, NULL] Arrival time of output pins of sequential circuit elements Z3 and Z4 [NUL
L, NULL, 0.8] Further, to show an example of the input pins of the sequential circuit elements Z1, Z2, Z3, Z4, the target set S1,
S2, S3 are the starting points, and the sequential circuit elements Z1, Z2, Z
3, the delay time when Z4 is the end point is read from the delay constraint file 8 and the sequential circuit elements Z1, Z2 of FIG.
It is searched from the delay constraints between Z3, Z4, ... And set as the required time. That is, the required time of the input pin of the sequential circuit element Z1 [20, 2
0,10] Required time of input pin of sequential circuit element Z2 [40,2
0,10] Required time of the input pin of the sequential circuit device Z3 [30,1
0,20] Required time of input pin of sequential circuit element Z4 [10,1
0, 20] On the other hand, for the input parts I1 and I2 of the logic circuit 9, the sets S1, S2 and S3 given by the equation (3) set their values, and otherwise set NULL as the arrival time.
That is, the arrival time of the input section I1 of the logic circuit 9 [NULL,
5, 3] Arrival time of the input section I2 of the logic circuit 9 [NULL,
4, 2] Furthermore, for the output parts O1 and O2 of the logic circuit 9, the sets S1, S2, and S3 given by the equation (4) require that value, and other values need the values for the input clock of that set. Set as time. That is, the required time of the output section O1 of the logic circuit 9 [7, 7, 5] The required time of the output section O2 of the logic circuit 9 [7, 7, 7] For the combinational circuit 10 including the random logic elements 11-1, 11-2, 11-3 other than the elements, the signal distribution elements 13-1, 13-2, 13-3, etc., the required time and arrival time are as follows. Calculate to.

That is, the input section I for the logic circuit 9
1, I2, ... And sequential circuit elements Z1, Z2, Z3, Z
Since the arrival times of 4 and 4 are given in the delay value setting procedure 2 for each set, the other random logic elements 11-1 and 11-
2, 11-3 and signal distribution elements 13-1, 13-2,
Arrival time Tik for a set i of logic circuit elements k such as 13-3 is calculated by the following equation in order from the input side.

Tik = max (Dij + Djk) (5) That is, the maximum value for the input to the logic circuit element k that has passed various logic circuit elements j for the set i is obtained.
However, Dij and Djk represent delay times required from the logic circuit element i, j to the logic circuit element j, k. However, when Dij is NULL, Tik is set to NULL when all Dij are NULL.

Further, output units O1 and O for the logic circuit 9 are provided.
2, ~ and sequential circuit elements Z1, Z2, Z3, Z4, ~
Required time is given in the set delay value setting procedure 2, so that the other random logic elements 11-1, 11-2, 1
The required time Hik for the set i of the logic circuit elements k such as 1-3 and the signal distribution elements 13-1, 13-2, 13-3 is calculated by the following equation in order from the output side.

Hik = min (Dij-Djk) (6) That is, the minimum value of the output of the logic circuit element k up to the logic circuit element j is obtained. However, the definitions of Dij and Djk are the same as in the case of Expression (5).

Then, the margin Slack of each logic circuit element is calculated by the value of the following equation (7) to obtain the margin Slac.
If k is negative, it is determined that the delay constraint is violated.

Slack = min (Hi-Ti) (7) That is, the minimum value for all sets i is obtained.
However, Hi is the required time, and Ti is the arrival time. Null items are ignored. If there is no delay constraint violation as a result of this, the entire process is terminated.

Next, FIG. 5 is a diagram showing an example of the random logical tree 12. The random logic tree extraction procedure 4 is performed by the logic circuit 9 including the random logic elements 11-1, 11-2, 11-.
A random logic tree 12 to be reconfigured as shown in FIG. 5 which is a tree-shaped circuit including 3 is selected.

Then, the random logic tree cut constraint setting procedure 5 is performed for each of the cuts n1, n2, ..., Nf on the input side and the cut r on the output side in the selected random logic tree 12 for each set. By the arrival time Tni, j (arrival time for the set Sj at the cut ni) and Hr, j (required time for the set Sj at the cut r) calculated in the delay value calculation procedure 3, Dni = min (Hr, j-Tni, j ) (8) That is, the minimum value for the delay calculation set Sj is obtained. Then, Dmax = max (Dni) (9) That is, the maximum value for the cuts n1, n2, to nf on the input side is obtained.

Further, Hr = Dmax (10) Tni = Dmax-Dni (11), Hr is set as a representative value of the required time of the cut r on the output side, and Tni is set. Input side cuts n1, n2, ~ n
Set as a representative value of the arrival time of f.

Then, in the random logic tree conversion procedure 6, the random logic tree 12 is used in the same manner as the conventional method for the representative value Hr of the required time and the representative value Tni of the arrival time set in the random logic tree cut constraint setting procedure 5. And the delay time is optimized by reconstructing the random logic tree 12.

Next, FIG. 6 is a flow chart showing a second embodiment of the logic circuit delay time optimizing method of the present invention. Also,
FIG. 7 is a diagram showing an example of the signal distribution tree 14. As shown in FIG. 6, the second embodiment has the same delay calculation set creation procedure 1, set-specific delay value setting procedure 2, and set-specific delay value calculation procedure 3 as in the first embodiment.

Therefore, the signal distribution tree extraction procedure 21 is performed by the logic circuit 9 by the signal distribution elements 13-1, 13-2, 13-3.
A signal distribution tree 14 to be reconfigured as shown in FIG.

Then, the signal distribution tree cutout constraint setting procedure 2
2 is a cut t on the input side and cuts m1, m2, to mg on the output side in the selected signal distribution tree 14.
On the other hand, the arrival time Tt, j (arrival time for the set Sj at the cut t) and Hmi, j (set S at the cut mi calculated in the above-mentioned delay value calculation procedure 3 for each set)
Dmi = min (Hmi, j-Tt, j) ... (12) That is, the minimum value for the delay calculation set Sj is obtained. Then, Tt = 0 ... (13) Hmi = Dmi (14), Tt is set as a representative value of the arrival time of the input side cut t, and Hmi is set as the output side cut m1. m2, ~ mg
Set as a representative value of the required time.

Then, in the signal distribution tree conversion procedure 23, the signal distribution tree 14 is processed in the same manner as in the conventional case with respect to the representative value Tt of the arrival time and the representative value Hmi of the required time set in the signal distribution tree cut restriction setting procedure 22. And the delay time is optimized by reconfiguring the signal distribution tree 14.

[0041]

As described above, the logic circuit delay time optimizing method of the present invention divides sequential circuit elements into groups based on the characteristics of the starting point side, and calculates the delay time for each of these groups. This has the effect that the delay time of the logic circuit can be optimized accurately and in a short time.

Further, in the logic circuit delay time optimizing method of the present invention, one representative value is calculated from the delay values for each of the sets before the actual optimization is performed, and the representative value is calculated. Therefore, there is an effect that the delay time optimizing method such as reconfiguration in the conventional logic circuit delay time optimizing method can be used as it is.

[Brief description of drawings]

FIG. 1 is a flowchart showing a first embodiment of a logic circuit delay time optimizing method of the present invention.

FIG. 2 is a diagram showing an example of a logic circuit 9 for optimizing a delay time.

FIG. 3 is a diagram showing an example of the contents of a delay constraint file 8.

FIG. 4 shows sequential circuit elements Z1 and Z included in a logic circuit 9.
2, Z3, Z4, ...
It is a figure which shows an example.

FIG. 5 is a diagram showing an example of a random logical tree 12.

FIG. 6 is a flow chart showing a second embodiment of the logic circuit delay time optimizing method of the present invention.

7 is a diagram showing an example of a signal distribution tree 14. FIG.

[Explanation of symbols]

 1 Delay calculation set creation procedure 2 Set delay value setting procedure 3 Set delay value calculation procedure 4 Random logic tree extraction procedure 5 Random logic tree cut constraint setting procedure 6 Random logic tree conversion procedure 7 Library 8 Delay constraint file 9 Logic circuit 10 Combination circuit 11-1, 11-2, 11-3 Random logic element 12 Random logic tree 13-1, 13-2, 13-3 Signal distribution element 14 Signal distribution tree 21 Signal distribution tree extraction procedure 22 Signal distribution tree cut restriction Setting procedure 23 Signal distribution tree conversion procedure I1, I2, ~ Input section m1, m2, ~ mg Output side cut n1, n2, ~ nf Input side cut O1, O2, ~ Output section r Output side cut S1, S2 , S3, ~ Set t Input side cut Z1, Z2, Z3, Z4 ~ Sequential circuit element φ1, φ2 ~ Clock

Claims (4)

[Claims] 1. A delay calculation for reading out classification information of sequential circuit elements from a delay constraint file for a logic circuit to be subjected to delay optimization, and dividing the sequential circuit elements included in the logic circuit into several sets. And (B) the library information of each logic element including the delay constraint information in the delay constraint file and the sequential circuit element in the library is read out, and each input section of the logic circuit and each sequential circuit element are read. It is necessary to set an arrival time corresponding to each set for each of the output pins of the above, and to correspond to each set for each of the output pins of the logic circuit and the input pins other than the clock input of each sequential circuit element. Set delay value setting procedure for setting time, and (C) each input section and each sequential circuit element of the logic circuit set in the set delay value setting procedure Based on the arrival time of each output pin, the arrival time of each logic element is sequentially calculated toward the output side for each set, and each output of the logic circuit set in the set delay value setting procedure is set. A delay value calculation procedure for each set for sequentially calculating the required time of each logic element toward the input side based on the required time of each input pin of each section and each sequential circuit element; AND, OR, NAND, NOR, EX existing in the logic circuit
A random logic tree extraction procedure for selecting a random logic tree that is a tree-like circuit to be reconfigured by random logic elements such as OR, EXNOR, and their complex logic; and (E) a random logic tree extracted by the random logic tree extraction procedure. For each cut of input and output of, from the arrival time and the required time calculated for each set in the delay value calculation procedure for each set,
By setting the representative values of the arrival time and the required time, a random logic tree added to the random logic tree of the logic circuit as constraint information for each cut of the input / output of the random logic tree extracted by the random logic tree extraction procedure. Based on the cut constraint setting procedure and (F) the constraint information added in the random logical tree cut constraint setting procedure, the random logical tree extracted in the random logical tree extraction procedure is converted to obtain delay time due to reconstruction. A method for optimizing a delay time of a logic circuit, comprising: a random logic tree conversion procedure for performing optimization. 2. (A) The classification information of the sequential circuit elements is read from the delay constraint file for the logic circuit to be the target of delay optimization, and the sequential circuit elements included in the logic circuit are divided into several sets, B) The delay constraint information in the delay constraint file and the library information of each logic element including the sequential circuit element in the library are read out, and each input section of the logic circuit and each output pin of each sequential circuit element are read out. , While setting the arrival time corresponding to each set, for each output pin of the logic circuit and each input pin other than the clock input of each sequential circuit element,
A required time corresponding to each set is set, and (C) each logic is sequentially directed toward the output side based on the arrival time of each set input part of the logic circuit and each output pin of each sequential circuit element. The arrival time of the elements is calculated for each set, and based on the required times of the output pins of the logic circuit and the input pins of the sequential circuit elements that have been set, the logical elements of the logic elements are sequentially turned toward the input side. The required time is calculated for each set, and (D) AND, O existing in the logic circuit
A random logic tree that is a tree-like circuit to be reconfigured by random logic elements such as R, NAND, NOR, EXOR, EXNOR and their complex logic is extracted, and (E) each input / output section of the extracted random logic tree For each set, a representative value of the arrival time and the required time is set from the arrival time and the required time calculated for each set, so that the logic circuit is used as constraint information for each cut of the input / output of the extracted random logic tree. To the random logical tree of (F)
A method of optimizing delay time by converting the extracted random logic tree based on the added constraint information and optimizing the delay time by reconstruction. 3. A delay calculation set creating procedure according to claim 1, a set delay value setting procedure according to claim 1,
A logic circuit delay time optimizing method having the set-based delay value calculation procedure described in (A) Signal distribution of a buffer, an inverter, and their complex logic existing in a logic circuit to be subjected to delay optimization. A signal distribution tree extracting procedure for selecting a signal distribution tree which is a tree-like circuit to be reconfigured by elements, and (B) each of the input and output cuts of the signal distribution tree extracted by the signal distribution tree extracting procedure. From the arrival time and the required time calculated for each set in the delay value calculation procedure, by setting the representative values of the arrival time and the required time, each of the input and output of the signal distribution tree extracted in the signal distribution tree extraction procedure is set. Based on the signal distribution tree cut constraint setting procedure added to the signal distribution tree of the logic circuit as constraint information to the cut, and (C) the constraint information added in the signal distribution tree cut constraint setting procedure. And a signal distribution tree conversion procedure for converting the signal distribution tree extracted in the signal distribution tree extraction procedure and optimizing the delay time by reconfiguration, and a logic circuit delay time optimizing method. . 4. (A) The classification information of the sequential circuit elements is read from the delay constraint file for the logic circuit that is the target of delay optimization, and the sequential circuit elements included in the logic circuit are divided into several sets, B) The delay constraint information in the delay constraint file and the library information of each logic element including the sequential circuit element in the library are read out, and each input section of the logic circuit and each output pin of each sequential circuit element are read out. , While setting the arrival time corresponding to each set, for each output pin of the logic circuit and each input pin other than the clock input of each sequential circuit element,
A required time corresponding to each set is set, and (C) each logic is sequentially directed toward the output side based on the arrival time of each set input part of the logic circuit and each output pin of each sequential circuit element. The arrival time of the elements is calculated for each set, and based on the required times of the output pins of the logic circuit and the input pins of the sequential circuit elements that have been set, the logical elements of the logic elements are sequentially turned toward the input side. (D) A tree-like circuit to be reconfigured by a signal distribution element such as a buffer, an inverter, and their complex logic, which is present in the logic circuit to be subjected to delay optimization, by calculating the required time for each set. A certain signal distribution tree is extracted, and (E) for each input / output section of the extracted signal distribution tree, a representative value of the arrival time and the necessary time is set from the arrival time and the necessary time calculated for each set. thing Then, the extracted signal distribution tree is added to the signal distribution tree of the logic circuit as constraint information for each input / output section of the extracted signal distribution tree, and (F) the extracted signal distribution tree is converted based on the added constraint information. A method for optimizing a delay time by a reconfiguration, comprising: optimizing a delay time.