JPH06231053A - Data saving system - Google Patents

Abstract

PURPOSE:To prevent the storage data of a volatile memory from being deleted without using a battery back-up when a power source is interrupted. CONSTITUTION:The interrupting period of a direct current power source output from a power source 26 for cache when interruption occurs, is delayed by (the discharge action of) a capacitor 263 connected with a smoothing circuit 262 in the power source 26 in parallel. At that time, the supply of the direct current power source from the power source 26 to a cache RAM 23, EEPROM 24, and data saving/restoration control circuit 25 is continued regardless of the occurrence of interruption. Also, at the time of the interruption (direct current power source interruption), a power source interruption signal 27 is outputted from the power source 26. Then, the data saving/restoration control circuit 25 operates data saving from the cache RAM 23 to the EEPROM 24. On the other hand, at the time of restoration from the power source interruption, the data saving/restoration control circuit 25 waits for the end of the change of the capacitor 263, and operates data restoration from the EEPROM 24 to the cache RAM 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device equipped with a readable / writable volatile memory, and more particularly to saving data in the volatile memory to a non-volatile memory when power is cut off. The present invention relates to a data saving method that prevents data loss.

[0002]

2. Description of the Related Art In many disk subsystems of computer systems in recent years, a disk cache system is applied in order to speed up disk access. This disk cache system has a disk cache (cache RAM) of RAM (volatile memory) structure in which a copy of a part of the disk data is placed. When the target data exists in the cache, the disk device is accessed. Even if it does not exist, the target data can be obtained.
There are two disk cache methods, a write-through cache method and a write-back cache method, depending on the difference in write access.

The write-through cache system is a system in which data is written to the disk simultaneously with writing to the cache RAM, and the contents of the cache RAM and the corresponding contents of the disk are always the same.

On the other hand, in the write-through cache method, the writing (requested) is terminated when the data is written in the cache RAM, and the writing from the cache RAM to the disk has a relationship with the load (processing status). This is a method that is appropriately performed while the load is low while watching. This method
Since the performance of write operation to the disk is remarkably improved, it is the mainstream of the disk cache method.

The most important point in applying this write-back cache method is that data in the cache RAM is lost when a power failure or the like occurs. This means that the existence of undisclosed data is a problem.

[0006]

As described above, in the disk subsystem to which the write-back cache system is applied, the performance of the write operation to the disk is remarkably improved, but the data in the cache RAM is lost when a power failure or the like occurs. Therefore, there is a problem when there is unwritten data to the disk in the cache RAM. Therefore, the following two methods have been conventionally known as methods for solving this problem.

The first is a method of using a non-volatile memory instead of a RAM for the storage element of the disk cache. However, in the first method, the writing speed of the non-volatile memory is much slower than that of the RAM, so that there is a problem that the disk cache cannot be satisfied in terms of performance.

Secondly, the RAM is used as a storage device as in the conventional case, and when the power is cut off, the power is backed up using a rechargeable battery to continue the power supply to the RAM (cache RAM), thereby storing the RAM. This is a method to prevent data loss. However, the second method has a problem that the life of the rechargeable battery is short and the number of times of replacement is large.

The present invention has been made in consideration of the above circumstances, and an object thereof is to store data stored in a volatile memory in a non-volatile memory even when a volatile memory (RAM) is used as a storage device when power is cut off. Another object of the present invention is to provide a data saving method in which data loss can be prevented by saving the data to a computer, and a battery backup is unnecessary.

[0010]

The present invention provides an information processing apparatus having a volatile memory, a nonvolatile memory, a control circuit for controlling data saving from the volatile memory to the nonvolatile memory, and an AC power supply. DC power is generated based on
A power supply device for supplying to a volatile memory, a non-volatile memory, and a control circuit, which is charged at the start of energization of an AC power supply,
A power supply device with a built-in large-capacity capacitor is provided for continuing the supply of DC power for a short time even after the AC power is cut off by discharging when the AC power is cut off, and the above control circuit is activated when the AC power is cut off. In addition, the configuration is characterized in that it receives the DC power continuously supplied from the power supply device by discharging the capacitor and saves the data from the volatile memory to the nonvolatile memory.

Further, according to the present invention, the control circuit starts data restoration from the non-volatile memory to the volatile memory in response to the completion of charging of the capacitor when the power supply is restored from the AC power interruption. It is also characterized by what was done.

[0012]

In the above structure, when the AC power supply of the power supply device is cut off due to a power failure or the like, the control circuit is activated. At this time, the capacitor built in the power supply device starts discharging because the AC power supply is cut off. As a result, the interruption of the DC power supplied from the power supply device to the volatile memory, the non-volatile memory, the control circuit, etc. is delayed, and the DC power supply is continued for a short time. The control circuit
Upon receiving the DC power supply accompanying the discharge of the capacitor, the stored data in the volatile memory is saved in the non-volatile memory when the AC power supply is cut off. Since this data saving can be done in a short time, it is possible to store the data in the volatile memory only by slightly delaying the cutoff time of the DC power supply by the capacitor built in the power supply device (about 8 seconds in the case of the volatile memory having a capacity of 16 MB). Data loss can be prevented.

Next, when the AC power is supplied to the power supply device after recovery from a power failure or the like, charging of the discharged capacitor is started, and the control circuit is restarted in response to the completion of the charging. It Then, the control circuit restores the data saved in the non-volatile memory to the volatile memory. As a result, normal operation becomes possible.

[0014]

1 is a block diagram showing an embodiment in which the data saving method of the present invention is applied to a magnetic disk subsystem of a computer system.

In the figure, reference numeral 1 is a CPU 1, 2 which is the center of the computer system, and 2 is a magnetic disk subsystem to which a write-back cache system is applied. The CPU 1 and the magnetic disk subsystem 2 are connected by an I / O bus 3.

The magnetic disk subsystem 2 includes a controller 21 that controls the entire system 2, two disk drives 22 that are access-controlled by the controller 21, and 16 MB (megabyte) R, for example.
AM configuration disk cache (hereinafter referred to as cache RA
(Referred to as M) 23. This cache RA
The M23 is used to hold a copy of a part of the storage data of the disk drive 22 (a disk that is a storage medium mounted in the disk drive 22).

The magnetic disk subsystem 2 is also a readable / writable non-volatile memory (having the same capacity as the cache RAM 23) used for saving the data stored in the cache RAM 23, for example, an EEPROM (electrically erasable PROM). 24, data saving from the cache RAM 23 to the EEPROM 24, and the EEPROM
It has a data save / restore control circuit 25 for controlling data restoration from 24 to the cache RAM 23, and a cache power supply 26 for generating a DC power supply with a rating of 3.5 A and 5 V from an AC power supply (commercial power supply). . The DC power generated by the cache power supply 26 is the cache RA.
It is supplied to the M23, the EEPROM 24, and the data save / restore control circuit 25 as driving power.

The cache power supply 26 includes a rectifying circuit 261 for rectifying an alternating current and a smoothing circuit 262 for smoothing a rectified voltage.
And a large-capacity capacitor 263 provided between and. The capacitor 263 is connected in parallel with the smoothing circuit 262, and is charged when the AC power supply to the cache power supply 26 is energized and discharged when the AC power supply is shut off.

The capacitor 263 does not immediately shut off the DC power supply even if the AC power supply is shut off due to the discharging action when the AC power supply is shut off, so that the DC power supply output continues for a short time (that is, the DC power supply shutoff timing is delayed). Is provided). As for the capacity of the capacitor 263, the discharge time (delay time of DC power supply cutoff) is determined by the cache RAM 23.
It is necessary to select a time period that is sufficiently longer than the time period (here, about 7 seconds) required to save data from the memory to the EEPROM 24. In this example, the capacity of the capacitor 263 is 5,610 μF, and in this case, it is possible to delay the DC power supply cutoff timing accompanying the AC power supply cutoff by about 8 seconds. The delay time when the capacitor 263 is not used is about 400 milliseconds when the capacity of the capacitor in the smoothing circuit 262 is 300 μF.

The cache power supply 26 has a known function of detecting AC power interruption due to power failure or the like and outputting a power interruption signal 27, and also when the capacitor 263 is charged by the start of energization of the AC power supply. In addition, it has a function of detecting that the charging voltage becomes equal to or higher than a predetermined level (by a charging completion detecting circuit (not shown)) and outputting the charging completion signal 28. The power cutoff signal 27 and the charge completion signal 28 are supplied to the data save / restore control circuit 25. Note that FIG.
In, the controller power supply for supplying power to the controller 21 is omitted. Next, the operation of the magnetic disk subsystem 2 in FIG. 1 will be described.

In the magnetic disk subsystem 2 to which the write-back cache method is applied, when the CPU 1 makes a disk write request, the controller 21 reports the completion of writing to the CPU 1 when the data is written in the cache RAM 23. It Then, writing to the disk drive 22 is performed in consideration of a light load.

In such a write-back cache system, although the performance of the disk write access can be improved, if the power supply to the cache RAM 23 is lost due to a power failure or the like, the data stored in the cache RAM 23 will be lost. It becomes impossible to rewrite unwritten data (unupdated data) in the disk drive 22 (a disk mounted in the disk drive) into correct data.

In this embodiment, however, the cache R is delayed by the action of the capacitor 263 in the cache power supply 26 when a power failure or the like occurs.
The data stored in the AM 23 is saved in the EEPROM 24 so that the contents of the cache RAM 23 can be restored by the saved data when returning from a power failure or the like.
Hereinafter, the data saving operation at the time of power failure and the data restoring operation at the time of recovery from the power failure will be described with reference to the flowcharts of FIGS. 2 and 3.

First, when a power failure occurs and the AC power input to the cache power supply 26 is shut off, the cache power supply 26 (a power shutoff detection circuit (not shown)) detects that fact and saves data. The power-off signal 27 is output to the restoration control circuit 25 (step S1).

In the cache power supply 26,
Since the AC power supply is cut off, the discharge of the capacitor 263 is started. As a result, even if the AC power is cut off,
The period until the discharge of this capacitor 263 is completed is
In accordance with the discharge current from the capacitor 263, the DC power supply output from the cache power supply 26 is continued and the cache RA
DC power is supplied to the M23, the EEPROM 24, and the data save / restore control circuit 25 (step S2).

The data save / restore control circuit 25 is activated by the power cutoff signal 27 from the cache power supply 26, and the data stored in the cache RAM 23 is stored in the EEPROM.
Processing for transferring to 24 and writing, that is, cache RAM 23
A data saving process is performed to save the stored data in the EEPROM 24 (step S3). The time required for this save processing is about 7 seconds in the present embodiment in which the capacity of the cache RAM 23 and the EEPROM 24 is 16 MB. On the other hand, the discharge time of the capacitor 263 (the delay time of the cutoff of the DC power supply due to the cutoff of the AC power supply) is 5,610.
When it is set to μF, it takes about 8 seconds. Therefore, during the above data saving process, the DC power supply from the cache power supply 26 to the cache RAM 23, the EEPROM 24, and the data save / restore control circuit 25 is surely continued by the discharging operation of the capacitor 263 in the cache power supply 26. Thus, the data saving process is surely executed.

Next, when the power supply for cache 26 is restored from the power failure and the AC power is supplied to the power supply for cache 26, the charging of the capacitor 263 in the power supply for cache 26 is started. Then, when the charging voltage of the capacitor 263 becomes equal to or higher than a predetermined level and the charging is completed (in this embodiment, the charging is completed in about 30 seconds), the cache power supply 26 (the charging completion detection circuit (not shown) therein) indicates that. The charge completion signal 28 is detected and output to the data save / restore control circuit 25 (step S11).

The data save / restore control circuit 25 is restarted by the charging completion signal 28 from the cache power supply 26, and contrary to the above, the data saved in the EEPROM 24 is transferred to the cache RAM 23 and written therein. processing,
That is, a data restoration process is performed to restore the contents of the cache RAM 23 to the state immediately before the power failure (step S12). When this data restoration process is completed, normal operation of the magnetic disk subsystem 2 becomes possible.

In the above embodiment, in order to prevent the DC power output from the cache power supply 26 from being immediately shut off in the event of a power failure or the like, more specifically, delaying the DC power shutoff is delayed. Then, in order to enable the data to be saved from the cache RAM 23 to the EEPROM 24 within the delay time, the case where the large capacity capacitor 263 is provided in parallel with the smoothing circuit 262 has been described, but the present invention is not limited to this. For example, the smoothing circuit 26
A large-capacity capacitor may be used as the capacitor included in 2.

The case has been described above in which the stored data in the cache RAM 23 in the magnetic disk subsystem 2 is saved in the non-volatile memory (EEPROM 24) in the event of a power failure in order to prevent the stored data from being lost during a power failure. , This invention is a cache R
Not only the AM 23 but also the volatile memory in general can be applied to the prevention of loss of stored data at the time of power failure.

[0031]

As described above in detail, according to the present invention,
An information processing device equipped with a volatile memory is provided with a non-volatile memory and a control circuit for controlling data saving from the volatile memory to the non-volatile memory, and the volatile memory, the non-volatile memory, the control circuit, etc. A large-capacity capacitor is provided in the power supply unit that supplies DC power when the AC power is turned on and is discharged when the AC power is turned off. Data is saved from the volatile memory to the non-volatile memory under the control of the control circuit within the shutdown delay time, so even if a power failure occurs, the stored data in the volatile memory will not be lost. This can be prevented, and maintenance is simplified because a battery backup system is not used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the data saving method of the present invention is applied to a magnetic disk subsystem of a computer system.

FIG. 2 is a flow chart for explaining a data saving operation at the time of power failure in the same embodiment.

FIG. 3 is a flowchart for explaining a data restoration operation at the time of recovery from a power failure in the same embodiment.

[Explanation of symbols]

1 ... CPU, 2 ... Magnetic disk subsystem, 21 ... Controller, 22 ... Disk drive, 23 ... Cache RAM (volatile memory), 24 ... EEPROM (nonvolatile memory), 25 ... Data save / restore control circuit, 26
... cache power supply, 261 ... rectifier circuit, 262 ... smoothing circuit, 263 ... capacitor.

Claims (2)

[Claims] 1. An information processing device comprising a readable / writable volatile memory, comprising: a non-volatile memory used to save the stored data of the volatile memory; and the volatile memory to the non-volatile memory. And a power supply device for generating a direct current power supply based on an alternating current power supply and supplying the direct current power supply to at least the volatile memory, the non-volatile memory and the control circuit, A power supply device having a built-in large-capacity capacitor for continuing the supply of the DC power supply for a short time even after the AC power supply is cut off by charging when the AC power supply starts to be energized and discharging when the AC power supply is cut off; The control circuit is activated when the AC power supply is cut off, receives the DC power supply continuously supplied from the power supply device by discharging the capacitor, and volatilizes the control circuit. Data storage method, characterized in that it is configured to save data stored in a non-volatile memory to the non-volatile memory. 2. The control circuit restores data from the non-volatile memory to the volatile memory in response to completion of charging of the capacitor when the AC power supply of the power supply device is restored. The data saving method according to claim 1.