JPH06224944A - Serial data reception circuit - Google Patents

Abstract

PURPOSE:To obtain the serial data reception circuit at a low cost and with a small circuit scale which is able to receive phase modulation serial data. CONSTITUTION:A start-stop synchronization data conversion circuit 2 samples received phase modulation serial data by using a clock signal being higher than a bit rate, that is, a multiple of (mX2)XjXp of the bit rate of phase modulation serial data fed from a clock generating circuit 5. Then the circuit 2 converts the phase modulation serial data into m-bit parallel data in the unit of p-bits based on data of majority decision of each of j-sets of sampling data. A control circuit 3 reads the parallel data from the start-stop synchronization data conversion circuit 2 and a logic arithmetic operation circuit 4 generates p-bit data of the phase modulation serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication circuit for reading start-stop synchronization serial data or phase modulation serial data, and more particularly to a start-stop synchronization serial data receiving circuit for reading start-stop synchronization serial data or phase modulation serial data. The present invention relates to a serial data receiving circuit suitable for use in the above.

[0002]

2. Description of the Related Art A conventional example will be described below.

As a communication circuit for transmitting and receiving data of different communication systems, there is Japanese Patent Publication No. Sho 55-140936 "Communication control device". In this receiving operation, data of different communication systems such as start-stop synchronization type, independent synchronization type, and flag synchronization type are format-converted into parallel data by a communication control interface corresponding to each communication type,
It is read by the communication controller and supplied to the arithmetic and control unit. Further, the communication control controller is configured to perform setting and control for format conversion into parallel data at each communication control interface.

[0004]

As described above, in the conventional method, when reading data of different communication methods of phase-modulated serial data and start-stop synchronous serial data,
A dedicated data conversion circuit is required for each.

However, when the phase modulation data conversion circuit and the start-stop synchronization data conversion circuit are used, the circuit scale becomes large.
Further, the phase modulation data conversion circuit is difficult to obtain as a general-purpose product, and it is necessary to develop it using an MPU (microprocessor). Therefore, the circuit scale becomes large, and it becomes a problem in short-term and low-cost product development.

There is also a method of directly fetching the phase modulation serial data from the port of the control circuit, but in this case, the processing of the control circuit is performed by the phase modulation serial data while the phase modulation serial data is being transmitted. You have to concentrate on capturing the data, and other processing cannot be performed satisfactorily.

Another object of the present invention is to solve the above problems,
It is an object to provide a small-scale, low-cost serial data receiving circuit that reads phase-modulated serial data.

[0008]

In order to achieve the above-mentioned object, in the present invention, the clock generation means uses k times the bit rate of the phase-modulated serial data inputted (k>
(m + 2) clock generating means and a clock from the clock generating means are input, and data of 1 bit or 2 bit unit of the phase-modulated serial data is transmitted at a bit rate of m + 2 [bit / sec]. Considered as serial data in synchronous serial data format,
Sampling is performed by the clock from the clock generation means, a majority decision is made in units of k / (m + 2) sampling data, and m-bit data after the first "0" data is output as parallel data of bit number m. Also, start-stop synchronization data conversion means for outputting status data indicating that the parallel data has been converted, control means for reading parallel data according to the status data output from the start-stop synchronization data conversion means, and The parallel data read by the control means is logically operated or logically determined to generate bit data in units of 1 bit or 2 bits of the original phase-modulated serial data.

[0009]

In the start-stop synchronization data conversion circuit, the phase-modulated serial data is converted into the bit rate k of the phase-modulated serial data.
Sampling with a double clock, and majority decision,
It is converted into parallel data of bit number m in units of 1 bit or 2 bits.

Therefore, according to the present invention, the phase modulation serial data can be read without using a dedicated phase modulation data conversion circuit. Further, since the control circuit reads parallel data according to the status data from the start / stop synchronization data conversion circuit, the processing is not occupied.

As a result, it is possible to receive the phase-modulated serial data with a small circuit scale and a low cost structure.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a serial data receiving circuit as a first embodiment of the present invention, FIG. 4 is a timing chart showing the timing of the main signal of FIG. 1, and FIG. 5 is the main signal of FIG. 3 is a timing chart showing the timing of FIG.

Note that each reference numeral in FIG. 4 corresponds to each reference numeral in FIG.

First, the operation of the serial data receiving circuit according to the first embodiment will be described with reference to FIGS.

The bit data of the phase-modulated serial data A (FIG. 4A) has a signal level of "0" during a 1-bit cycle period.
Is represented by the ratio of the period of 1 to the period of “1”. For example, in the case of bit data, if the period of “0” in the 1-bit cycle period is longer than the period of “1”, the bit data is “0” or 1 bit. When the "0" period of the cycle period is shorter than the "1" period, the signal indicates "1". The phase-modulated serial data A is input via the serial data input terminal (1) and supplied to the start-stop synchronization data conversion circuit (2). Further, the start-stop synchronization data conversion circuit (2) samples the phase-modulated serial data A input by the control signal E from the control circuit (3) with the sampling clock H (FIG. 4H) from the clock generation circuit (5). For example, the number j of pieces of data for judging majority of the sampling data B (FIG. 4B) is
j = 8, and the number of bits m to be converted into the parallel data B is set to, for example, m = 7 bits.

The clock generation circuit (5) inputs the basic clock G output from the clock generation circuit (6) to the start-stop synchronization data conversion circuit (2) according to the control signal F from the control circuit (3). It is set to a frequency division ratio to be output as a sampling clock H having a frequency of (m + 2) × j times the bit rate of the phase-modulated serial data A.
That is, the control signal F is, for example, 8-bit binary data, and the clock generation circuit (5) is, for example, PTC.
Like a (programmable timer counter), in which the count value indicated by the control signal F is set in the timer counter as the timer initial value and decremented.
When the timer counter value reaches zero, the output is inverted,
Further, by repeating the operation of setting the timer initial value in the timer counter, the sampling clock H obtained by dividing the basic clock G is generated.

In the start / stop synchronization data conversion circuit (2),
The phase-modulated serial data A that is input is sampled with the sampling clock H from the clock generation circuit (5), and, for example, when the sampling clock H is a clock of (m + 2) × j times the bit rate, the sampling clock H is used. A majority decision is made for every j pieces of sampled data. Further, the first bit of "0" is detected as the start bit from the data determined by the majority decision, and the m-bit data after the start bit is converted into the parallel data B using, for example, a shift register. Also, the start-stop synchronization data conversion circuit (2) becomes "1" when it detects "1" data following the majority-decision-determined m-bit data as a signal indicating that the parallel data B has been converted. The status data C (FIG. 4C) is output.

The control circuit (3) inputs, for example, the status data C as an interrupt signal according to the status data C from the start / stop synchronization data conversion circuit (2), and the status data C changes from "0" to "1". When the change is detected, the interrupt processing is performed and the parallel data B is read. Further, the parallel data B read by the control circuit (3) is converted into parallel data B by the start / stop synchronization data conversion circuit (2) by at least one of logical operation and logical judgment by the logical operation circuit (4). Bit data of the converted phase-modulated serial data A is generated. Here, as a method of generating bit data of the phase-modulated serial data A from the parallel data B, for example, in the phase-modulated data conversion circuit (2), the phase-modulated serial data A has a bit number m = 7 in 1-bit units. When converted into parallel data B, the bit 4 of the parallel data B read by the control circuit (3) is determined. If bit 4 is “0”, the bit data is “0”, and bit 4 is “1”.
In that case, a method of setting the bit data to "1" can be considered.

By the above operation, the phase modulated serial data can be received.

The second embodiment of the serial data receiving circuit capable of receiving both phase modulated serial data and start / stop synchronization serial data will be described below.

FIG. 2 is a block diagram showing the configuration of the serial data receiving circuit according to the second embodiment, and FIG. 5 is a timing chart showing the timing of the main signal of FIG.

That is, the second embodiment is provided with a serial data input terminal (7) and a mode detection circuit (9) in addition to the configuration shown in FIG.

The operation of the serial data receiving circuit of the second embodiment will be described with reference to FIGS. 2, 4 and 5.

The symbols in FIGS. 4 and 5 correspond to the symbols in FIG. 2, respectively.

The phase-modulated serial data A (A in FIGS. 4 and 5) is supplied to one input terminal of the switch circuit (8) and the mode detection circuit (9) via the serial data input terminal (1). To be done. Asynchronous serial data M
(FIG. 5M) is supplied to the other one input terminal of the switch circuit (8) and the mode detection circuit (9). The mode detection circuit (9) detects that at least one of the phase-modulated serial data A and the start-stop synchronization serial data M is input, and the detection result is detected, for example, when the phase-modulated serial data A is input. Is "0", otherwise it is "1" 1-bit mode detection data J (see FIG. 5).
J) is output and supplied to the control circuit (3). Here, as a method of detecting the input of the phase-modulated serial data A in the mode detection circuit (9), for example, an attention signal indicating the start of data transmission of the phase-modulated serial data,
For example, there is a method of detecting a "0" signal for a period much longer than the 1-bit cycle period of phase-modulated serial data.

Further, in the switch circuit (8), depending on the control signal L from the control circuit (3), for example, when the control signal L is "0", it is on the input terminal I side, and the control signal L is "1".
In the case of, the input terminal II side is switched, and the serial data K (FIG. 5K) in which the phase-modulated serial data A and the start-stop synchronization serial data M are combined is output and supplied to the start-stop synchronization data conversion circuit (2). Clock generation circuit (5)
May be, for example, the PTC in the above-described first embodiment, and a division ratio for dividing the basic clock G from the clock generation circuit (6) by the control signal F from the control circuit (3) may be used. Change, for example, start / stop synchronization data conversion circuit (2)
When the data of the serial data K input to is the data of the phase-modulated serial data A, the sampling clock H of (m + 2) × j times the bit rate of the phase-modulated serial data A is generated, and the start-stop synchronization data conversion circuit (2)
When the data of the serial data K input to is the data of the asynchronous serial data M, a sampling clock H of j times the bit rate of the asynchronous serial data M is generated and supplied to the asynchronous data conversion circuit (2). To do. Here, the control signal F is, for example, 8-bit binary data, and is a counter initial value of a timer counter for generating the sampling clock H to be supplied to the start-stop synchronization data conversion circuit (2).

When the serial data K input from the switch circuit (8) is the phase-modulated serial data A, the start-stop synchronization data conversion circuit (2) is, for example, a sampling clock from the clock generation circuit (5). The number j of majority judgments of the sampling data sampled by H is set to j = 8, the number of bits m to be converted into the parallel data B is set to m = 7, and the serial data input from the switch circuit (8) is set. When K is the asynchronous serial data M, for example, the number j of majority judgments of the sampling data sampled by the sampling clock H from the clock generation circuit (5) is converted to j = 8 and to the parallel data B. The number of bits m is set to m = 6 by the control signal E from the control circuit (3). Thus, the start-stop synchronization data conversion circuit (2)
According to the control signal E, the phase-modulated serial data A or the start-stop synchronization serial data M is sampled by the sampling clock H, respectively, and the start bit is detected from the data obtained by the majority decision for every j pieces of the sampling data. , M bits of data following the start bit are extracted to generate parallel data B having the number of bits m and output to the control circuit (3). The start-stop synchronization data conversion circuit (2) outputs status data C indicating that the serial data K has been converted into parallel data B.

The control circuit (3) includes a mode detection circuit (9).
A control signal L for controlling the switch circuit (8), a control signal E for controlling the start / stop synchronization data conversion circuit (2), and a control signal F for controlling the clock generation circuit (5) based on the mode detection data J from And output. Further, in response to the status data C from the start / stop synchronization data conversion circuit (2), for example, the status data C is input as an interrupt signal, and when it is detected that the status data C has changed from "0" to "1". , Interrupt processing is performed and parallel data B is read. Further, in the control circuit (3), when the mode detection data J from the mode detection circuit (9) indicates that the phase modulation serial data A is input, the read parallel data B is changed to the logical operation circuit ( In 4), the phase-modulated serial data A converted into the parallel data B in the start / stop synchronization data conversion circuit (2) by at least one of the logical operation and the logical determination.
Generate the bit data of. Here, the parallel data B
As a method of generating the bit data of the phase-modulated serial data A, for example, when the phase-modulated serial data A is converted into parallel data B having a bit number of 7 in 1-bit units, the parallel data read by the control circuit (3) is used. A method of judging bit4 of the data B and setting the bit data to "0" if the bit4 is "0" and setting the bit data to "1" if the bit4 is "1" can be considered.

These operations enable reception of either the phase-modulated serial data A or the start-stop synchronization serial data M.

The above is a description of the operation of the first and second embodiments.

In the first and second embodiments, the start / stop synchronization data conversion circuit (2) uses the method of converting the phase-modulated serial data into parallel data in 1-bit units. The sampling clock obtained by dividing the frequency by the clock generation circuit (5) is not limited to (m + 2) × j × of the bit rate of the phase-modulated serial data.
1 time, (m + 2) × j × 2 times, ..., (m + 2) × j × p
It is obvious that the phase-modulated serial data can be converted into parallel data in units of 1 bit, 2 bits, ...

In the mode detection circuit (9) of FIG. 2,
The case where the detection of the phase-modulated serial data A is detected by the attention signal indicating the start of transmission of the phase-modulated serial data A has been described, but in the present invention, the serial data input terminal (1) is composed of a plurality of signal lines. And
This is also effective when detecting by a signal line other than the signal line for phase modulation serial data transmission.

In the mode detection circuit (9) shown in FIG.
The state of mode detection data J is phase-modulated serial data A
However, in the present invention, the state of the mode detection data J may be changed when the start / stop synchronization serial data M is input.

The mode detection circuit (9) of FIG. 2 may be included in the control circuit (3).

Next, another embodiment of the configuration of the clock generation circuit (5) in the second embodiment will be described.

FIG. 3 is a block diagram showing a clock generation circuit (5) as a third embodiment.

In FIG. 3, the basic clock G from the clock generating circuit (6) is supplied to the frequency dividing circuit 1 (10) and the frequency dividing circuit 2 (11). The frequency dividing circuit 1 (10) and the frequency dividing circuit 2 (11) may be, for example, PTC. The frequency dividing circuit 1 (10) receives the control signal F from the control circuit (3) and outputs the bit rate (m of the bit rate of the phase-modulated serial data A input to the start-stop synchronization data conversion circuit (2).
The frequency dividing ratio is set to obtain a sampling clock H of +2) × j times, and the frequency dividing circuit 2 (11) inputs the start / stop synchronization serial data M to the start / stop synchronization data conversion circuit (2).
The frequency division ratio is set to obtain a sampling clock H that is j times the bit rate. Thus, the frequency divider circuit 1 (10)
The basic clock G divided by is supplied to one input terminal of the switch circuit (12) as a clock Q, and the basic clock G divided by the divider circuit 2 (11) is supplied as a clock R to the switch circuit. (12) It is supplied to the other one input terminal. In the switch circuit (12), for example, the control signal F ′ is a 1-bit signal according to the control signal F ′ from the control circuit (3), and when it is “0”, the input terminal is
To the III side, and when the control signal F'is "1", input terminal IV
The sampling clock H, which is switched to the side and selectively outputs the clock Q and the clock R, is supplied to the start-stop synchronization data conversion circuit (2).

From this, the start-stop synchronization data conversion circuit (2)
It is possible to generate the sampling clock H necessary for receiving the phase-modulated serial data A or the start-stop synchronization serial data M input to the.

Although the frequency dividing circuit 1 (10) and the frequency dividing circuit 2 (11) in FIG. 3 have been described as being capable of changing the frequency dividing ratio, the present invention has only a fixed frequency dividing ratio. It is obvious that the method can be applied even when the frequency divider circuit is used.

The switch circuit (8) in FIG. 2 and the switch circuit (12) in FIG. 3 have been described in the case of being controlled by the control signal L and the control signal F'from the control circuit (3), respectively. The present invention is also applied to the case where the switch circuit (8) and the switch circuit (12) are controlled by the mode detection data J from the mode detection circuit (9).

[0042]

As described above, according to the present invention,
By giving a sampling clock of (m + 2) × j times the bit rate of the phase-modulated serial data to the start-stop synchronization data conversion circuit, the phase-modulated serial data can be converted into parallel data in bit units, and at least either logical operation or logical judgment can be performed. By generating the bit data of the phase-modulated serial data by one of the processes, the phase-modulated serial data can be received.

Further, by supplying a sampling clock of (m + 2) × j times the bit rate of the phase-modulated serial data and a sampling clock of j times the bit rate of the asynchronous serial data to the start / stop synchronization data conversion circuit by switching. A serial data receiving circuit that can handle both phase-modulated serial data and start-stop synchronous serial data can be realized in a small scale and at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a serial data receiving circuit as a first embodiment of the present invention.

FIG. 2 is a block diagram showing a serial data receiving circuit as a second embodiment of the present invention.

FIG. 3 is a block diagram showing a clock generation circuit according to a third embodiment of the present invention.

4 is a timing chart showing signal timing of main parts of the serial data receiving circuit of FIGS. 1 and 2. FIG.

5 is a timing chart showing signal timing of main parts of the serial data receiving circuit of FIG.

[Explanation of symbols]

1, 7 ... Serial data input terminal, 2 ... Start-stop synchronization data conversion circuit, 3 ... Control circuit, 4 ... Logical operation circuit, 5 ... Clock generation circuit, 6 ... Clock generation circuit, 8, 12 ... Switch circuit, 9 ... Mode Detection circuit, 10 ... Dividing circuit 1, 1
1 ... Divider circuit 2.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatoshi Sudo, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company, AV equipment division, Hitachi Ltd.

Claims (3)

[Claims] 1. A serial data communication circuit for transmitting / receiving start-stop synchronous serial data, comprising an arithmetic processing circuit for performing format conversion, control code (code) discrimination, control command decoding, status information transmission, etc. The start-stop synchronization serial data is sampled with an external clock that is n times the bit rate of the start-stop synchronization serial data, and a start bit is detected from the bit data for which a majority decision is made for every n sampling data, and the start bit is continued. m data bits are extracted and converted to parallel data with m bits,
Data conversion means (2) for outputting the parallel data and status data indicating that the start-stop synchronization serial data has been converted to the parallel data, and phase-modulated serial data as input, and the data conversion means (2 ) Serial data input means 1
(1), clock generation means (6) for generating a clock having a frequency higher than the bit rate of the phase-modulated serial data input to the serial data input means 1 (1), and output from the clock generation means (6) A clock which is k times (k> m + 2) the bit rate of the phase-modulated serial data and is supplied to the data conversion means (2); According to the status data output from the means (2), the phase-modulated serial data is read out as data converted into parallel data with a bit number m in p-bit units, and at least one of logical operation and logical judgment is performed. Logical operation means (4) for generating p-bit bit data of the phase-modulated serial data by the processing of and the data conversion Stage (2) and said logical operation means (4) and the serial data receiving circuit, wherein the control means (3) and in that it consists of the control of a clock generating means (5). 2. The serial data receiving circuit according to claim 1, wherein serial data input means 2 (7) for inputting asynchronous serial data and asynchronous serial data from said serial data input means 2 (7) A data selection means (8) for selectively outputting the phase-modulated serial data from the serial data input means 1 (1), and detecting that at least one of the phase-modulated serial data and the start-stop synchronization serial data is input. The serial data receiving circuit is characterized by further comprising a mode detecting means (9) for outputting a detection result. 3. The serial data receiving circuit according to claim 1, wherein the clock generation circuit is a clock having a bit rate k times the bit rate of the phase-modulated serial data input to the serial data input means 1 (1). And a clock frequency dividing means 2 (11) for generating a clock that is n times the bit rate of the start-stop synchronization serial data input to the serial data input means 2 (7). And a clock selection for selectively outputting the clock 1 from the clock frequency dividing means 1 (11) and the clock 2 from the clock frequency dividing means 2 (2) according to the control signal from the control circuit (3). A serial data receiving circuit comprising: a means (12);