JP2002281504A - 0/1 detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 0/1 detecting circuit for attaining high speed 0/1 detecting processing to an n-bit parallel signal. SOLUTION: A mask part 1 masks one part of a parallel signal 3 at a signal level designated by a level designating part 4 and outputs a mask signal 5. A level detecting part 2 detects whether or not the signal level designated by the level designating part 4 exists in the mask signal 5 and when that signal level exists there, a position signal showing that bit position and a detecting signal 7 showing the existence as a result of detection are outputted. When the detecting signal 7 is fed back to the level designating part 4, the level designating part 4 inverts out a level designating signal 8. On the other hand, the mask part 1 masks the parallel signal 3 up to the bit position shown by the fed-back position signal 6 at a signal level designated by the level designating signal 8 at output timing of the detecting signal 7 and outputs the mask signal 5. Such operation is repeated until the designated signal level is not detected any more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 0/1 detection circuit, and more particularly, to detecting information on a position of a signal represented by a binary value of 0 or 1 whose value has changed from 0 to 1 or from 1 to 0. 0 /
1 detection circuit.

[0002]

2. Description of the Related Art Conventionally, this type of 0/1 detection circuit has a continuous binary signal (0 or 1) for reset control by detecting a change point, timing operation for shifting to the next operation, and image processing. Is used for an encoder or the like that converts a symbol into a code.

FIG. 4 is a block diagram showing a configuration of a conventional 0/1 detection circuit. A conventional 0/1 detection circuit converts a parallel signal 44 into a serial signal 45 by a parallel / serial converter 41,
The exclusive OR circuit 43 holds the data in the holder 42 and
, The change from 0 to 1 or from 1 to 0 is detected by taking the exclusive OR of the serial signal 45 and the serial signal 46 held immediately before this signal.

[0004]

The conventional 0/1 described above
In the detection circuit, since the detection processing is performed in serial processing, for example, the input signal is n bits, and the operation speed of the circuit is m.
If the frequency is Hz, the signal transfer rate is m / n Hz, and there is a problem that the encoding processing speed is reduced regardless of the change point.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a 0/1 detection circuit that realizes a high-speed 0/1 detection process.

[0006]

According to the present invention, there is provided a 0/1 detection circuit, comprising: a level designation unit for designating a detection signal level;
A mask processing unit that masks a part of the input parallel signal at a signal level designated by the level designation unit and outputs a mask signal; and detects a bit signal of the signal level designated by the level designation unit from the mask signal. A level detection unit that outputs a detection signal indicating a signal level change point of the mask signal and a position signal indicating a bit position of the signal level, wherein the mask unit performs the input parallel processing up to a bit position indicated by the position signal. Masking the signal;
When the detection signal is input, the level designating signal is inverted and output.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 2 is a time chart showing the operation of the first embodiment. FIG. 3 is a block diagram showing a second embodiment of the present invention.

The 0/1 detection circuit of the first embodiment is shown in FIG.
As shown in FIG. 3, the mask unit 1, the level detection unit 2, and the level designation unit 4 are provided.

The mask unit 1 masks a part of the input parallel signal 3 with “0” or “1”, and generates a mask signal 5.
Is output. Note that the partial specification in the mask processing is performed by a level detection unit 2 described later, and selection of “0” or “1” is specified by a level specification unit 4 described later.

The level specifying section 4 outputs a level specifying signal 8 for specifying the level (0 or 1) of the signal to be detected to the mask section 1 and the level detecting section 2. The value of the level designation signal 8 is inverted according to the detection state of the level detection unit 2. As a specific inversion means, a selector or the like can be given. In the present embodiment, it is assumed that “0” is set as the initial value of the level designation signal 8.

The level detecting section 2 is a circuit for detecting whether or not the mask signal 5 output from the mask section 1 contains a signal of the level specified by the level specifying signal 8. Is present, a detection signal 7 indicating presence of level detection and a position signal 6 indicating the bit position in binary are output. The detection signal 7 is fed back to the level detection unit 2 and the mask unit 1, and the position signal 6 is fed back to the mask unit 1. The level detector 2 is realized by, for example, an exclusive OR circuit or the like.

Next, the operation of the first embodiment will be described in detail with reference to FIGS. The parallel signal 3 in the present embodiment will be described below as an 8-bit parallel signal “11000011” having two change points.

When the parallel signal 3 of "11000011" is input to the mask unit 1, the mask unit 1 does not perform any processing and uses the parallel signal 3 as a mask signal 5 as it is as a level detector 2
Output to

The level detecting section 2 performs an exclusive OR operation on the mask signal 5 and the level specifying signal 8 input from the level specifying section 4, and the level specified by the level specifying signal 8 exists in the mask signal 5. Is detected.

Here, the mask signal 5 is "1100001"
Since the level designation signal 8 is “0”, the level detection unit 2 detects that the third bit of the mask signal 5 has “0” level, and the position signal 6 represents “011” representing binary “3” as the position signal 6. Is output as a detection signal 7 and a pulse "1" indicating that a level is detected.

The level designating section 4 receives a signal from the level detecting section 2
When the position signal 6 indicating 011 ″ is fed back,
The level designation signal 8 is inverted from “0” to “1” and output to the mask unit 1 and the level detection unit 2.

On the other hand, when the position signal 6 and the detection signal 7 fed back from the level detection unit 2 are input, the mask unit 1 masks the first three bits of the parallel signal 3 indicating "11000011" with "0". And "0000001
1 ”is output to the level detector 2 as the mask signal 5.

The level detector 2 performs an exclusive OR operation of “00000011” output as the mask signal 5 and the designation signal 8 indicating the “1” level, and the level “1” signal is added to the mask signal 5. Detect if it exists. Then, when detecting that the seventh bit of the mask signal 5 is “1”, the level detection unit 2 indicates “111” representing binary “7” as the position signal 6 and indicates that there is level detection as the detection signal 7. The pulse "1" is output.

The level designating section 4 receives a signal from the level detecting section 2
When the position signal 6 indicating 111 ″ is fed back,
The level designation signal 8 is inverted from “1” to “0” and output to the mask unit 1 and the level detection unit 2.

On the other hand, when the position signal 6 and the detection signal 7 fed back from the level detection unit 2 are input, the mask unit 1 masks the first 7 bits of the parallel signal 3 with “1” and “11111111”. Is output to the level detector 2 as the mask signal 5.

The level detector 2 performs an exclusive OR operation of “11111111” output as the mask signal 5 and the designation signal 8 indicating the “0” level, and the level “0” signal is added to the mask signal 5. Detect if it exists. However, the specified level “0” is assigned to “11111111”.
Is not present, the level detector 2 takes in the new parallel signal 3 and repeats the above-described series of detection processing.

As described above, in the present embodiment, 2
In 0/1 detection of an 8-bit parallel signal having three transition points, the transition point can be detected at four times the speed of the related art.

In the first embodiment, the parallel signal 3 is 2
Although the description has been made on the assumption that the signal is an 8-bit parallel signal having various change points, the present invention can also obtain the same effect in the case of n bits other than 8 bits.

When 0/1 detection of an n-bit parallel signal is performed, as shown in FIG. 3, the mask signal 5 is set to n bits for the n-bit parallel signal 3, and the position signal 6 is set to m (2 ^m ≧ n), it is possible to realize the same function as in the case of the 8-bit parallel signal described above.

[0025]

As described above, the 0/1 detection circuit of the present invention is n times faster than a conventional circuit for converting to a serial signal when there is no change point in the n-bit parallel signal. In addition, even when the change point is 所 (χ ≦ n), n /
It is possible to detect a change point at χ times speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional 0/1 detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mask part 2 Level detection part 3 Parallel signal 4 Level specification part 5 Mask signal 6 Position signal 7 Detection signal 8 Level specification signal 41 Parallel / serial converter 42 Holder 43 Exclusive OR circuit 44 Parallel signal 45, 46 Serial signal

Claims (1)

[Claims] A level designating unit for designating a detection signal level; a mask processing unit for masking a part of an input parallel signal with a signal level designated by the level designating unit to output a mask signal; A level detection unit that detects a bit signal of a signal level designated by the mask signal, and outputs a detection signal indicating a signal level change point of the mask signal and a position signal indicating a bit position of the signal level, The mask unit masks the input parallel signal up to the bit position indicated by the position signal, and the level designation unit inverts and outputs the level designation signal when the detection signal is input. 1
Detection circuit.