JPH06224653A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase a mutual conductance without increasing an input capacity by applying a voltage changing according to a change in a voltage applied to a gate terminal to a base terminal of a MOS transistor(TR). CONSTITUTION:An NMOS TR 1 has a drain terminal 1D, a gate terminal 1G, a source terminal 1S and a base terminal 1B, and a voltage application circuit 2a is connected between the gate terminal 1G and the base terminal 1B. Then a voltage changing according to a voltage applied to the gate terminal 1G is applied to the base terminal 1B. That is, a source-base voltage VSB changes according to a change in the gate source voltage VGS of the NMOS TR 1, the mutual conductance gm is increased when a gate-source voltage VGS, that is, a voltage applied to the gate terminal 1G is increased depending on the characteristic of the NMOS TR 1, and the mutual conductance gm is decreased when the voltage applied to the gate terminal 1G decreased on the other hand.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a MOS transistor.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, there is a circuit including a MOS transistor for amplifying a signal.

FIG. 18 is a circuit diagram of a conventional differential amplifier. A constant current source 3 for supplying a constant current to the circuit is connected to a power supply terminal 2 that receives a power supply voltage. A PMOS transistor 101 and a load 10 composed of an NMOS transistor are provided between the constant current source 3 and the ground terminal 4 which receives the ground voltage.
3 is connected in series, and the PMOS transistor 102 and the load 104 formed of an NMOS transistor are connected in series. A node between the PMOS transistor 101 and the load 103, and the load 103 and the load 10
4 are connected to respective gate terminals. Also PM
The gate terminals 101G and 102G of the OS transistors 101 and 102 are used as input terminals of the differential amplifier. Further, the output terminal 105 of the differential amplifier is connected to the node between the PMOS transistor 102 and the load 104.
Is provided.

Next, the operation will be described. Constant current source 3
Outputs a constant current. Gate terminal 101G, 10
An input voltage is externally applied to each of 2G.
The current output from the constant current source 3 is P that constitutes a differential pair.
By the MOS transistors 101 and 102, the loads 103 and 10 are loaded in accordance with the magnitude of the input voltage applied to them.
It is distributed to four. In the case of a differential pair of PMOS transistors, more current is distributed to the transistor with the lower input voltage. The output voltage value of the output terminal 105 is the load 1
The value is determined by the product of the current value distributed to the 04 side and the resistance value of the load 104. That is, the output voltage value is P
The voltage becomes a voltage according to the difference between the input voltages applied to the MOS transistors 101 and 102.

The gain of this differential amplifier is PMO.
It is represented by the product of the mutual conductance of the S transistors 101 and 102 and the output resistance of the loads 103 and 104.

In such a differential amplifier, in order to improve the performance, it is necessary to increase the sensitivity by increasing the gain. In order to increase the gain in this way, it was necessary to increase the value of the transconductance. As a method of increasing the mutual conductance, it has been conventionally considered to increase the size of the MOS transistors forming the differential pair.

[0007]

However, when the size of the MOS transistor is increased as described above, the MOS
There has been a problem that the input capacitance (parasitic capacitance of the gate) of the transistor increases, which causes the frequency characteristic to deteriorate.

The present invention has been made to solve such a problem, and it is an object of the present invention to provide a semiconductor integrated circuit capable of increasing the transconductance of a MOS transistor without increasing the input capacitance. To aim.

[0009]

The present invention according to claim 1 includes a MOS transistor and a voltage applying means.

In the MOS transistor, a variable voltage is applied to its gate terminal. The voltage applying means applies a voltage that changes according to a change in the voltage applied to the gate terminal to the substrate terminal of the MOS transistor.

The present invention according to claim 2 is a semiconductor integrated circuit for differentially amplifying two voltages, comprising a constant current source,
Load, second load, first MOS transistor, second
MOS transistor, first voltage applying means and second
Voltage applying means.

The first MOS transistor is connected between the constant current source and the first load, and a changeable first voltage is applied to its gate terminal.

The second MOS transistor is connected between the constant current source and the second load, and a changeable second voltage is applied to its gate terminal.

The first voltage applying means is the first MOS
A voltage that changes according to the change in the first voltage is applied to the substrate terminal of the first MOS transistor in response to the voltage of the node between the transistor and the first load.

The second voltage applying means is the second MOS.
A voltage that changes according to the change of the second voltage is applied to the substrate terminal of the second MOS transistor in response to the voltage of the node between the transistor and the second load.

The present invention according to claim 3 is a semiconductor integrated circuit for differentially amplifying two voltages, comprising a constant current source, a first
Load, second load, first MOS transistor, second
MOS transistor, first voltage applying means and second
Voltage applying means.

The first MOS transistor is connected between the constant current source and the first load, and a changeable first voltage is applied to its gate terminal.

The second MOS transistor is connected between the constant current source and the second load, and a changeable second voltage is applied to its gate terminal.

The first voltage applying means is the second MOS
A voltage that changes according to the change of the first voltage is applied to the substrate terminal of the first MOS transistor in response to the voltage of the node between the transistor and the second load.

The second voltage applying means is the first MOS
A voltage that changes according to the change of the second voltage is applied to the substrate terminal of the second MOS transistor in response to the voltage of the node between the transistor and the first load.

The present invention according to claim 4 provides the first MOS.
It includes a transistor, a second MOS transistor and voltage applying means.

A variable voltage is applied to the gate terminal of the first MOS transistor. The second MOS transistor is connected in parallel with the first MOS transistor.

The voltage applying means applies to the gate terminal of the second MOS transistor a voltage that changes according to a change in the voltage applied to the gate terminal of the first MOS transistor.

The present invention according to claim 5 is a semiconductor integrated circuit for differentially amplifying two voltages, comprising a constant current source, a first
Load, second load, first MOS transistor, second
MOS transistor, third MOS transistor, fourth MOS transistor, first voltage applying means, and second voltage applying means.

The first MOS transistor is connected between the constant current source and the first load, and a changeable first voltage is applied to its gate terminal. The second MOS transistor is connected between the constant current source and the second load, and a changeable second voltage is applied to its gate terminal.

The third MOS transistor is connected in parallel with the first MOS transistor. 4th MOS
The transistor is connected in parallel with the second MOS transistor.

The first voltage applying means is the first MOS
A third transistor in response to a voltage at a node between the transistor and the third MOS transistor and the first load.
A voltage that changes according to the change in the first voltage is applied to the gate terminal of the MOS transistor.

The second voltage applying means is the second MOS.
A fourth transistor in response to a voltage at a node between the transistor and the fourth MOS transistor and the second load.
A voltage that changes according to the change in the second voltage is applied to the gate terminal of the MOS transistor.

The present invention according to claim 6 is a semiconductor integrated circuit for differentially amplifying two voltages, comprising: a power supply terminal;
Load, second load, first bipolar transistor,
It includes a second bipolar transistor, a third load, a fourth load, a first MOS transistor, a second MOS transistor, a first voltage applying means and a second voltage applying means.

The first bipolar transistor is connected between the power supply terminal and the first load, and a variable first voltage is applied to its base terminal. The second bipolar transistor is connected between the power supply terminal and the second load, and a second voltage that can change in phase opposite to the first voltage is applied to the base terminal of the second bipolar transistor.

The first MOS transistor is connected between the first bipolar transistor and the third load, and the voltage of the node between the second bipolar transistor and the second load has its gate. Applied to the terminals.

The second MOS transistor is connected between the second bipolar transistor and the fourth load, and the voltage of the node between the first bipolar transistor and the first load is applied to the gate of the second MOS transistor. Applied to the terminals.

The first voltage application means is responsive to the voltage of the node between the second bipolar transistor and the second load to connect the second bipolar transistor and the second bipolar transistor to the substrate terminal of the first MOS transistor. The second
Apply a voltage that varies as the voltage on the node changes during the load.

The second voltage application means is responsive to the voltage of the node between the first bipolar transistor and the first load to connect the first bipolar transistor and the first bipolar transistor to the substrate terminal of the second MOS transistor. The first
Apply a voltage that varies as the voltage on the node changes during the load.

[0035]

According to the present invention as set forth in claim 1, since a voltage varying according to the voltage applied to the gate terminal is applied to the substrate terminal of the MOS transistor, when the voltage of the gate terminal increases, As the voltage increases, the voltage at the gate terminal decreases and the voltage at the substrate terminal decreases.

For example, when this MOS transistor is an N-channel MOS transistor, as the voltage of the gate terminal increases, the current easily flows through the transistor, but with this, the voltage of the substrate terminal with respect to the voltage of the source terminal. The threshold voltage value decreases, which increases the transconductance.
Also, for example, when this MOS transistor is a P-channel MOS transistor, as the voltage at the gate terminal decreases, current easily flows through the MOS transistor, but with this, the voltage at the substrate terminal is greater than the voltage at the source terminal. As the threshold voltage decreases, the threshold voltage value decreases, which increases the transconductance.

According to the second aspect of the present invention, the first voltage applied to the gate terminal of the first MOS transistor and the second voltage applied to the gate terminal of the second MOS transistor. The current from the constant current source is distributed to the first load and the second load according to the difference of The current value of the current distributed to the first load side and the resistance value of the first load determine the voltage of the node between the first MOS transistor and the first load, and the second load side. The second MOS according to the current value of the current distributed to the second load and the resistance value of the second load.
The voltage at the node between the transistor and the second load is determined. Therefore, the voltage of the node between the first MOS transistor and the first load changes as the first voltage changes, while the voltage of the node between the second MOS transistor and the second load changes. The voltage will change as the second voltage changes.

The first voltage applying means applies a voltage that changes according to the change of the first voltage in response to the voltage of the node between the first MOS transistor and the first load to the first MOS.
Since the voltage is applied to the substrate terminal of the transistor, the first MOS
The voltage at the substrate terminal of the transistor changes according to the first voltage. The second voltage applying means applies to the substrate terminal of the second MOS transistor a voltage that changes according to the change in the second voltage in response to the voltage of the node between the second MOS transistor and the second load. Therefore, the voltage of the substrate terminal of the second MOS transistor changes according to the second voltage.

Therefore, the transconductance of the first MOS transistor and the second MOS transistor is increased by the same action as the MOS transistor of the first aspect of the invention.

According to the present invention described in claim 3, similarly to the present invention described in claim 2, the voltage of the node between the first MOS transistor and the first load is the first MOS transistor. Changes when the first voltage applied to the gate terminal of the second MOS transistor changes, while the voltage of the node between the second MOS transistor and the second load is applied to the gate terminal of the second MOS transistor. It changes when the second voltage changes.

The first voltage applying means applies a voltage that changes according to the first voltage in response to the voltage of the node between the second MOS transistor and the second load to the substrate terminal of the first MOS transistor. The voltage applied to the substrate terminal of the first MOS transistor changes according to the first voltage. The second voltage applying means is the first MO.
A voltage, which varies according to the second voltage, in response to the voltage of the node between the S transistor and the first load is changed to the second M voltage.
Since the voltage is applied to the substrate terminal of the OS transistor, the second M
The voltage applied to the substrate terminal of the OS transistor changes according to the second voltage.

Therefore, the mutual conductance of the first MOS transistor and the second MOS transistor increases due to the same action as the MOS transistor of the present invention according to claim 1.

According to the present invention of claim 4, in the two MOS transistors connected in parallel, the first M
When a voltage that changes according to the change in the voltage applied to the gate terminal of the OS transistor is applied to the gate terminal of the second MOS transistor, the gain constant of the pair of MOS transistors becomes the sum of the gain constants of the two MOS transistors. Therefore, the gain constant becomes larger than that of a single MOS transistor. MOS
In the transistor, since the magnitude of the gain constant and the magnitude of the mutual conductance are proportional to each other, the mutual conductance increases as the gain constant increases.

According to the fifth aspect of the present invention, the first transistor pair including the first MOS transistor and the third MOS transistor are connected in parallel, and the second MO transistor is connected.
A second transistor pair composed of an S transistor and a fourth MOS transistor is connected in parallel, and the current from the constant current source is applied to the gate terminal of the first MOS transistor forming the first transistor pair. Depending on the difference between the first voltage applied to the gate terminal of the second MOS transistor forming the second transistor pair and the second voltage applied to the gate terminal of the second MOS transistor forming the second transistor pair. It First
Voltage of the node distributed between the first MOS transistor and the first load is determined by the current value of the current distributed to the load side of the first load and the resistance value of the first load. The voltage value of the node between the second MOS transistor and the second load is determined by the current value of the distributed current and the resistance value of the second load.

Therefore, the voltage of the node between the first MOS transistor and the first load changes when the first voltage changes, while the voltage of the second MOS transistor and the second MOS transistor changes.
The voltage at the node to and from the load will change as the second voltage changes.

The first voltage applying means applies a voltage that changes according to the change of the first voltage in response to the voltage of the node between the first MOS transistor and the first load to the third MOS.
Since the voltage is applied to the gate terminal of the transistor, the transconductance of the first transistor pair is increased by the same operation as that of the present invention according to claim 4. Further, the second voltage applying means applies to the fourth MOS transistor a voltage that changes according to the change of the second voltage in response to the voltage of the node between the second MOS transistor and the second load. Therefore, the transconductance of the second transistor pair is increased by the same action as the invention of claim 4.

According to the sixth aspect of the present invention, the first voltage applied to the first MOS transistor and the second voltage applied to the second MOS transistor have opposite phases (complementary). ), The voltage at the node between the second MOS transistor and the second load is applied to the gate terminal of the first MOS transistor connected between the first bipolar transistor and the third load. Is applied, the difference between the voltage received from the first bipolar transistor side and the voltage at the gate terminal becomes large in the first MOS transistor. Therefore, the voltage of the node between the second bipolar transistor and the second load becomes higher than the first voltage and the second voltage. Due to the similar operation, the voltage of the node between the first bipolar transistor and the first load also becomes higher than the first voltage and the second voltage.

The voltage of the node between the second bipolar transistor and the second load is applied to the gate terminal of the first MOS transistor, and the first bipolar transistor is connected to the substrate terminal of the first MOS transistor. Transistor and first
Since a voltage that changes according to the change in the voltage of the node between the first and the second load is applied, the transconductance of the first MOS transistor is increased by the same operation as that of the present invention according to claim 1. The second MOS transistor is also the first
The mutual conductance is increased by the same action as that of the MOS transistor.

[0049]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a circuit diagram showing the structure of a semiconductor integrated circuit according to the first embodiment. The NMOS transistor 1 includes a drain terminal 1D, a gate terminal 1G, a source terminal 1S and a substrate terminal 1B. The voltage application circuit 2a is connected between the gate terminal 1G and the substrate terminal 1B.

FIG. 2 is a circuit diagram showing a detailed structure of the semiconductor integrated circuit of FIG. In the voltage applying circuit 2a,
An npn-type transistor 203 is provided between a power supply terminal 201 that receives a power supply voltage and a ground terminal 202 that receives a ground voltage.
And the constant current source 204 are connected in series. Also, the gate terminal 1G and the base of the transistor 203 are connected,
The substrate terminal 1B and the emitter of the transistor 203 are connected.

Next, the operation of the semiconductor integrated circuit shown in FIGS. 1 and 2 will be described. FIG. 3 is a graph showing the relationship between the gate-source voltage VGS and the source-substrate voltage VSB of the NMOS transistor 1 in the semiconductor integrated circuit shown in FIGS. 1 and 2, with the vertical axis representing the source-substrate voltage. VSB, gate-source voltage VG on the horizontal axis
The relationship between these voltages is shown by a solid line, and the relationship between these voltages when VSB = VGS is shown by a broken line. The substrate terminal 1B has an NMOS transistor 1
Transistor 20 than the gate-source voltage VGS of
A voltage reduced by the base-emitter voltage VBE of 3 is applied. Therefore, the source-substrate voltage VSB is
It changes according to the change of the gate-source voltage VGS.

Further, the MOS transistor has the following characteristics. For example, the NMOS transistor 1 has a property that a drain current easily flows when the gate-source voltage VGS increases. NM
The transconductance gm in the saturation region of the OS transistor 1 has a transistor gain constant β and a threshold voltage VT.
Depending on H and the gate-source voltage VGS, the following (1)
It is expressed like a formula.

Gm = β (VGS-VTH) (1) Further, the threshold voltage VTH in the above equation (1) is expressed by the following equation (2).

VTH = VT0 + γ (√ (2φf + VSB) −√ (2φf)) (2) where VT0 is the threshold voltage when the potential of the substrate terminal is equal to the potential of the source terminal, γ is the substrate constant, and φf is It is a constant determined by the impurity density of the substrate.

Further, from the equations (1) and (2), the mutual conductance gm is expressed by the following equation (3).

Gm = β (VGS-VT0-γ (√ (2φf + VSB) −√ (2φf))) (3) Therefore, when the source-substrate voltage VSB increases, the threshold voltage VTH decreases, which causes The mutual conductance gm increases.

Here, when the mutual conductance when the potential of the substrate terminal is equal to the potential of the source terminal is gm0, the ratio (gm / gm0) between this mutual conductance gm0 and the mutual conductance gm of the equation (3) is Is expressed by the following equation (4).

(Gm / gm0) = (VGS-VT0-γ (√ (2φf + VSB) −√ (2φf))) / (VGS-VT0) (4) In the equation (4), for example, VGS = 1. .2V,
When VT0 = 0.7V, γ = 0.4, φ = 0.3 and the source-substrate voltage VSB is changed, the source-substrate voltage VSB and the transconductance ratio gm / gm0 are shown in FIG. The relationship is as shown in.

FIG. 4 is a graph showing the relationship between the source-substrate voltage VSB and the transconductance ratio (gm / gm0), where the ordinate represents the transconductance ratio (gm / gm).
m0), and the horizontal axis represents the source-substrate voltage VSB, and the relationship between them is shown.

As is apparent from FIG. 4, the NMOS transistor 1 has a characteristic that the mutual conductance gm increases as the source-substrate voltage VSB increases.

As described above, in the NMOS transistor 1, the source-substrate voltage VSB changes according to the change in the gate-source voltage VGS.
Due to the characteristics of the S transistor, the gate-source voltage V
GS, that is, the transconductance gm increases when the voltage applied to the gate terminal 1G increases, while the transconductance gm decreases when the voltage applied to the gate terminal 1G decreases. As a result, in the semiconductor integrated circuit of the first embodiment, it is possible to increase the mutual conductance gm without increasing the input capacitance of the NMOS transistor 1.

The PMOS transistor is an NMOS
Only the conductivity is different from the transistor, and it has the same characteristics as the NMOS transistor described above.

Although the circuit shown in FIG. 2 is used as the voltage applying circuit 2a in the first embodiment described above,
Not limited to this, the voltage application circuit 2a uses a pnp-type transistor so that the source-substrate voltage VSB becomes higher than the gate-source voltage VGS by the base-emitter voltage VBE. May be level-shifted, or the gate terminal 1G and the substrate terminal 1B may be directly connected to each other so that the source-substrate voltage VSB and the gate-source voltage VGS become equal. May be.

Second Embodiment Next, a second embodiment will be described. In the above-described first embodiment, the semiconductor integrated circuit including the N-channel type MOS transistor has been described, but in the second embodiment, the same principle as that described in the first embodiment is applied to the P-channel type MOS transistor. This is an example applied to a semiconductor integrated circuit including a transistor.

FIG. 5 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the second embodiment. PMOS transistor 10
Includes a drain terminal 10D, a gate terminal 10G, a source terminal 10S and a substrate terminal 10B. Voltage application circuit 2
b is connected between the gate terminal 10G and the substrate terminal 10B.

The structure of the voltage application circuit 2b in the semiconductor integrated circuit of FIG. 5 is the circuit or the gate-source voltage VGS having the structure for directly applying the gate-source voltage VGS as described in the first embodiment. It is a circuit configured to apply a level shift.

Next, the operation of the semiconductor integrated circuit of FIG. 5 will be described. A voltage that changes according to a change in the voltage applied to the gate terminal 10G is applied to the substrate terminal 10B from the voltage application circuit 2b.

In the PMOS transistor 10, the NMOS
Contrary to the transistor 1, the drain current easily flows when the voltage applied to the gate terminal 10G decreases. Further, when the voltage applied to the substrate terminal 10B is decreased and the source-substrate voltage VSB is increased, the threshold voltage VTH is decreased, which increases the mutual conductance gm.

In the PMOS transistor 10, the source-substrate voltage VSB changes in accordance with the change in the voltage applied to the gate terminal 10G. Due to the characteristics of the PMOS transistor described above, the voltage applied to the gate terminal 10G changes. When it decreases, the transconductance gm increases, while when the voltage applied to the gate terminal 10G increases, the transconductance gm decreases. Therefore, in the semiconductor integrated circuit of the second embodiment, the transconductance gm is increased without increasing the input capacitance of the PMOS transistor 10.
Can be increased.

Third Embodiment Next, a third embodiment will be described. The third embodiment is a voltage application circuit 2 in the semiconductor integrated circuit according to the first embodiment.
The input signal to a is different from the signal from the gate terminal 1G, and the difference from the first embodiment will be described below.

FIG. 6 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the third embodiment. In FIG. 6, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The voltage application circuit 2c is connected between the input terminal 20 to which a predetermined signal is input and the substrate terminal 1B. The voltage applying circuit 2c includes, for example, a gate terminal 1G.
A signal that changes in a phase opposite to that of the voltage applied to is input. The voltage application circuit 2c is configured by a circuit that inverts an input signal and outputs a signal that changes in phase with the signal applied to the gate terminal 1G. Since a voltage that changes in accordance with the change in the voltage applied to the gate terminal 1G is applied from the voltage application circuit 2c to the substrate terminal 1B, this semiconductor integrated circuit has the same input capacitance as the first embodiment. It is possible to increase the mutual conductance gm of the NMOS transistor 1 without increasing it.

Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment is a voltage application circuit 2 in the semiconductor integrated circuit according to the second embodiment.
The input signal of b is made different from the signal from the gate terminal 10G, and the difference from the second embodiment will be described below.

FIG. 7 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the fourth embodiment. In FIG. 7, the same parts as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted.

The voltage application circuit 2d is connected between the input terminal 20 to which a predetermined signal is input and the substrate terminal 10B. The voltage applying circuit 2d includes, for example, a gate terminal 10
A signal that changes in the opposite phase to the change in the voltage applied to G is input. The voltage application circuit 2d is configured by a circuit that inverts an input signal and outputs a signal that changes in phase with the signal applied to the gate terminal 10G. Since a voltage that changes according to the change in the voltage applied to the gate terminal 10G is applied from the voltage applying circuit 2d to the substrate terminal 10B, this semiconductor integrated circuit operates according to the same principle as in the second embodiment. It is possible to increase the transconductance gm of the PMOS transistor 10 without increasing

In the above-mentioned third and fourth embodiments, the signals input to the voltage application circuits 2c and 2d are changed to the signal opposite to the signal applied to the gate terminals 1G and 10G, and the voltage is changed. Although the application circuits 2c and 2d invert the input signals and apply them to the substrate terminals 1B and 10B, the present invention is not limited to this, and signals input to the voltage application circuits 2c and 2d are applied to the gate terminals 1G and 10G. Alternatively, the voltage applying circuits 2c and 2d may apply the input signals to the substrate terminals 1B and 10B without inverting the input signals.

Fifth Embodiment Next, a fifth embodiment will be described. FIG. 8 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the fifth embodiment. A constant current source 3 that supplies a constant current is connected to a power supply terminal 2 that receives a power supply voltage. The PMOS transistor 11 and the load 51 are connected in series between the constant current source 3 and the ground terminal 4, and the PMOS transistor 12 and the load 52 are connected.
And are connected in series. PMOS transistors 11 and 1
The respective gate terminals 11G and 12G of 2 are input terminals of this semiconductor integrated circuit. An output terminal 61 is provided at a node between the PMOS transistor 11 and the load 51, and the output terminal 61 is provided at the node.
An output terminal 62 is provided at a node between and.

The differential amplifier 7 has its negative input terminal 7a connected to the node between the PMOS transistor 11 and the load 51, and its positive input terminal 7b connected to the node between the PMOS transistor 12 and the load 52. Connected. The positive output terminal 7c of the differential amplifier 7 is connected to the PMOS transistor 1
1 is connected to the board terminal 11 B and the output terminal 81.
The negative output terminal 7d of the differential amplifier 7 is connected to the substrate terminal 12B of the PMOS transistor 12 and the output terminal 82.

FIG. 9 is a circuit diagram showing a detailed description of the differential amplifier 7 of FIG. Between the power supply terminal 71 receiving the power supply voltage and the ground terminal 72 receiving the ground voltage, a resistor 73,
Bipolar transistor 75 and constant current source 77a are connected in series. A resistor 74 and a bipolar transistor 76 are connected in series between the power supply terminal 71 and the constant current source 77a. The base terminal of the bipolar transistor 75 is the negative side input terminal 7a, and
The base terminal of 6 is the positive side input terminal 7b. Power supply terminal 7
A bipolar transistor 78 is connected between 1 and the positive output terminal 7c, and a constant current source 77b is connected between the positive output terminal 7c and the ground terminal 72. A bipolar transistor 79 is connected between the power supply terminal 71 and the negative output terminal 7d, and a constant current source 77c is connected between the negative output terminal 7d and the ground terminal 72. Bipolar transistor 78
Of the base, resistor 73 and bipolar transistor 7
Nodes between 5 are connected. The base of bipolar transistor 79 is connected to the node between resistor 74 and bipolar transistor 76.

Next, the operation of the semiconductor integrated circuit shown in FIGS. 8 and 9 will be described. The constant current source 3 outputs a constant current. Input voltage V1 is applied to the gate terminal 11G.
Is applied, and the input voltage V2 is applied to the gate terminal 12G. The current output from the constant current source 3 is distributed to the loads 51 and 52 according to the difference between the input voltages V1 and V2 of the PMOS transistors 11 and 12 that form the differential pair. For PMOS transistors, more current is distributed to the transistor with the lower input voltage. The output voltage V3 of the output terminal 61 is a value determined by the product of the resistance value of the load 51 and the distributed current value, and the output voltage V4 of the output terminal 62 is the resistance value of the load 52 and the distributed current value. It is a value determined by the product.

Referring to FIG. 9, in differential amplifier 7, voltage V3 input to negative side input terminal 7a and positive side input terminal 7 are
A current is distributed to the resistors 73 and 74 according to the difference from the voltage V4 input to b. Then, the voltage applied to the base of the bipolar transistor 78 (the voltage of the node between the resistor 73 and the bipolar transistor 75) is determined by the voltage drop determined by the product of the resistance value of the resistor 73 and the distributed current value, The bipolar transistor 79 has a voltage drop determined by the product of the resistance value of the resistor 74 and the distributed current value.
The voltage (the voltage of the node between the resistor 74 and the bipolar transistor 76) applied to the base of is determined.

In accordance with the difference between the base voltages of the bipolar transistors 78 and 79 thus determined, the current is distributed to the constant current sources 77b and 77c which are loads. Then, the product of the resistance value of the constant current source 77b and the current value of the distributed current determines the output voltage V5 of the positive output terminal 7c, and the resistance value of the constant current source 77c and the current value of the distributed current. The output voltage V6 of the negative output terminal 7d is determined by the product of The output voltage V5 determined in this way is the PMOS transistor 1
1 is applied to the substrate terminal 11B, while the output voltage V6 is applied to the substrate terminal 12B of the PMOS transistor 12.

Specifically, for example, when the input voltage V1 decreases, the current distributed to the load 51 increases and the output voltage V3 increases. When the output voltage V3 increases, the gate voltage of the bipolar transistor 78 decreases, so that the current distributed to the constant current source 77b decreases and the output voltage V5 decreases. Therefore, the voltage applied to the substrate terminal 11B decreases. When the voltage applied to the substrate terminal 11B decreases, the source-substrate voltage VSB of the PMOS transistor 11 increases and the transconductance gm of the PMOS transistor 11 increases. On the other hand, when the input voltage V1 increases, the source-substrate voltage VSB decreases and PM
The mutual conductance gm of the OS transistor 11 decreases.

With respect to the PMOS transistor 12, the same operation as in the case of the above-described PMOS transistor 11 causes the mutual conductance of the PMOS transistor 12 to increase as the input voltage V2 decreases, resulting in an increase in the input voltage V2.
Increases, the transconductance gm of the PMOS transistor 12 decreases.

FIGS. 10A and 10B show input voltages V1,
It is a graph which shows the relationship of the difference of V2, and output voltage V3, V4, V5, V6. In FIG. 10A, the input voltage V
Shows the relationship between the difference between 1, V2 and the output voltage V3, V4,
FIG. 10B shows the relationship between the difference between the input voltages V1 and V2 and the output voltages V5 and V6.

As is apparent from FIG. 10A, the output voltage V3 increases as the input voltage V2 increases with respect to the input voltage V1, while the output voltage V3 increases with the input voltage V1 increasing with respect to the input voltage V2. V4 increases. Further, as is apparent from FIG. 10B, the output voltage V6 increases as the input voltage V2 increases with respect to the input voltage V1, while the output voltage V5 increases as the input voltage V1 increases with respect to the input voltage V2. To increase.

Sixth Embodiment Next, a sixth embodiment will be described. The sixth embodiment is a semiconductor configured to change the voltage applied to the respective substrate terminals 11B and 12B of the PMOS transistors 11 and 12 without using the differential amplifier 7 shown in FIG. 8 which represents the fifth embodiment. It is an integrated circuit. FIG. 11 is a circuit diagram showing the configuration of the semiconductor integrated circuit according to the sixth embodiment.
8 that correspond to those in FIG. 8 are assigned the same numbers and their explanations are omitted. The semiconductor integrated circuit of FIG. 11 does not use the differential amplifier 7 of FIG. 8 and does not use the node between the PMOS transistor 11 and the load 51 and the PMOS transistor 1.
2 is connected to the substrate terminal 12B of the PMOS transistor 12, and the node between the PMOS transistor 12 and the load 52 is connected to the substrate terminal 11B of the PMOS transistor 11.

Next, the operation of the semiconductor integrated circuit of FIG. 11 will be described. The voltage V3 at the node between the PMOS transistor 11 and the load 51 is directly applied to the substrate terminal 12B, and the voltage V4 at the node between the PMOS transistor 12 and the load 52 is directly applied to the substrate terminal 11B. . Therefore, when the output voltage V3 is increased by decreasing the input voltage V1 with respect to the input voltage V2, the output voltage V4 is decreased, so that the voltage applied to the substrate terminal 11B is decreased and the PMOS transistors 11 are connected to each other. The conductance gm increases. On the other hand, in this case, the board terminal 12
The voltage applied to B increases the output voltage V3, so
As a result, the transconductance gm of the PMOS transistor 12 decreases. Conversely, if the input voltage V1 is the input voltage V2
When the output voltage V3 decreases due to the increase, the output voltage V4 increases, so that the voltage applied to the substrate terminal 11B increases and the transconductance gm of the PMOS transistor 11 decreases. On the other hand, in this case, the voltage applied to the substrate terminal 12B decreases because the output voltage V3 decreases, and the transconductance gm of the PMOS transistor 12 increases.

As described above, in the semiconductor integrated circuit of the sixth embodiment, the transconductance gm can be increased for each of the PMOS transistors 11 and 12 without increasing the input capacitance.

Seventh Embodiment Next, a seventh embodiment will be described. FIG. 12 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the seventh embodiment.
NMOS transistor 13 and NMOS transistor 14
Are connected in parallel by connecting the drain terminals D to each other and the source terminals S to each other. A variable voltage is applied to the gate terminal 13G of the NMOS transistor 13. The voltage application circuit 2e includes an input terminal 20 and an NMO.
It is connected to the gate terminal 14G of the S transistor 14.

Next, the operation of the semiconductor integrated circuit of FIG. 12 will be described. A signal that changes in phase with the voltage applied to the gate terminal 13G of the PMOS transistor 13 is input to the voltage application circuit 2e via the input terminal 20. The voltage application circuit 2e outputs a voltage that changes according to the voltage applied to the gate terminal 13G in response to the input signal. As a result, the voltage VG that changes according to the change in the voltage applied to the gate terminal 13G of the PMOS transistor 13 is applied to the gate terminal 14G of the PMOS transistor 14.

As shown in FIG. 12, two NMOS transistors 13 and 14 are connected in parallel, and a voltage VG that changes according to the voltage applied to the gate terminal 13G of one NMOS transistor 13 is applied to the gate terminal 14G of the other NMOS transistor 14. When applied to, the two NMOS transistors 13 and 14 have the property of operating as if their respective gain constants β were added. Since the mutual conductance gm of the MOS transistor increases as the gain constant β increases as shown in the equation (1),
As described above, the two NMOS transistors 13 and 14 operate as if the respective gain constants β are added, so that the NMOS transistors 13 and 1 connected in parallel are
The mutual conductance gm of 4 is a value obtained by adding the mutual conductances gm.

The characteristic of the mutual conductance gm is shown in FIG.
3 shows. FIG. 13 is a graph showing the relationship between the voltage VG applied to one gate terminal 14G of the NMOS transistors 13 and 14 connected in parallel and the overall mutual conductance gm of the NMOS transistors 13 and 14.
The vertical axis represents the total transconductance gm, and the horizontal axis represents the voltage VG applied to one of the gate terminals 14G. The relationship between these is shown by a solid line and each NMO is shown.
Mutual conductance gm of the S transistors 13 and 14
1 and gm2 are indicated by broken lines. However, in FIG. 13, as an example, the mutual conductance gm1 of the NMOS transistor 13 is made constant, and the NMOS transistor 14 is
The characteristics when only the mutual conductance gm2 of is changed are shown.

When the voltage VG applied to the gate terminal 14G exceeds the threshold voltage VTH of the NMOS transistor 14, the mutual conductance gm2 of the NMOS transistor 14 increases. In this case, the overall transconductance gm becomes a value obtained by adding the transconductance gm2 of the NMOS transistor 14 to the transconductance gm1 of the NMOS transistor 13, and thus the overall transconductance gm increases as the transconductance gm2 increases.

As described above, the two NMOS transistors 13 and 14 are connected in parallel, and a voltage that changes according to the voltage applied to the gate terminal 13G of one NMOS transistor 13 is applied to the gate terminal 14G of the other NMOS transistor 14. Then, the sum of the transconductances of these NMOS transistors 13 and 14 becomes the total transconductance.
The transconductance of the OS transistor can be increased without increasing the input capacitance thereof.

Eighth Embodiment Next, an eighth embodiment will be described. FIG. 14 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the eighth embodiment.
PMOS transistor 15 and PMOS transistor 16
Are connected in parallel by connecting the drain terminals D to each other and the source terminals S to each other. A variable voltage is applied to the gate terminal 15G of the PMOS transistor 15. The voltage application circuit 2f includes an input terminal 20 and a PMO.
It is connected to the gate terminal 16G of the S transistor 16.

Next, the operation of the semiconductor integrated circuit of FIG. 14 will be described. This semiconductor integrated circuit is different from the semiconductor integrated circuit of the seventh embodiment shown in FIG. 12 only in the conductivity of the PMOS transistors 15 and 16, and the voltage applying circuit 2f is different from the voltage applying circuit 2e in FIG. Do the same. As a result, in this semiconductor integrated circuit, the gain constant β increases and the relative mutual conductance gm increases, as in the seventh embodiment. Therefore, the mutual conductance gm of the PMOS transistor can be increased without increasing the input capacitance of the PMOS transistor.

Ninth Embodiment Next, a ninth embodiment will be described. FIG. 15 is a circuit diagram showing the structure of the semiconductor integrated circuit according to the ninth embodiment.
A constant current source 31 and PMOS transistors 151, 161 connected in parallel are connected in series between a power supply terminal 21 receiving a power supply voltage and an output terminal 63. Output terminal 63
And the load 53 is connected between the ground terminal 4 and the ground terminal 4 which receives the ground potential. The PMOS transistors 152 and 162 connected in parallel are connected between the constant current source 31 and the output terminal 64. The load 54 is connected between the output terminal 64 and the ground terminal 4.

A load 55 is connected between the power supply terminal 22 and the output terminal 83, and an NMOS transistor 171 and an NMOS transistor 180 are connected in series between the output terminal 83 and the ground terminal 4. The load 56 is connected between the power supply terminal 23 and the output terminal 84, and the load 56 and the output terminal 84 are connected to each other.
An NMOS transistor 172 is connected between it and the MOS transistor 180.

Load 55 and NMOS transistor 17
1 is connected to the gate terminal of the PMOS transistor 161, and the node between the load 56 and the NMOS transistor 171 is connected to the PMOS transistor 16.
2 gate terminals are connected. The nodes of PMOS transistor 151 and load 53 are connected to the gate terminal of NMOS transistor 171, and the nodes of PMOS transistor 152 and load 54 are connected to the gate terminal of NMOS transistor 172. Also, NMOS
Gate terminal 151G of transistor 151 and NMO
A variable voltage is applied to the gate terminal 152G of the S-transistor 152. NMOS transistor 180
A clock signal φ having a predetermined frequency is applied to the gate terminal 180G.

Next, the operation of the semiconductor integrated circuit of FIG. 15 will be described. When the clock signal φ is at low level, the NMOS transistor 180 is turned off, so that PM
The voltage of each gate terminal of the OS transistors 161 and 162 becomes substantially equal to the power supply voltage, the PMOS transistors 161 and 162 are not activated, and only the PMOS transistors 151 and 152 have their respective gate terminals 151.
The current of the constant current source 31 is distributed to the loads 53 and 54 according to the difference between the input voltages V1 and V2 of G and 152G.

On the other hand, when the clock signal φ is at high level, the NMOS transistor 180 is turned on,
The NMOS transistors 171 and 172 form a differential pair to generate a voltage on the loads 55 and 56. The voltage V5 applied to the gate terminal of the PMOS transistor 161 is determined by the voltage drop due to the voltage generated in the load 5,
The voltage V6 applied to the gate terminal of the transistor 162
Is determined by the voltage drop due to the voltage generated in the load 56.

For example, when the input voltage V1 applied to the gate terminal 151G of the PMOS transistor 151 decreases, the current distributed to the load 53 increases due to the characteristics of the PMOS transistor, and the output applied to the gate terminal of the NMOS transistor 171 is increased. The voltage V3 increases. Then, the current flowing through the load 55 increases due to the characteristics of the NMOS transistor, and the voltage drop amount due to the load 55 increases,
The voltage V5 applied to the gate terminal of the PMOS transistor 161 decreases. On the other hand, when the input voltage V1 applied to the gate terminal 151G increases, the voltage V5 applied to the gate terminal of the PMOS transistor 161 increases. Operations similar to these operations also occur in the PMOS transistors 152 and 162.

That is, when the input voltage V1 (or V2) decreases, the output voltage V3 (or V4) increases and the output voltage V5 (or V6) decreases. On the other hand, when the input voltage V1 (or V2) increases, the output voltage V3 (or V4) decreases and the output voltage V5 (or V6) increases.

As described above, in the semiconductor integrated circuit of FIG. 15, the gate terminal 151G of the PMOS transistor 151 is used.
Since the voltage V5 that changes according to the input voltage V1 applied to the PMOS transistor 161 is applied to the gate terminal of the PMOS transistor 161, the overall transconductance of the PMOS transistors 151 and 161 increases as described in the eighth embodiment. . Similarly, since the voltage V6 that changes according to the input voltage V2 applied to the gate terminal 152G of the PMOS transistor 152 is applied to the gate of the PMOS transistor 162, the PMOS transistors 152 and 162 are applied as described in the eighth embodiment. The overall transconductance of is increased.

Next, the relationship between the input voltages V1 and V2 and the output voltages V3, V4, V5 and V6 in this semiconductor integrated circuit will be described. 16 (a) to 16 (d) are similar to FIG.
3 is a timing chart showing the relationship between input voltage and output voltage in the semiconductor integrated circuit of FIG. 16A shows a clock signal φ, FIG. 16B shows input voltages V1 and V2, and FIG.
6C shows a timing chart of the output voltages V3 and V4, and FIG. 16D shows a timing chart of the output voltages V5 and V6.

While the clock signal φ is at the low level L as shown in FIG. 16A, the input voltages V1 and V2 which are increasing or decreasing as shown in FIG. 16B are applied. In that case, the input voltages V1 and V2 are amplified,
It appears as output voltages V3 and V4 as shown in FIG. The semiconductor integrated circuit of FIG. 15 is usually used as a voltage comparator. In that case, the input voltages V1, V
It is necessary to output the output voltages V3 and V4 amplified in accordance with 2 as a digital signal that has been switched to a high level or a low level. However, the input voltage V1, V
When the difference between 2 is small, the output voltages V3 and V4 are not sufficiently amplified voltages. Therefore, when the clock signal φ becomes high level H, the output voltage V amplified to some extent
3 and V4 are input to the NMOS transistors 171 and 172, the output voltages V5 and V, whose potential difference is amplified, are output.
6 is generated, and its voltage is PMOS transistors 161,1
62 to the respective gate terminals.

Therefore, even when the clock signal φ is at the high level H, if the input voltages V1 and V2 are changing in the same direction as the period when the clock signal φ is at the low level L, the PMOS transistor 151 is changed. , 15
Since the mutual conductance gm of the PMOS transistors 161 and 162 acts as well as the mutual conductance gm of 2, the gain becomes large, and the output voltages V3 and V4 can be easily set to the high level H and the low level L.

In this semiconductor integrated circuit, the clock signal φ
Is high level H, the PMOS transistor 1
The voltage V5 applied to the gate terminal of 61 changes according to the input voltage V1 applied to the gate terminal 151G of the PMOS transistor 151. At the same time, the voltage V6 applied to the gate terminal of the PMOS transistor 162 changes according to the input voltage V2 applied to the gate terminal 152G of the PMOS transistor 152. This PMOS
The overall transconductance gm of the transistors 151 and 161 can be increased, and the overall transconductance gm of the PMOS transistors 152 and 162 can be increased. Therefore, the PMOS
The transconductance can be increased without increasing the input capacitance of each of the transistors 151 and 152.

Tenth Embodiment Next, a tenth embodiment will be described. FIG. 17 shows the first
It is a circuit diagram which shows the structure of the semiconductor integrated circuit by 0 Example. An npn-type bipolar transistor 9 is provided between a power supply terminal 2 receiving a power supply voltage and a ground terminal 4 receiving a ground voltage.
1. Level shift circuit 93 and constant current source 3 as a load
2 are connected in series. An npn-type bipolar transistor 92, a level shift circuit 94, and a constant current source 33 as a load are connected in series between the power supply terminal 2 and the ground terminal 4.

Between the node between the bipolar transistor 92 and the level shift circuit 94 and the ground terminal 4, P
The MOS transistor 17 and the load NMOS transistor 191 are connected in series. A PMOS transistor 18 and a load NMOS transistor 192 are connected in series between the node between the bipolar transistor 91 and the level shift circuit 93 and the ground terminal 4.

Base terminal 91b of bipolar transistor 91 and base terminal 92 of bipolar transistor 92
Signals that can change in opposite phase (complementary) are input to b. Further, the node between the bipolar transistor 92 and the level shift circuit 94 is connected to the substrate terminal 18B of the PMOS transistor 18. The node between the bipolar transistor 91 and the level shift circuit 93 is connected to the substrate terminal 17B of the PMOS transistor 17. Level shift circuit 93 and constant current source 32
Is connected to the gate terminal of the PMOS transistor 17, and the level shift circuit 94 and the constant current source 3 are connected.
The node between 3 and the gate terminal of the PMOS transistor 18 are connected. PMOS transistor 17 and N
A node between the MOS transistors 191 is connected to the gate terminal of the NMOS transistor 191 and the gate terminal of the NMOS transistor 192. The output terminal 65 is provided at a node between the PMOS transistor 18 and the NMOS transistor 192.

Next, the operation of the semiconductor integrated circuit of FIG. 17 will be described. Currents are distributed to the constant current sources 32 and 33 according to the difference between the input voltage applied to the base terminal 91b of the bipolar transistor 91 and the input voltage applied to the base terminal 92b of the bipolar transistor 92. Then, the product of the resistance value of each of the constant current sources 32 and 33 and the current distributed to each of them is used to calculate the PMOS transistor 1
The voltage applied to each gate terminal of 7 and 18 is determined. The level shift circuits 93 and 94 are PMOS
It functions to lower the voltage applied to the gate terminals of the transistors 17 and 18 to the level of the operating point of each transistor.

Since the source terminal of the PMOS transistor 17 is connected to the node between the bipolar transistor 92 and the level shift circuit 94, the voltage applied to the gate terminal and the source terminal of the PMOS transistor 17 are applied. Since the voltage changes in the opposite direction, the gate-source voltage increases. Also PM
Since the source terminal of the OS transistor 18 is connected to the node between the bipolar transistor 91 and the level shift circuit 93, the gate-source voltage becomes large as in the case of the PMOS transistor 17. Thus, since the gate-source voltages of the PMOS transistors 17 and 18 are large, the output voltage of the output terminal 65 greatly changes even when the difference between the input voltages of the bipolar transistors 91 and 92 is relatively small.

Further, since the voltage which changes according to the voltage applied to the gate terminal of the PMOS transistor 17 is applied to the substrate terminal 17B of the PMOS transistor 17, when the voltage applied to the gate terminal decreases, The transconductance gm increases. Also, PMO
Since a voltage that changes according to the voltage applied to the gate terminal of the PMOS transistor 18 is applied to the substrate terminal 18B of the S transistor 18, its transconductance g when the voltage applied to the gate terminal decreases.
m increases.

As described above, in the semiconductor integrated circuit of FIG. 17, the transconductance gm can be increased in the PMOS transistors 17 and 18 without increasing the input capacitance of each.

[0118]

According to the first aspect of the present invention, the voltage applying means changes the voltage applied to the substrate terminal according to the change in the voltage applied to the gate terminal of the MOS transistor. When the current flowing through the substrate is increased, the change in the voltage applied to the substrate terminal acts to reduce the threshold voltage value. Therefore, it is possible to increase the transconductance without increasing the input capacitance of the MOS transistor, which makes it possible to increase the gain of the circuit and operate the circuit at high speed.

According to the second aspect of the present invention, the voltage that changes according to the first voltage changes according to the difference between the first voltage and the second voltage by the first voltage applying means. The voltage is applied to the substrate terminal of the first MOS transistor in response to the voltage of the node between the first MOS transistor and the first load. Further, the voltage that changes according to the second voltage is changed between the second MOS transistor and the second load that changes according to the difference between the first voltage and the second voltage by the second voltage applying unit. The second MO in response to the voltage at the node
It is applied to the substrate terminal of the S-transistor. Therefore, in each of the first MOS transistor and the second MOS transistor, when the current flowing in the MOS transistor is increased, the change in the voltage applied to the substrate terminal reduces the threshold voltage to reduce the current. Since it works to promote the increase, it is possible to increase the transconductance without increasing the input capacitance thereof, thereby increasing the gain of the circuit and operating the circuit at high speed.

According to the third aspect of the present invention, the voltage that changes according to the first voltage changes according to the difference between the first voltage and the second voltage by the first voltage applying means. The voltage is applied to the substrate terminal of the first MOS transistor in response to the voltage of the node between the second MOS transistor and the second load. In addition, the voltage that changes according to the second voltage is changed between the first MOS transistor and the first load that changes according to the difference between the first voltage and the second voltage by the second voltage applying unit. The second MO in response to the voltage at the node
It is applied to the substrate terminal of the S-transistor. Therefore, in each of the first MOS transistor and the second MOS transistor, when the current flowing through the MOS transistor is increased, the change in the voltage applied to the substrate terminal reduces the threshold voltage to decrease the current. Since it works to promote the increase, it is possible to increase the transconductance without increasing the input capacitance thereof, thereby increasing the gain of the circuit and operating the circuit at high speed.

According to the present invention described in claim 4, in the two MOS transistors connected in parallel, the first M
Since the voltage that changes according to the change in the voltage applied to the gate terminal of the OS transistor is applied to the gate terminal of the second MOS transistor by the voltage applying means, the mutual conductance due to the parallel connection is the mutual conductance of the two MOS transistors. Since it is the sum of
The transconductance can be increased without increasing the input capacitance of the transistor, whereby the gain of the circuit can be increased and the circuit can be operated at high speed.

According to the fifth aspect of the present invention, a first MOS transistor and a third MOS transistor connected in parallel are provided.
In the transistor, a voltage that changes according to the voltage applied to the gate terminal of the first MOS transistor is applied to the gate terminal of the third MOS transistor by the first voltage applying means. In the second MOS transistor and the fourth MOS transistor connected in parallel, the voltage that changes according to the voltage applied to the gate terminal of the second MOS transistor is changed by the second voltage applying means to the fourth MOS transistor. Applied to the gate terminal of. For this reason, the mutual conductance due to the parallel connection of each set of these MOS transistors connected in parallel is the sum of the mutual conductances of the two MOS transistors, so that the mutual conductance is increased without increasing the input capacitance of the MOS transistor. Therefore, the gain of the circuit can be increased and the circuit can be operated at high speed.

According to the sixth aspect of the present invention, the voltage which changes according to the change of the voltage applied to the gate terminal of the first MOS transistor is changed by the first voltage applying means to the substrate of the first MOS transistor. Applied to the terminals.
Further, the voltage that changes according to the change in the voltage applied to the gate terminal of the second MOS transistor is applied to the substrate terminal of the second MOS transistor by the second voltage applying means. Therefore, in each of the first MOS transistor and the second MOS transistor, when the current flowing in the MOS transistor is increased, the change in the voltage applied to the substrate terminal reduces the threshold voltage to reduce the current. Since it works to promote the increase, it is possible to increase the transconductance without increasing the input capacitance thereof, thereby increasing the gain of the circuit and operating the circuit at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a detailed configuration of a semiconductor integrated circuit according to the first embodiment.

FIG. 3 is a graph showing the relationship between the gate-source voltage and the source-substrate voltage in the semiconductor integrated circuit shown in FIGS. 1 and 2.

FIG. 4 is a graph showing a relationship between a gate-source voltage of an NMOS transistor and a transconductance ratio.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth example.

FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fifth example.

9 is a circuit diagram showing a detailed configuration of the differential amplifier of FIG.

10 is a graph showing a relationship between an input voltage and an output voltage of the semiconductor integrated circuit of FIG.

FIG. 11 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment.

FIG. 12 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a seventh embodiment.

FIG. 13 is a graph showing the relationship between the voltage applied to one gate terminal of NMOS transistors connected in parallel and the relative transconductance.

FIG. 14 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to an eighth example.

FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a ninth embodiment.

16 is a timing chart showing the relationship between the input voltage and the output voltage in the semiconductor integrated circuit of FIG.

FIG. 17 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a tenth embodiment.

FIG. 18 is a circuit diagram of a conventional differential amplifier.

[Explanation of symbols]

1, 11-14, 151, 152, 161, 162 N
MOS transistor 3, 31, 32, 33 constant current source 10, 15-18, 171, 172 PMOS transistor 51, 52, 53, 54 load 1B, 10B-12B, 17B, 18B substrate terminal 1G, 10G-16G, 151G, 152G gate terminals 2a to 2f voltage application circuit

Claims (6)

[Claims] 1. A MOS transistor in which a variable voltage is applied to its gate terminal, and a voltage applying means for applying a voltage that changes in accordance with a change in the voltage applied to the gate terminal to a substrate terminal of the MOS transistor. A semiconductor integrated circuit provided. 2. A semiconductor integrated circuit for differentially amplifying two voltages, comprising a constant current source, a first load, a second load, and the constant current source and the first load. Connected between the constant current source and the second load, and a first MOS transistor to which a changeable first voltage is applied to its gate terminal and which can change to its gate terminal A second MOS transistor to which a second voltage is applied; and a substrate terminal of the first MOS transistor in response to a voltage of a node between the first MOS transistor and the first load. A first voltage applying unit that applies a voltage that changes according to a change in the first voltage; and a voltage of a node between the second MOS transistor and the second load, in response to the voltage of the second MOS transistor. The second voltage is applied to the substrate terminal. And a second voltage applying means for applying a voltage that varies according of semiconductor integrated circuits. 3. A semiconductor integrated circuit for differentially amplifying two voltages, comprising: a constant current source, a first load, a second load, and the constant current source and the first load. Connected between the constant current source and the second load, and a first MOS transistor to which a changeable first voltage is applied to its gate terminal and which can change to its gate terminal A second MOS transistor to which a second voltage is applied; and a substrate terminal of the first MOS transistor in response to a voltage of a node between the second MOS transistor and the second load. A first voltage applying unit that applies a voltage that changes according to a change in the first voltage; and a voltage of a node between the first MOS transistor and the first load, The second voltage is applied to the substrate terminal. And a second voltage applying means for applying a voltage that varies according of semiconductor integrated circuits. 4. A first MOS transistor to which a variable voltage is applied to a gate terminal, and a second MOS transistor connected in parallel with the first MOS transistor.
And a voltage that changes according to a change in the voltage applied to the gate terminal of the first MOS transistor.
A semiconductor integrated circuit comprising: a voltage applying unit that applies a voltage to a gate terminal of a transistor. 5. A semiconductor integrated circuit for differentially amplifying two voltages, comprising a constant current source, a first load, a second load, and the constant current source and the first load. Connected between the constant current source and the second load, and a first MOS transistor to which a changeable first voltage is applied to its gate terminal and which can change to its gate terminal A second MOS transistor to which a second voltage is applied, and a third MOS transistor connected in parallel with the first MOS transistor.
And a fourth MOS transistor connected in parallel with the second MOS transistor.
MOS transistor, the first MOS transistor and the third MOS transistor
First voltage applying means for applying a voltage that changes according to the change of the first voltage to the gate terminal of the third MOS transistor in response to the voltage of the node between the transistor and the first load, The second MOS transistor and the fourth MOS
Second voltage applying means for applying a voltage that changes according to the change of the second voltage to the gate terminal of the fourth MOS transistor in response to the voltage of the node between the transistor and the second load. A semiconductor integrated circuit provided. 6. A semiconductor integrated circuit for differentially amplifying two voltages, comprising: a power supply terminal, a first load, a second load, and a connection between the power supply terminal and the first load. And a first bipolar transistor to which a changeable first voltage is applied to its base terminal, and a first bipolar transistor connected between the power supply terminal and the second load, the base terminal being connected to the first voltage. A second bipolar transistor to which a second voltage that can change to an opposite phase is applied, a third load, a fourth load, and a connection between the first bipolar transistor and the third load. A first MOS transistor having a gate terminal applied with a voltage of a node between the second bipolar transistor and the second load; and between the second bipolar transistor and the fourth load. Connected to the A second MOS transistor having a gate terminal applied with a voltage of a node between the first bipolar transistor and the first load; and a node between the second bipolar transistor and the second load. First voltage applying means for applying a voltage that changes according to a change in a voltage of a node between the second bipolar transistor and the second load to a substrate terminal of the first MOS transistor in response to the voltage; The voltage of the node between the first bipolar transistor and the first load is applied to the substrate terminal of the second MOS transistor in response to the voltage of the node between the first bipolar transistor and the first load. And a second voltage applying unit that applies a voltage that changes according to the change of the semiconductor integrated circuit.